1 /**
2 * Freecale 85xx and 86xx Global Utilties register set
3 *
4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 #ifndef __ASM_POWERPC_FSL_GUTS_H__
16 #define __ASM_POWERPC_FSL_GUTS_H__
17 #ifdef __KERNEL__
18
19 /**
20 * Global Utility Registers.
21 *
22 * Not all registers defined in this structure are available on all chips, so
23 * you are expected to know whether a given register actually exists on your
24 * chip before you access it.
25 *
26 * Also, some registers are similar on different chips but have slightly
27 * different names. In these cases, one name is chosen to avoid extraneous
28 * #ifdefs.
29 */
30 struct ccsr_guts {
31 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
32 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
33 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
34 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
38 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
39 u8 res024[0x30 - 0x24];
40 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
41 u8 res034[0x40 - 0x34];
42 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
43 u8 res044[0x50 - 0x44];
44 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
45 u8 res054[0x60 - 0x54];
46 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
47 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
48 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
49 u8 res06c[0x70 - 0x6c];
50 __be32 devdisr; /* 0x.0070 - Device Disable Control */
51 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
52 u8 res078[0x7c - 0x78];
53 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
54 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
55 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
56 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
57 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
58 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
59 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
60 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
61 __be32 autorstsr; /* 0x.009c - Automatic reset status register */
62 __be32 pvr; /* 0x.00a0 - Processor Version Register */
63 __be32 svr; /* 0x.00a4 - System Version Register */
64 u8 res0a8[0xb0 - 0xa8];
65 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
66 u8 res0b4[0xc0 - 0xb4];
67 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
68 Called 'elbcvselcr' on 86xx SOCs */
69 u8 res0c4[0x224 - 0xc4];
70 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
71 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
72 u8 res22c[0x800 - 0x22c];
73 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
74 u8 res804[0x900 - 0x804];
75 __be32 ircr; /* 0x.0900 - Infrared Control Register */
76 u8 res904[0x908 - 0x904];
77 __be32 dmacr; /* 0x.0908 - DMA Control Register */
78 u8 res90c[0x914 - 0x90c];
79 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
80 u8 res918[0xb20 - 0x918];
81 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
82 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
83 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
84 u8 resb2c[0xe00 - 0xb2c];
85 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
86 u8 rese04[0xe10 - 0xe04];
87 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
88 u8 rese14[0xe20 - 0xe14];
89 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
90 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
91 u8 rese28[0xf04 - 0xe28];
92 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
93 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
94 u8 resf0c[0xf2c - 0xf0c];
95 __be32 itcr; /* 0x.0f2c - Internal transaction control register */
96 u8 resf30[0xf40 - 0xf30];
97 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
98 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
99 } __attribute__ ((packed));
100
101
102 /* Alternate function signal multiplex control */
103 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
104
105 #ifdef CONFIG_PPC_86xx
106
107 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
108 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
109
110 /*
111 * Set the DMACR register in the GUTS
112 *
113 * The DMACR register determines the source of initiated transfers for each
114 * channel on each DMA controller. Rather than have a bunch of repetitive
115 * macros for the bit patterns, we just have a function that calculates
116 * them.
117 *
118 * guts: Pointer to GUTS structure
119 * co: The DMA controller (0 or 1)
120 * ch: The channel on the DMA controller (0, 1, 2, or 3)
121 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
122 */
guts_set_dmacr(struct ccsr_guts __iomem * guts,unsigned int co,unsigned int ch,unsigned int device)123 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
124 unsigned int co, unsigned int ch, unsigned int device)
125 {
126 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
127
128 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
129 }
130
131 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
132 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
133 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
134 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
135 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
136 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
137 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
138 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
139 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
140 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
141 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
142 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
143 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
144 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
145 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
146 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
147
148 /*
149 * Set the DMA external control bits in the GUTS
150 *
151 * The DMA external control bits in the PMUXCR are only meaningful for
152 * channels 0 and 3. Any other channels are ignored.
153 *
154 * guts: Pointer to GUTS structure
155 * co: The DMA controller (0 or 1)
156 * ch: The channel on the DMA controller (0, 1, 2, or 3)
157 * value: the new value for the bit (0 or 1)
158 */
guts_set_pmuxcr_dma(struct ccsr_guts __iomem * guts,unsigned int co,unsigned int ch,unsigned int value)159 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
160 unsigned int co, unsigned int ch, unsigned int value)
161 {
162 if ((ch == 0) || (ch == 3)) {
163 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
164
165 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
166 }
167 }
168
169 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
170 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
171 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
172 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
173 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
174 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
175 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
176 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
177 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
178 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
179 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
180 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
181
182 #endif
183
184 #endif
185 #endif
186