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Searched refs:enable_reg (Results 1 – 25 of 45) sorted by relevance

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/linux-3.4.99/arch/arm/mach-ep93xx/
Dclock.c35 void __iomem *enable_reg; member
56 .enable_reg = EP93XX_SYSCON_DEVCFG,
63 .enable_reg = EP93XX_SYSCON_DEVCFG,
70 .enable_reg = EP93XX_SYSCON_DEVCFG,
91 .enable_reg = EP93XX_SYSCON_PWRCNT,
97 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
112 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
119 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
135 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
[all …]
/linux-3.4.99/arch/arm/mach-omap2/
Dclock2430_data.c141 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
152 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
317 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
360 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
427 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
446 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
596 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
625 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
[all …]
Dclock2420_data.c142 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
153 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
297 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
341 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
376 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
449 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
467 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
485 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
499 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
[all …]
Dclock3xxx_data.c208 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
545 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
658 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
761 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
848 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
875 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
900 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
1003 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
1136 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1212 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
[all …]
Dclock44xx_data.c61 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
81 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
632 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
890 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
1300 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1310 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1320 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1330 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1340 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1382 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
[all …]
Dclock.c153 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); in omap2_clk_dflt_find_companion()
178 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap2_clk_dflt_find_idlest()
200 if (unlikely(clk->enable_reg == NULL)) { in omap2_dflt_clk_enable()
206 v = __raw_readl(clk->enable_reg); in omap2_dflt_clk_enable()
211 __raw_writel(v, clk->enable_reg); in omap2_dflt_clk_enable()
212 v = __raw_readl(clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
224 if (!clk->enable_reg) { in omap2_dflt_clk_disable()
234 v = __raw_readl(clk->enable_reg); in omap2_dflt_clk_disable()
239 __raw_writel(v, clk->enable_reg); in omap2_dflt_clk_disable()
430 regval32 = __raw_readl(clk->enable_reg); in omap2_clk_disable_unused()
Dclock3517.c57 *idlest_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_idlest()
79 *other_reg = (__force void __iomem *)(clk->enable_reg); in am35xx_clk_find_companion()
111 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in am35xx_clk_ipss_find_idlest()
Dclock34xx.c49 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_ssi_find_idlest()
92 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_dss_usbhost_find_idlest()
133 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); in omap3430es2_clk_hsotgusb_find_idlest()
Dclkt_iclk.c32 r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_allow_idle()
44 r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); in omap2_clkt_iclk_deny_idle()
/linux-3.4.99/arch/arm/mach-omap1/
Dclock_data.c103 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
115 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
137 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
156 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
167 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
180 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
193 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
217 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
239 .enable_reg = DSP_IDLECT2,
251 .enable_reg = DSP_IDLECT2,
[all …]
Dclock.c45 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
334 val = __raw_readl(clk->enable_reg); in omap1_set_uart_rate()
341 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
361 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
401 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
457 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
464 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_enable_generic()
466 __raw_writel(regval32, clk->enable_reg); in omap1_clk_enable_generic()
[all …]
/linux-3.4.99/arch/arm/mach-pnx4008/
Dclock.c61 if (clk->enable_reg) in clk_reg_disable()
62 __raw_writel(__raw_readl(clk->enable_reg) & in clk_reg_disable()
63 ~(1 << clk->enable_shift), clk->enable_reg); in clk_reg_disable()
68 if (clk->enable_reg) in clk_reg_enable()
69 __raw_writel(__raw_readl(clk->enable_reg) | in clk_reg_enable()
70 (1 << clk->enable_shift), clk->enable_reg); in clk_reg_enable()
436 .enable_reg = OSC13CTRL_REG,
461 .enable_reg = PLLCTRL_REG,
477 .enable_reg = PWRCTRL_REG,
491 .enable_reg = USBCTRL_REG,
[all …]
/linux-3.4.99/arch/arm/mach-imx/
Dclock-imx21.c267 reg = __raw_readl(clk->enable_reg); in _clk_enable()
269 __raw_writel(reg, clk->enable_reg); in _clk_enable()
277 reg = __raw_readl(clk->enable_reg); in _clk_disable()
279 __raw_writel(reg, clk->enable_reg); in _clk_disable()
664 .enable_reg = CCM_PCCR_UART1_REG,
671 .enable_reg = CCM_PCCR_UART2_REG,
678 .enable_reg = CCM_PCCR_UART3_REG,
685 .enable_reg = CCM_PCCR_UART4_REG,
714 .enable_reg = CCM_PCCR_GPT1_REG,
721 .enable_reg = CCM_PCCR_GPT2_REG,
[all …]
Dclock-imx1.c70 reg = __raw_readl(clk->enable_reg); in _clk_enable()
72 __raw_writel(reg, clk->enable_reg); in _clk_enable()
81 reg = __raw_readl(clk->enable_reg); in _clk_disable()
83 __raw_writel(reg, clk->enable_reg); in _clk_disable()
134 .enable_reg = CCM_CSCR,
491 .enable_reg = SCM_GCCR,
501 .enable_reg = SCM_GCCR,
511 .enable_reg = SCM_GCCR,
521 .enable_reg = SCM_GCCR,
Dclock-mx51-mx53.c84 u32 reg = __raw_readl(clk->enable_reg); in _clk_ccgr_setclk()
89 __raw_writel(reg, clk->enable_reg); in _clk_ccgr_setclk()
831 .enable_reg = MXC_CCM_CCGR0,
849 .enable_reg = MXC_CCM_CCGR0,
858 .enable_reg = MXC_CCM_CCGR0,
867 .enable_reg = MXC_CCM_CCGR0,
874 .enable_reg = MXC_CCM_CCGR5,
891 .enable_reg = MXC_CCM_CCGR5,
937 .enable_reg = MXC_CCM_CCGR0,
994 .enable_reg = MXC_CCM_CCGR4,
[all …]
Dclock-imx31.c80 if (!clk->enable_reg) in cgr_enable()
83 reg = __raw_readl(clk->enable_reg); in cgr_enable()
85 __raw_writel(reg, clk->enable_reg); in cgr_enable()
94 if (!clk->enable_reg) in cgr_disable()
97 reg = __raw_readl(clk->enable_reg); in cgr_disable()
101 if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8) in cgr_disable()
104 __raw_writel(reg, clk->enable_reg); in cgr_disable()
447 .enable_reg = er, \
459 .enable_reg = er, \
/linux-3.4.99/arch/arm/mach-lpc32xx/
Dclock.c547 tmp = __raw_readl(clk->enable_reg); in local_onoff_enable()
554 __raw_writel(tmp, clk->enable_reg); in local_onoff_enable()
563 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
570 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
577 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
584 .enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
591 .enable_reg = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
598 .enable_reg = LPC32XX_CLKPWR_DEBUG_CTRL,
605 .enable_reg = LPC32XX_CLKPWR_DMA_CLK_CTRL,
613 .enable_reg = LPC32XX_CLKPWR_UART_CLK_CTRL,
[all …]
/linux-3.4.99/drivers/regulator/
Dtps6586x-regulator.c64 int enable_reg[2]; member
172 return tps6586x_set_bits(parent, ri->enable_reg[0], in tps6586x_regulator_enable()
181 return tps6586x_clr_bits(parent, ri->enable_reg[0], in tps6586x_regulator_disable()
192 ret = tps6586x_read(parent, ri->enable_reg[0], &reg_val); in tps6586x_regulator_is_enabled()
257 .enable_reg[0] = TPS6586X_SUPPLY##ereg0, \
259 .enable_reg[1] = TPS6586X_SUPPLY##ereg1, \
311 if (ri->enable_reg[0] == ri->enable_reg[1] && in tps6586x_regulator_preinit()
315 ret = tps6586x_read(parent, ri->enable_reg[0], &val1); in tps6586x_regulator_preinit()
319 ret = tps6586x_read(parent, ri->enable_reg[1], &val2); in tps6586x_regulator_preinit()
331 ret = tps6586x_set_bits(parent, ri->enable_reg[0], in tps6586x_regulator_preinit()
[all …]
Dmax8925-regulator.c47 int enable_reg; member
103 return max8925_set_bits(info->i2c, info->enable_reg, in max8925_enable()
114 return max8925_set_bits(info->i2c, info->enable_reg, in max8925_disable()
125 ret = max8925_reg_read(info->i2c, info->enable_reg); in max8925_is_enabled()
147 return max8925_set_bits(info->i2c, info->enable_reg, mask, data); in max8925_set_dvm_voltage()
199 .enable_reg = MAX8925_SDCTL##_id, \
217 .enable_reg = MAX8925_LDOCTL##_id, \
D88pm8607.c35 int enable_reg; member
305 return pm860x_set_bits(info->i2c, info->enable_reg, in pm8607_enable()
314 return pm860x_set_bits(info->i2c, info->enable_reg, in pm8607_disable()
323 ret = pm860x_reg_read(info->i2c, info->enable_reg); in pm8607_is_enabled()
352 .enable_reg = PM8607_##ereg, \
371 .enable_reg = PM8607_##ereg, \
/linux-3.4.99/drivers/input/misc/
Dsparcspkr.c22 void __iomem *enable_reg; member
126 outb(inb(info->enable_reg) | 3, info->enable_reg); in grover_spkr_event()
134 outb(inb_p(info->enable_reg) & 0xFC, info->enable_reg); in grover_spkr_event()
289 info->enable_reg = of_ioremap(&op->resource[3], 0, 1, "grover beep enable"); in grover_beep_probe()
290 if (!info->enable_reg) in grover_beep_probe()
303 of_iounmap(&op->resource[3], info->enable_reg, 1); in grover_beep_probe()
324 of_iounmap(&op->resource[3], info->enable_reg, 1); in grover_remove()
/linux-3.4.99/include/linux/
Dsh_clk.h51 void __iomem *enable_reg; member
108 .enable_reg = (void __iomem *)_enable_reg, \
118 .enable_reg = (void __iomem *)_reg, \
139 .enable_reg = (void __iomem *)_reg, \
150 .enable_reg = (void __iomem *)_reg, \
/linux-3.4.99/drivers/char/agp/
Damd-k7-agp.c211 u16 enable_reg; in amd_irongate_configure() local
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
236 enable_reg = (enable_reg | 0x0004); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
255 u16 enable_reg; in amd_irongate_cleanup() local
259 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
260 enable_reg = (enable_reg & ~(0x0004)); in amd_irongate_cleanup()
261 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
Dsworks-agp.c266 u8 enable_reg; in serverworks_configure() local
292 pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg); in serverworks_configure()
293 enable_reg |= 0x1; /* Agp Enable bit */ in serverworks_configure()
294 pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg); in serverworks_configure()
303 pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg); in serverworks_configure()
304 enable_reg &= ~0x3; in serverworks_configure()
305 pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg); in serverworks_configure()
307 pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg); in serverworks_configure()
308 enable_reg |= (1<<6); in serverworks_configure()
309 pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg); in serverworks_configure()
/linux-3.4.99/arch/arm/mach-mxs/
Dclock-mx23.c44 if (clk->enable_reg) { in _raw_clk_enable()
45 reg = __raw_readl(clk->enable_reg); in _raw_clk_enable()
47 __raw_writel(reg, clk->enable_reg); in _raw_clk_enable()
57 if (clk->enable_reg) { in _raw_clk_disable()
58 reg = __raw_readl(clk->enable_reg); in _raw_clk_disable()
60 __raw_writel(reg, clk->enable_reg); in _raw_clk_disable()
137 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
388 .enable_reg = DIGCTRL_BASE_ADDR,
397 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \

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