Searched refs:ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT (Results 1 – 1 of 1) sorted by relevance
450 #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17 macro451 …rcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)