Searched refs:dct_sel_lo (Results 1 – 2 of 2) sorted by relevance
236 #define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)237 #define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)238 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))239 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))241 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))243 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))244 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))366 u32 dct_sel_lo; /* DRAM Controller Select Low */ member
1271 if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()1273 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()1303 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()