Searched refs:crtc_offset_cntl (Results 1 – 4 of 4) sorted by relevance
373 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; in radeon_crtc_do_set_base() local468 crtc_offset_cntl = 0; in radeon_crtc_do_set_base()476 crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; in radeon_crtc_do_set_base()479 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | in radeon_crtc_do_set_base()483 crtc_offset_cntl |= RADEON_CRTC_TILE_EN; in radeon_crtc_do_set_base()486 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | in radeon_crtc_do_set_base()490 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; in radeon_crtc_do_set_base()501 crtc_offset_cntl |= (y % 16); in radeon_crtc_do_set_base()548 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); in radeon_crtc_do_set_base()
98 u32 crtc_offset_cntl; member
1264 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); in r128_do_init_pageflip()1268 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); in r128_do_init_pageflip()1283 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); in r128_do_cleanup_pageflip()
191 u32 crtc_offset_cntl; member