Searched refs:clk_upll (Results 1 – 10 of 10) sorted by relevance
46 if (parent == &clk_upll) in s3c24xx_dclk_setparent()134 else if (parent == &clk_upll) in s3c24xx_clkout_setparent()
52 clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), in s3c24xx_setup_clocks()
205 clk_upll.enable = s3c2410_upll_enable; in s3c2410_baseclk_add()
231 struct clk clk_upll = { variable263 .parent = &clk_upll,370 if (s3c24xx_register_clock(&clk_upll) < 0) in s3c24xx_register_baseclocks()
110 else if (parent == &clk_upll) in s3c2412_setparent_usysclk()586 .src_1 = &clk_upll,676 clk_upll.enable = s3c2412_upll_enable; in s3c2412_baseclk_add()711 clk_set_parent(&clk_usysclk, &clk_upll); in s3c2412_baseclk_add()718 print_mhz(clk_get_rate(&clk_upll)), in s3c2412_baseclk_add()
381 s3c24xx_dclk0.parent = &clk_upll; in osiris_map_io()384 s3c24xx_dclk1.parent = &clk_upll; in osiris_map_io()
441 s3c24xx_dclk0.parent = &clk_upll; in anubis_map_io()444 s3c24xx_dclk1.parent = &clk_upll; in anubis_map_io()
595 s3c24xx_dclk0.parent = &clk_upll; in bast_map_io()598 s3c24xx_dclk1.parent = &clk_upll; in bast_map_io()
343 s3c24xx_dclk0.parent = &clk_upll; in vr1000_map_io()
77 extern struct clk clk_upll;