Searched refs:clk_bypass (Results 1 – 7 of 7) sorted by relevance
| /linux-3.4.99/arch/arm/mach-omap2/ |
| D | clkt_dpll.c | 209 clk_reparent(clk, dd->clk_bypass); in omap2_init_dpll_parent()
213 clk_reparent(clk, dd->clk_bypass); in omap2_init_dpll_parent()
218 clk_reparent(clk, dd->clk_bypass); in omap2_init_dpll_parent()
255 return dd->clk_bypass->rate; in omap2_get_dpll_rate()
259 return dd->clk_bypass->rate; in omap2_get_dpll_rate()
264 return dd->clk_bypass->rate; in omap2_get_dpll_rate()
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| D | dpll3xxx.c | 381 if (clk->rate == dd->clk_bypass->rate) { in omap3_noncore_dpll_enable()
382 WARN_ON(clk->parent != dd->clk_bypass); in omap3_noncore_dpll_enable()
449 omap2_clk_enable(dd->clk_bypass); in omap3_noncore_dpll_set_rate()
452 if (dd->clk_bypass->rate == rate && in omap3_noncore_dpll_set_rate()
458 new_parent = dd->clk_bypass; in omap3_noncore_dpll_set_rate()
497 omap2_clk_disable(dd->clk_bypass); in omap3_noncore_dpll_set_rate()
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| D | clock44xx_data.c | 254 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
430 .clk_bypass = &core_hsd_byp_clk_mux_ck,
668 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
736 .clk_bypass = &div_mpu_hs_clk,
809 .clk_bypass = &per_hsd_byp_clk_mux_ck,
953 .clk_bypass = &usb_hs_clk_div_ck,
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| D | clock3xxx_data.c | 280 .clk_bypass = &dpll1_fck,
351 .clk_bypass = &dpll2_fck,
412 .clk_bypass = &sys_ck,
569 .clk_bypass = &sys_ck,
591 .clk_bypass = &sys_ck,
923 .clk_bypass = &sys_ck,
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| D | clock2420_data.c | 112 .clk_bypass = &sys_ck,
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| D | clock2430_data.c | 111 .clk_bypass = &sys_ck,
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| /linux-3.4.99/arch/arm/plat-omap/include/plat/ |
| D | clock.h | 148 struct clk *clk_bypass; member
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