Searched refs:chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (Results 1 – 3 of 3) sorted by relevance
192 chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; in chipcHw_pll1Enable()
83 (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS * in chipcHw_getClockFrequency()285 (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS * in chipcHw_setClockFrequency()
209 #define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max f… macro