Searched refs:chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE (Results 1 – 2 of 2) sorted by relevance
1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; in chipcHw_ddrSwPhaseAlignEnable()1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; in chipcHw_ddrSwPhaseAlignDisable()
473 #define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment… macro