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/linux-3.4.99/arch/arm/mm/
Dtlb-v7.S50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
Dtlb-v6.S48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
Dtlb-v4wb.S40 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
43 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dtlb-v4wbi.S42 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
43 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
Dproc-arm720.S82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
126 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
154 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
Dproc-sa110.S71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
170 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
Dproc-sa1100.S79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
209 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dtlb-fa.S45 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
Dproc-fa526.S66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
119 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
148 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dtlb-v4.S40 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
Dproc-arm920.S94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
364 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
398 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
417 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dabort-ev7.S39 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
Dproc-arm926.S86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
377 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
413 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-mohawk.S77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
331 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
354 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
Dproc-xscale.S150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
474 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
544 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
563 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
Dproc-arm1026.S93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
375 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
404 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-arm922.S96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-arm1022.S93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
386 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
414 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-arm1020e.S104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
404 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-xsc3.S121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
367 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
433 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
455 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
Dproc-arm1020.S104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
420 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Dproc-arm925.S126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
416 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
454 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
/linux-3.4.99/fs/cifs/
Dsmbencrypt.c116 E_P24(unsigned char *p21, const unsigned char *c8, unsigned char *p24) in E_P24() argument
120 rc = smbhash(p24, c8, p21); in E_P24()
123 rc = smbhash(p24 + 8, c8, p21 + 7); in E_P24()
126 rc = smbhash(p24 + 16, c8, p21 + 14); in E_P24()
182 SMBencrypt(unsigned char *passwd, const unsigned char *c8, unsigned char *p24) in SMBencrypt() argument
197 rc = E_P24(p21, c8, p24); in SMBencrypt()
230 SMBNTencrypt(unsigned char *passwd, unsigned char *c8, unsigned char *p24, in SMBNTencrypt() argument
245 rc = E_P24(p21, c8, p24); in SMBNTencrypt()
/linux-3.4.99/arch/arm/mach-iop32x/include/mach/
Dentry-macro.S22 mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
/linux-3.4.99/arch/arm/boot/compressed/
Dhead.S35 mcr p14, 0, \ch, c8, c0, 0
627 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
636 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
649 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
677 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
682 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
959 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
975 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB

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