1 /* 2 * _tiomap.h 3 * 4 * DSP-BIOS Bridge driver support functions for TI OMAP processors. 5 * 6 * Definitions and types private to this Bridge driver. 7 * 8 * Copyright (C) 2005-2006 Texas Instruments, Inc. 9 * 10 * This package is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 17 */ 18 19 #ifndef _TIOMAP_ 20 #define _TIOMAP_ 21 22 /* 23 * XXX These powerdomain.h/clockdomain.h includes are wrong and should 24 * be removed. No driver should call pwrdm_* or clkdm_* functions 25 * directly; they should rely on OMAP core code to do this. 26 */ 27 #include <mach-omap2/powerdomain.h> 28 #include <mach-omap2/clockdomain.h> 29 /* 30 * XXX These mach-omap2/ includes are wrong and should be removed. No 31 * driver should read or write to PRM/CM registers directly; they 32 * should rely on OMAP core code to do this. 33 */ 34 #include <mach-omap2/cm2xxx_3xxx.h> 35 #include <mach-omap2/prm-regbits-34xx.h> 36 #include <mach-omap2/cm-regbits-34xx.h> 37 #include <dspbridge/devdefs.h> 38 #include <hw_defs.h> 39 #include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */ 40 #include <dspbridge/sync.h> 41 #include <dspbridge/clk.h> 42 43 struct map_l4_peripheral { 44 u32 phys_addr; 45 u32 dsp_virt_addr; 46 }; 47 48 #define ARM_MAILBOX_START 0xfffcf000 49 #define ARM_MAILBOX_LENGTH 0x800 50 51 /* New Registers in OMAP3.1 */ 52 53 #define TESTBLOCK_ID_START 0xfffed400 54 #define TESTBLOCK_ID_LENGTH 0xff 55 56 /* ID Returned by OMAP1510 */ 57 #define TBC_ID_VALUE 0xB47002F 58 59 #define SPACE_LENGTH 0x2000 60 #define API_CLKM_DPLL_DMA 0xfffec000 61 #define ARM_INTERRUPT_OFFSET 0xb00 62 63 #define BIOS24XX 64 65 #define L4_PERIPHERAL_NULL 0x0 66 #define DSPVA_PERIPHERAL_NULL 0x0 67 68 #define MAX_LOCK_TLB_ENTRIES 15 69 70 #define L4_PERIPHERAL_PRM 0x48306000 /*PRM L4 Peripheral */ 71 #define DSPVA_PERIPHERAL_PRM 0x1181e000 72 #define L4_PERIPHERAL_SCM 0x48002000 /*SCM L4 Peripheral */ 73 #define DSPVA_PERIPHERAL_SCM 0x1181f000 74 #define L4_PERIPHERAL_MMU 0x5D000000 /*MMU L4 Peripheral */ 75 #define DSPVA_PERIPHERAL_MMU 0x11820000 76 #define L4_PERIPHERAL_CM 0x48004000 /* Core L4, Clock Management */ 77 #define DSPVA_PERIPHERAL_CM 0x1181c000 78 #define L4_PERIPHERAL_PER 0x48005000 /* PER */ 79 #define DSPVA_PERIPHERAL_PER 0x1181d000 80 81 #define L4_PERIPHERAL_GPIO1 0x48310000 82 #define DSPVA_PERIPHERAL_GPIO1 0x11809000 83 #define L4_PERIPHERAL_GPIO2 0x49050000 84 #define DSPVA_PERIPHERAL_GPIO2 0x1180a000 85 #define L4_PERIPHERAL_GPIO3 0x49052000 86 #define DSPVA_PERIPHERAL_GPIO3 0x1180b000 87 #define L4_PERIPHERAL_GPIO4 0x49054000 88 #define DSPVA_PERIPHERAL_GPIO4 0x1180c000 89 #define L4_PERIPHERAL_GPIO5 0x49056000 90 #define DSPVA_PERIPHERAL_GPIO5 0x1180d000 91 92 #define L4_PERIPHERAL_IVA2WDT 0x49030000 93 #define DSPVA_PERIPHERAL_IVA2WDT 0x1180e000 94 95 #define L4_PERIPHERAL_DISPLAY 0x48050000 96 #define DSPVA_PERIPHERAL_DISPLAY 0x1180f000 97 98 #define L4_PERIPHERAL_SSI 0x48058000 99 #define DSPVA_PERIPHERAL_SSI 0x11804000 100 #define L4_PERIPHERAL_GDD 0x48059000 101 #define DSPVA_PERIPHERAL_GDD 0x11805000 102 #define L4_PERIPHERAL_SS1 0x4805a000 103 #define DSPVA_PERIPHERAL_SS1 0x11806000 104 #define L4_PERIPHERAL_SS2 0x4805b000 105 #define DSPVA_PERIPHERAL_SS2 0x11807000 106 107 #define L4_PERIPHERAL_CAMERA 0x480BC000 108 #define DSPVA_PERIPHERAL_CAMERA 0x11819000 109 110 #define L4_PERIPHERAL_SDMA 0x48056000 111 #define DSPVA_PERIPHERAL_SDMA 0x11810000 /* 0x1181d000 conflict w/ PER */ 112 113 #define L4_PERIPHERAL_UART1 0x4806a000 114 #define DSPVA_PERIPHERAL_UART1 0x11811000 115 #define L4_PERIPHERAL_UART2 0x4806c000 116 #define DSPVA_PERIPHERAL_UART2 0x11812000 117 #define L4_PERIPHERAL_UART3 0x49020000 118 #define DSPVA_PERIPHERAL_UART3 0x11813000 119 120 #define L4_PERIPHERAL_MCBSP1 0x48074000 121 #define DSPVA_PERIPHERAL_MCBSP1 0x11814000 122 #define L4_PERIPHERAL_MCBSP2 0x49022000 123 #define DSPVA_PERIPHERAL_MCBSP2 0x11815000 124 #define L4_PERIPHERAL_MCBSP3 0x49024000 125 #define DSPVA_PERIPHERAL_MCBSP3 0x11816000 126 #define L4_PERIPHERAL_MCBSP4 0x49026000 127 #define DSPVA_PERIPHERAL_MCBSP4 0x11817000 128 #define L4_PERIPHERAL_MCBSP5 0x48096000 129 #define DSPVA_PERIPHERAL_MCBSP5 0x11818000 130 131 #define L4_PERIPHERAL_GPTIMER5 0x49038000 132 #define DSPVA_PERIPHERAL_GPTIMER5 0x11800000 133 #define L4_PERIPHERAL_GPTIMER6 0x4903a000 134 #define DSPVA_PERIPHERAL_GPTIMER6 0x11801000 135 #define L4_PERIPHERAL_GPTIMER7 0x4903c000 136 #define DSPVA_PERIPHERAL_GPTIMER7 0x11802000 137 #define L4_PERIPHERAL_GPTIMER8 0x4903e000 138 #define DSPVA_PERIPHERAL_GPTIMER8 0x11803000 139 140 #define L4_PERIPHERAL_SPI1 0x48098000 141 #define DSPVA_PERIPHERAL_SPI1 0x1181a000 142 #define L4_PERIPHERAL_SPI2 0x4809a000 143 #define DSPVA_PERIPHERAL_SPI2 0x1181b000 144 145 #define L4_PERIPHERAL_MBOX 0x48094000 146 #define DSPVA_PERIPHERAL_MBOX 0x11808000 147 148 #define PM_GRPSEL_BASE 0x48307000 149 #define DSPVA_GRPSEL_BASE 0x11821000 150 151 #define L4_PERIPHERAL_SIDETONE_MCBSP2 0x49028000 152 #define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000 153 #define L4_PERIPHERAL_SIDETONE_MCBSP3 0x4902a000 154 #define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000 155 156 /* define a static array with L4 mappings */ 157 static const struct map_l4_peripheral l4_peripheral_table[] = { 158 {L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX}, 159 {L4_PERIPHERAL_SCM, DSPVA_PERIPHERAL_SCM}, 160 {L4_PERIPHERAL_MMU, DSPVA_PERIPHERAL_MMU}, 161 {L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5}, 162 {L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6}, 163 {L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7}, 164 {L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8}, 165 {L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1}, 166 {L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2}, 167 {L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3}, 168 {L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4}, 169 {L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5}, 170 {L4_PERIPHERAL_IVA2WDT, DSPVA_PERIPHERAL_IVA2WDT}, 171 {L4_PERIPHERAL_DISPLAY, DSPVA_PERIPHERAL_DISPLAY}, 172 {L4_PERIPHERAL_SSI, DSPVA_PERIPHERAL_SSI}, 173 {L4_PERIPHERAL_GDD, DSPVA_PERIPHERAL_GDD}, 174 {L4_PERIPHERAL_SS1, DSPVA_PERIPHERAL_SS1}, 175 {L4_PERIPHERAL_SS2, DSPVA_PERIPHERAL_SS2}, 176 {L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1}, 177 {L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2}, 178 {L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3}, 179 {L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1}, 180 {L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2}, 181 {L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3}, 182 {L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4}, 183 {L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5}, 184 {L4_PERIPHERAL_CAMERA, DSPVA_PERIPHERAL_CAMERA}, 185 {L4_PERIPHERAL_SPI1, DSPVA_PERIPHERAL_SPI1}, 186 {L4_PERIPHERAL_SPI2, DSPVA_PERIPHERAL_SPI2}, 187 {L4_PERIPHERAL_PRM, DSPVA_PERIPHERAL_PRM}, 188 {L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM}, 189 {L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER}, 190 {PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE}, 191 {L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2}, 192 {L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3}, 193 {L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL} 194 }; 195 196 /* 197 * 15 10 0 198 * --------------------------------- 199 * |0|0|1|0|0|0|c|c|c|i|i|i|i|i|i|i| 200 * --------------------------------- 201 * | (class) | (module specific) | 202 * 203 * where c -> Externel Clock Command: Clk & Autoidle Disable/Enable 204 * i -> External Clock ID Timers 5,6,7,8, McBSP1,2 and WDT3 205 */ 206 207 /* MBX_PM_CLK_IDMASK: DSP External clock id mask. */ 208 #define MBX_PM_CLK_IDMASK 0x7F 209 210 /* MBX_PM_CLK_CMDSHIFT: DSP External clock command shift. */ 211 #define MBX_PM_CLK_CMDSHIFT 7 212 213 /* MBX_PM_CLK_CMDMASK: DSP External clock command mask. */ 214 #define MBX_PM_CLK_CMDMASK 7 215 216 /* MBX_PM_MAX_RESOURCES: CORE 1 Clock resources. */ 217 #define MBX_CORE1_RESOURCES 7 218 219 /* MBX_PM_MAX_RESOURCES: CORE 2 Clock Resources. */ 220 #define MBX_CORE2_RESOURCES 1 221 222 /* MBX_PM_MAX_RESOURCES: TOTAL Clock Reosurces. */ 223 #define MBX_PM_MAX_RESOURCES 11 224 225 /* Power Management Commands */ 226 #define BPWR_DISABLE_CLOCK 0 227 #define BPWR_ENABLE_CLOCK 1 228 229 /* OMAP242x specific resources */ 230 enum bpwr_ext_clock_id { 231 BPWR_GP_TIMER5 = 0x10, 232 BPWR_GP_TIMER6, 233 BPWR_GP_TIMER7, 234 BPWR_GP_TIMER8, 235 BPWR_WD_TIMER3, 236 BPWR_MCBSP1, 237 BPWR_MCBSP2, 238 BPWR_MCBSP3, 239 BPWR_MCBSP4, 240 BPWR_MCBSP5, 241 BPWR_SSI = 0x20 242 }; 243 244 static const u32 bpwr_clkid[] = { 245 (u32) BPWR_GP_TIMER5, 246 (u32) BPWR_GP_TIMER6, 247 (u32) BPWR_GP_TIMER7, 248 (u32) BPWR_GP_TIMER8, 249 (u32) BPWR_WD_TIMER3, 250 (u32) BPWR_MCBSP1, 251 (u32) BPWR_MCBSP2, 252 (u32) BPWR_MCBSP3, 253 (u32) BPWR_MCBSP4, 254 (u32) BPWR_MCBSP5, 255 (u32) BPWR_SSI 256 }; 257 258 struct bpwr_clk_t { 259 u32 clk_id; 260 enum dsp_clk_id clk; 261 }; 262 263 static const struct bpwr_clk_t bpwr_clks[] = { 264 {(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5}, 265 {(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6}, 266 {(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7}, 267 {(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8}, 268 {(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3}, 269 {(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1}, 270 {(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2}, 271 {(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3}, 272 {(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4}, 273 {(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5}, 274 {(u32) BPWR_SSI, DSP_CLK_SSI} 275 }; 276 277 /* Interrupt Register Offsets */ 278 #define INTH_IT_REG_OFFSET 0x00 /* Interrupt register offset */ 279 #define INTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt reg offset */ 280 281 #define DSP_MAILBOX1_INT 10 282 /* 283 * Bit definition of Interrupt Level Registers 284 */ 285 286 /* Mail Box defines */ 287 #define MB_ARM2DSP1_REG_OFFSET 0x00 288 289 #define MB_ARM2DSP1B_REG_OFFSET 0x04 290 291 #define MB_DSP2ARM1B_REG_OFFSET 0x0C 292 293 #define MB_ARM2DSP1_FLAG_REG_OFFSET 0x18 294 295 #define MB_ARM2DSP_FLAG 0x0001 296 297 #define MBOX_ARM2DSP HW_MBOX_ID0 298 #define MBOX_DSP2ARM HW_MBOX_ID1 299 #define MBOX_ARM HW_MBOX_U0_ARM 300 #define MBOX_DSP HW_MBOX_U1_DSP1 301 302 #define ENABLE true 303 #define DISABLE false 304 305 #define HIGH_LEVEL true 306 #define LOW_LEVEL false 307 308 /* Macro's */ 309 #define CLEAR_BIT(reg, mask) (reg &= ~mask) 310 #define SET_BIT(reg, mask) (reg |= mask) 311 312 #define SET_GROUP_BITS16(reg, position, width, value) \ 313 do {\ 314 reg &= ~((0xFFFF >> (16 - (width))) << (position)) ; \ 315 reg |= ((value & (0xFFFF >> (16 - (width)))) << (position)); \ 316 } while (0); 317 318 #define CLEAR_BIT_INDEX(reg, index) (reg &= ~(1 << (index))) 319 320 /* This Bridge driver's device context: */ 321 struct bridge_dev_context { 322 struct dev_object *dev_obj; /* Handle to Bridge device object. */ 323 u32 dsp_base_addr; /* Arm's API to DSP virt base addr */ 324 /* 325 * DSP External memory prog address as seen virtually by the OS on 326 * the host side. 327 */ 328 u32 dsp_ext_base_addr; /* See the comment above */ 329 u32 api_reg_base; /* API mem map'd registers */ 330 void __iomem *dsp_mmu_base; /* DSP MMU Mapped registers */ 331 u32 api_clk_base; /* CLK Registers */ 332 u32 dsp_clk_m2_base; /* DSP Clock Module m2 */ 333 u32 public_rhea; /* Pub Rhea */ 334 u32 int_addr; /* MB INTR reg */ 335 u32 tc_endianism; /* TC Endianism register */ 336 u32 test_base; /* DSP MMU Mapped registers */ 337 u32 self_loop; /* Pointer to the selfloop */ 338 u32 dsp_start_add; /* API Boot vector */ 339 u32 internal_size; /* Internal memory size */ 340 341 struct omap_mbox *mbox; /* Mail box handle */ 342 343 struct cfg_hostres *resources; /* Host Resources */ 344 345 /* 346 * Processor specific info is set when prog loaded and read from DCD. 347 * [See bridge_dev_ctrl()] PROC info contains DSP-MMU TLB entries. 348 */ 349 /* DMMU TLB entries */ 350 struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB]; 351 u32 brd_state; /* Last known board state. */ 352 353 /* TC Settings */ 354 bool tc_word_swap_on; /* Traffic Controller Word Swap */ 355 struct pg_table_attrs *pt_attrs; 356 u32 dsp_per_clks; 357 }; 358 359 /* 360 * If dsp_debug is true, do not branch to the DSP entry 361 * point and wait for DSP to boot. 362 */ 363 extern s32 dsp_debug; 364 365 /* 366 * ======== sm_interrupt_dsp ======== 367 * Purpose: 368 * Set interrupt value & send an interrupt to the DSP processor(s). 369 * This is typically used when mailbox interrupt mechanisms allow data 370 * to be associated with interrupt such as for OMAP's CMD/DATA regs. 371 * Parameters: 372 * dev_context: Handle to Bridge driver defined device info. 373 * mb_val: Value associated with interrupt(e.g. mailbox value). 374 * Returns: 375 * 0: Interrupt sent; 376 * else: Unable to send interrupt. 377 * Requires: 378 * Ensures: 379 */ 380 int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val); 381 382 #endif /* _TIOMAP_ */ 383