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Searched refs:_reg (Results 1 – 25 of 37) sorted by relevance

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/linux-3.4.99/drivers/regulator/
Dmc13xxx.h68 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
78 .reg = prefix ## _reg, \
79 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
86 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
96 .reg = prefix ## _reg, \
97 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
101 #define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
111 .reg = prefix ## _reg, \
112 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
116 #define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \ argument
[all …]
Dmc13783-regulator.c185 #define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ argument
186 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
187 #define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \ argument
188 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
Dpcap-regulator.c109 #define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \ argument
111 .reg = _reg, \
/linux-3.4.99/arch/arm/mach-mmp/
Dclock.h31 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ argument
33 .clk_rst = APBC_##_reg, \
39 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ argument
41 .clk_rst = APBC_##_reg, \
47 #define APMU_CLK(_name, _reg, _eval, _rate) \ argument
49 .clk_rst = APMU_##_reg, \
55 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ argument
57 .clk_rst = APMU_##_reg, \
/linux-3.4.99/drivers/net/ethernet/xscale/ixp2000/
Dpm3386.c23 void *_reg; in pm3386_reg_read() local
26 _reg = (void *)ENP2611_PM3386_0_VIRT_BASE; in pm3386_reg_read()
28 _reg = (void *)ENP2611_PM3386_1_VIRT_BASE; in pm3386_reg_read()
30 value = *((volatile u16 *)(_reg + (reg << 1))); in pm3386_reg_read()
43 void *_reg; in pm3386_reg_write() local
48 _reg = (void *)ENP2611_PM3386_0_VIRT_BASE; in pm3386_reg_write()
50 _reg = (void *)ENP2611_PM3386_1_VIRT_BASE; in pm3386_reg_write()
52 *((volatile u16 *)(_reg + (reg << 1))) = value; in pm3386_reg_write()
54 dummy = *((volatile u16 *)_reg); in pm3386_reg_write()
62 static u16 pm3386_port_reg_read(int port, int _reg, int spacing) in pm3386_port_reg_read() argument
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/linux-3.4.99/drivers/media/common/tuners/
Dmc44s803_priv.h193 #define MC44S803_REG_SM(_val, _reg) \ argument
194 (((_val) << _reg##_S) & (_reg))
197 #define MC44S803_REG_MS(_val, _reg) \ argument
198 (((_val) & (_reg)) >> _reg##_S)
/linux-3.4.99/include/linux/
Dclk-private.h84 _flags, _reg, _bit_idx, \ argument
97 .reg = _reg, \
116 _flags, _reg, _shift, _width, \ argument
129 .reg = _reg, \
149 _reg, _shift, _width, \ argument
156 .reg = _reg, \
Dsh_clk.h115 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
118 .enable_reg = (void __iomem *)_reg, \
136 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
139 .enable_reg = (void __iomem *)_reg, \
147 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
150 .enable_reg = (void __iomem *)_reg, \
/linux-3.4.99/drivers/net/wireless/ath/ath5k/
Dath5k.h120 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
121 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
122 (((_val) << _flags##_S) & (_flags)), _reg)
124 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
126 (_mask)) | (_flags), _reg)
128 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
129 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
131 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ argument
132 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
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/linux-3.4.99/sound/soc/codecs/
Dadau1373.c463 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ argument
465 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
466 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
467 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
468 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
469 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
470 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
471 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
472 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
508 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ argument
[all …]
/linux-3.4.99/arch/arm/mach-ux500/
Dclock.h100 #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ argument
106 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
109 #define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ argument
116 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
/linux-3.4.99/drivers/net/ethernet/freescale/fs_enet/
Dmac-fec.c67 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) argument
70 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) argument
73 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) argument
76 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) argument
/linux-3.4.99/arch/mips/jz4740/
Dprom.c57 #define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2))) argument
/linux-3.4.99/arch/sh/kernel/cpu/sh4a/
Dclock-sh7366.c120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
140 #define MSTP(_parent, _reg, _bit, _flags) \ argument
141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7343.c117 #define DIV4(_reg, _bit, _mask, _flags) \ argument
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
137 #define MSTP(_parent, _reg, _bit, _flags) \ argument
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7722.c120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7723.c123 #define DIV4(_reg, _bit, _mask, _flags) \ argument
124 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux-3.4.99/arch/arm/mach-shmobile/
Dclock-sh7367.c179 #define DIV4(_reg, _bit, _mask, _flags) \ argument
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
228 #define MSTP(_parent, _reg, _bit, _flags) \ argument
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7377.c189 #define DIV4(_reg, _bit, _mask, _flags) \ argument
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
239 #define MSTP(_parent, _reg, _bit, _flags) \ argument
240 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh73a0.c263 #define DIV4(_reg, _bit, _mask, _flags) \ argument
264 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
486 #define MSTP(_parent, _reg, _bit, _flags) \ argument
487 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7372.c349 #define DIV4(_reg, _bit, _mask, _flags) \ argument
350 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
519 #define MSTP(_parent, _reg, _bit, _flags) \ argument
520 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
/linux-3.4.99/drivers/net/wireless/ath/ath9k/
Dhw.h72 #define REG_WRITE(_ah, _reg, _val) \ argument
73 (_ah)->reg_ops.write((_ah), (_val), (_reg))
75 #define REG_READ(_ah, _reg) \ argument
76 (_ah)->reg_ops.read((_ah), (_reg))
81 #define REG_RMW(_ah, _reg, _set, _clr) \ argument
82 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
/linux-3.4.99/drivers/mfd/
Drc5t583.c43 #define DEEPSLEEP_INIT(_id, _reg, _pos) \ argument
45 .reg_add = RC5T583_##_reg, \
Dtps65090.c47 #define TPS65090_IRQ(_reg, _mask_pos) \ argument
49 .mask_reg = (_reg), \
/linux-3.4.99/drivers/misc/
Dad525x_dpot.c506 #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \ argument
510 return sysfs_show_reg(dev, attr, buf, _reg); \
513 #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \ argument
518 return sysfs_set_reg(dev, attr, buf, count, _reg); \

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