1 /****************************************************************************
2  * Driver for Solarflare Solarstorm network controllers and boards
3  * Copyright 2005-2006 Fen Systems Ltd.
4  * Copyright 2006-2010 Solarflare Communications Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation, incorporated herein by reference.
9  */
10 
11 #ifndef EFX_REGS_H
12 #define EFX_REGS_H
13 
14 /*
15  * Falcon hardware architecture definitions have a name prefix following
16  * the format:
17  *
18  *     F<type>_<min-rev><max-rev>_
19  *
20  * The following <type> strings are used:
21  *
22  *             MMIO register  MC register  Host memory structure
23  * -------------------------------------------------------------
24  * Address     R              MCR
25  * Bitfield    RF             MCRF         SF
26  * Enumerator  FE             MCFE         SE
27  *
28  * <min-rev> is the first revision to which the definition applies:
29  *
30  *     A: Falcon A1 (SFC4000AB)
31  *     B: Falcon B0 (SFC4000BA)
32  *     C: Siena A0 (SFL9021AA)
33  *
34  * If the definition has been changed or removed in later revisions
35  * then <max-rev> is the last revision to which the definition applies;
36  * otherwise it is "Z".
37  */
38 
39 /**************************************************************************
40  *
41  * Falcon/Siena registers and descriptors
42  *
43  **************************************************************************
44  */
45 
46 /* ADR_REGION_REG: Address region register */
47 #define	FR_AZ_ADR_REGION 0x00000000
48 #define	FRF_AZ_ADR_REGION3_LBN 96
49 #define	FRF_AZ_ADR_REGION3_WIDTH 18
50 #define	FRF_AZ_ADR_REGION2_LBN 64
51 #define	FRF_AZ_ADR_REGION2_WIDTH 18
52 #define	FRF_AZ_ADR_REGION1_LBN 32
53 #define	FRF_AZ_ADR_REGION1_WIDTH 18
54 #define	FRF_AZ_ADR_REGION0_LBN 0
55 #define	FRF_AZ_ADR_REGION0_WIDTH 18
56 
57 /* INT_EN_REG_KER: Kernel driver Interrupt enable register */
58 #define	FR_AZ_INT_EN_KER 0x00000010
59 #define	FRF_AZ_KER_INT_LEVE_SEL_LBN 8
60 #define	FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
61 #define	FRF_AZ_KER_INT_CHAR_LBN 4
62 #define	FRF_AZ_KER_INT_CHAR_WIDTH 1
63 #define	FRF_AZ_KER_INT_KER_LBN 3
64 #define	FRF_AZ_KER_INT_KER_WIDTH 1
65 #define	FRF_AZ_DRV_INT_EN_KER_LBN 0
66 #define	FRF_AZ_DRV_INT_EN_KER_WIDTH 1
67 
68 /* INT_EN_REG_CHAR: Char Driver interrupt enable register */
69 #define	FR_BZ_INT_EN_CHAR 0x00000020
70 #define	FRF_BZ_CHAR_INT_LEVE_SEL_LBN 8
71 #define	FRF_BZ_CHAR_INT_LEVE_SEL_WIDTH 6
72 #define	FRF_BZ_CHAR_INT_CHAR_LBN 4
73 #define	FRF_BZ_CHAR_INT_CHAR_WIDTH 1
74 #define	FRF_BZ_CHAR_INT_KER_LBN 3
75 #define	FRF_BZ_CHAR_INT_KER_WIDTH 1
76 #define	FRF_BZ_DRV_INT_EN_CHAR_LBN 0
77 #define	FRF_BZ_DRV_INT_EN_CHAR_WIDTH 1
78 
79 /* INT_ADR_REG_KER: Interrupt host address for Kernel driver */
80 #define	FR_AZ_INT_ADR_KER 0x00000030
81 #define	FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
82 #define	FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
83 #define	FRF_AZ_INT_ADR_KER_LBN 0
84 #define	FRF_AZ_INT_ADR_KER_WIDTH 64
85 
86 /* INT_ADR_REG_CHAR: Interrupt host address for Char driver */
87 #define	FR_BZ_INT_ADR_CHAR 0x00000040
88 #define	FRF_BZ_NORM_INT_VEC_DIS_CHAR_LBN 64
89 #define	FRF_BZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
90 #define	FRF_BZ_INT_ADR_CHAR_LBN 0
91 #define	FRF_BZ_INT_ADR_CHAR_WIDTH 64
92 
93 /* INT_ACK_KER: Kernel interrupt acknowledge register */
94 #define	FR_AA_INT_ACK_KER 0x00000050
95 #define	FRF_AA_INT_ACK_KER_FIELD_LBN 0
96 #define	FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
97 
98 /* INT_ISR0_REG: Function 0 Interrupt Acknowledge Status register */
99 #define	FR_BZ_INT_ISR0 0x00000090
100 #define	FRF_BZ_INT_ISR_REG_LBN 0
101 #define	FRF_BZ_INT_ISR_REG_WIDTH 64
102 
103 /* HW_INIT_REG: Hardware initialization register */
104 #define	FR_AZ_HW_INIT 0x000000c0
105 #define	FRF_BB_BDMRD_CPLF_FULL_LBN 124
106 #define	FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
107 #define	FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
108 #define	FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
109 #define	FRF_CZ_TX_MRG_TAGS_LBN 120
110 #define	FRF_CZ_TX_MRG_TAGS_WIDTH 1
111 #define	FRF_AB_TRGT_MASK_ALL_LBN 100
112 #define	FRF_AB_TRGT_MASK_ALL_WIDTH 1
113 #define	FRF_AZ_DOORBELL_DROP_LBN 92
114 #define	FRF_AZ_DOORBELL_DROP_WIDTH 8
115 #define	FRF_AB_TX_RREQ_MASK_EN_LBN 76
116 #define	FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
117 #define	FRF_AB_PE_EIDLE_DIS_LBN 75
118 #define	FRF_AB_PE_EIDLE_DIS_WIDTH 1
119 #define	FRF_AA_FC_BLOCKING_EN_LBN 45
120 #define	FRF_AA_FC_BLOCKING_EN_WIDTH 1
121 #define	FRF_BZ_B2B_REQ_EN_LBN 45
122 #define	FRF_BZ_B2B_REQ_EN_WIDTH 1
123 #define	FRF_AA_B2B_REQ_EN_LBN 44
124 #define	FRF_AA_B2B_REQ_EN_WIDTH 1
125 #define	FRF_BB_FC_BLOCKING_EN_LBN 44
126 #define	FRF_BB_FC_BLOCKING_EN_WIDTH 1
127 #define	FRF_AZ_POST_WR_MASK_LBN 40
128 #define	FRF_AZ_POST_WR_MASK_WIDTH 4
129 #define	FRF_AZ_TLP_TC_LBN 34
130 #define	FRF_AZ_TLP_TC_WIDTH 3
131 #define	FRF_AZ_TLP_ATTR_LBN 32
132 #define	FRF_AZ_TLP_ATTR_WIDTH 2
133 #define	FRF_AB_INTB_VEC_LBN 24
134 #define	FRF_AB_INTB_VEC_WIDTH 5
135 #define	FRF_AB_INTA_VEC_LBN 16
136 #define	FRF_AB_INTA_VEC_WIDTH 5
137 #define	FRF_AZ_WD_TIMER_LBN 8
138 #define	FRF_AZ_WD_TIMER_WIDTH 8
139 #define	FRF_AZ_US_DISABLE_LBN 5
140 #define	FRF_AZ_US_DISABLE_WIDTH 1
141 #define	FRF_AZ_TLP_EP_LBN 4
142 #define	FRF_AZ_TLP_EP_WIDTH 1
143 #define	FRF_AZ_ATTR_SEL_LBN 3
144 #define	FRF_AZ_ATTR_SEL_WIDTH 1
145 #define	FRF_AZ_TD_SEL_LBN 1
146 #define	FRF_AZ_TD_SEL_WIDTH 1
147 #define	FRF_AZ_TLP_TD_LBN 0
148 #define	FRF_AZ_TLP_TD_WIDTH 1
149 
150 /* EE_SPI_HCMD_REG: SPI host command register */
151 #define	FR_AB_EE_SPI_HCMD 0x00000100
152 #define	FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
153 #define	FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
154 #define	FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
155 #define	FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
156 #define	FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
157 #define	FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
158 #define	FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
159 #define	FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
160 #define	FRF_AB_EE_SPI_HCMD_READ_LBN 15
161 #define	FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
162 #define	FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
163 #define	FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
164 #define	FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
165 #define	FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
166 #define	FRF_AB_EE_SPI_HCMD_ENC_LBN 0
167 #define	FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
168 
169 /* USR_EV_CFG: User Level Event Configuration register */
170 #define	FR_CZ_USR_EV_CFG 0x00000100
171 #define	FRF_CZ_USREV_DIS_LBN 16
172 #define	FRF_CZ_USREV_DIS_WIDTH 1
173 #define	FRF_CZ_DFLT_EVQ_LBN 0
174 #define	FRF_CZ_DFLT_EVQ_WIDTH 10
175 
176 /* EE_SPI_HADR_REG: SPI host address register */
177 #define	FR_AB_EE_SPI_HADR 0x00000110
178 #define	FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
179 #define	FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
180 #define	FRF_AB_EE_SPI_HADR_ADR_LBN 0
181 #define	FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
182 
183 /* EE_SPI_HDATA_REG: SPI host data register */
184 #define	FR_AB_EE_SPI_HDATA 0x00000120
185 #define	FRF_AB_EE_SPI_HDATA3_LBN 96
186 #define	FRF_AB_EE_SPI_HDATA3_WIDTH 32
187 #define	FRF_AB_EE_SPI_HDATA2_LBN 64
188 #define	FRF_AB_EE_SPI_HDATA2_WIDTH 32
189 #define	FRF_AB_EE_SPI_HDATA1_LBN 32
190 #define	FRF_AB_EE_SPI_HDATA1_WIDTH 32
191 #define	FRF_AB_EE_SPI_HDATA0_LBN 0
192 #define	FRF_AB_EE_SPI_HDATA0_WIDTH 32
193 
194 /* EE_BASE_PAGE_REG: Expansion ROM base mirror register */
195 #define	FR_AB_EE_BASE_PAGE 0x00000130
196 #define	FRF_AB_EE_EXPROM_MASK_LBN 16
197 #define	FRF_AB_EE_EXPROM_MASK_WIDTH 13
198 #define	FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
199 #define	FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
200 
201 /* EE_VPD_CFG0_REG: SPI/VPD configuration register 0 */
202 #define	FR_AB_EE_VPD_CFG0 0x00000140
203 #define	FRF_AB_EE_SF_FASTRD_EN_LBN 127
204 #define	FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
205 #define	FRF_AB_EE_SF_CLOCK_DIV_LBN 120
206 #define	FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
207 #define	FRF_AB_EE_VPD_WIP_POLL_LBN 119
208 #define	FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
209 #define	FRF_AB_EE_EE_CLOCK_DIV_LBN 112
210 #define	FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
211 #define	FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
212 #define	FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
213 #define	FRF_AB_EE_VPDW_LENGTH_LBN 80
214 #define	FRF_AB_EE_VPDW_LENGTH_WIDTH 15
215 #define	FRF_AB_EE_VPDW_BASE_LBN 64
216 #define	FRF_AB_EE_VPDW_BASE_WIDTH 15
217 #define	FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
218 #define	FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
219 #define	FRF_AB_EE_VPD_BASE_LBN 32
220 #define	FRF_AB_EE_VPD_BASE_WIDTH 24
221 #define	FRF_AB_EE_VPD_LENGTH_LBN 16
222 #define	FRF_AB_EE_VPD_LENGTH_WIDTH 15
223 #define	FRF_AB_EE_VPD_AD_SIZE_LBN 8
224 #define	FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
225 #define	FRF_AB_EE_VPD_ACCESS_ON_LBN 5
226 #define	FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
227 #define	FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
228 #define	FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
229 #define	FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
230 #define	FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
231 #define	FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
232 #define	FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
233 #define	FRF_AB_EE_VPD_EN_LBN 0
234 #define	FRF_AB_EE_VPD_EN_WIDTH 1
235 
236 /* EE_VPD_SW_CNTL_REG: VPD access SW control register */
237 #define	FR_AB_EE_VPD_SW_CNTL 0x00000150
238 #define	FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
239 #define	FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
240 #define	FRF_AB_EE_VPD_CYC_WRITE_LBN 28
241 #define	FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
242 #define	FRF_AB_EE_VPD_CYC_ADR_LBN 0
243 #define	FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
244 
245 /* EE_VPD_SW_DATA_REG: VPD access SW data register */
246 #define	FR_AB_EE_VPD_SW_DATA 0x00000160
247 #define	FRF_AB_EE_VPD_CYC_DAT_LBN 0
248 #define	FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
249 
250 /* PBMX_DBG_IADDR_REG: Capture Module address register */
251 #define	FR_CZ_PBMX_DBG_IADDR 0x000001f0
252 #define	FRF_CZ_PBMX_DBG_IADDR_LBN 0
253 #define	FRF_CZ_PBMX_DBG_IADDR_WIDTH 32
254 
255 /* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */
256 #define	FR_BB_PCIE_CORE_INDIRECT 0x000001f0
257 #define	FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
258 #define	FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
259 #define	FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
260 #define	FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
261 #define	FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
262 #define	FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
263 
264 /* PBMX_DBG_IDATA_REG: Capture Module data register */
265 #define	FR_CZ_PBMX_DBG_IDATA 0x000001f8
266 #define	FRF_CZ_PBMX_DBG_IDATA_LBN 0
267 #define	FRF_CZ_PBMX_DBG_IDATA_WIDTH 64
268 
269 /* NIC_STAT_REG: NIC status register */
270 #define	FR_AB_NIC_STAT 0x00000200
271 #define	FRF_BB_AER_DIS_LBN 34
272 #define	FRF_BB_AER_DIS_WIDTH 1
273 #define	FRF_BB_EE_STRAP_EN_LBN 31
274 #define	FRF_BB_EE_STRAP_EN_WIDTH 1
275 #define	FRF_BB_EE_STRAP_LBN 24
276 #define	FRF_BB_EE_STRAP_WIDTH 4
277 #define	FRF_BB_REVISION_ID_LBN 17
278 #define	FRF_BB_REVISION_ID_WIDTH 7
279 #define	FRF_AB_ONCHIP_SRAM_LBN 16
280 #define	FRF_AB_ONCHIP_SRAM_WIDTH 1
281 #define	FRF_AB_SF_PRST_LBN 9
282 #define	FRF_AB_SF_PRST_WIDTH 1
283 #define	FRF_AB_EE_PRST_LBN 8
284 #define	FRF_AB_EE_PRST_WIDTH 1
285 #define	FRF_AB_ATE_MODE_LBN 3
286 #define	FRF_AB_ATE_MODE_WIDTH 1
287 #define	FRF_AB_STRAP_PINS_LBN 0
288 #define	FRF_AB_STRAP_PINS_WIDTH 3
289 
290 /* GPIO_CTL_REG: GPIO control register */
291 #define	FR_AB_GPIO_CTL 0x00000210
292 #define	FRF_AB_GPIO_OUT3_LBN 112
293 #define	FRF_AB_GPIO_OUT3_WIDTH 16
294 #define	FRF_AB_GPIO_IN3_LBN 104
295 #define	FRF_AB_GPIO_IN3_WIDTH 8
296 #define	FRF_AB_GPIO_PWRUP_VALUE3_LBN 96
297 #define	FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8
298 #define	FRF_AB_GPIO_OUT2_LBN 80
299 #define	FRF_AB_GPIO_OUT2_WIDTH 16
300 #define	FRF_AB_GPIO_IN2_LBN 72
301 #define	FRF_AB_GPIO_IN2_WIDTH 8
302 #define	FRF_AB_GPIO_PWRUP_VALUE2_LBN 64
303 #define	FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8
304 #define	FRF_AB_GPIO15_OEN_LBN 63
305 #define	FRF_AB_GPIO15_OEN_WIDTH 1
306 #define	FRF_AB_GPIO14_OEN_LBN 62
307 #define	FRF_AB_GPIO14_OEN_WIDTH 1
308 #define	FRF_AB_GPIO13_OEN_LBN 61
309 #define	FRF_AB_GPIO13_OEN_WIDTH 1
310 #define	FRF_AB_GPIO12_OEN_LBN 60
311 #define	FRF_AB_GPIO12_OEN_WIDTH 1
312 #define	FRF_AB_GPIO11_OEN_LBN 59
313 #define	FRF_AB_GPIO11_OEN_WIDTH 1
314 #define	FRF_AB_GPIO10_OEN_LBN 58
315 #define	FRF_AB_GPIO10_OEN_WIDTH 1
316 #define	FRF_AB_GPIO9_OEN_LBN 57
317 #define	FRF_AB_GPIO9_OEN_WIDTH 1
318 #define	FRF_AB_GPIO8_OEN_LBN 56
319 #define	FRF_AB_GPIO8_OEN_WIDTH 1
320 #define	FRF_AB_GPIO15_OUT_LBN 55
321 #define	FRF_AB_GPIO15_OUT_WIDTH 1
322 #define	FRF_AB_GPIO14_OUT_LBN 54
323 #define	FRF_AB_GPIO14_OUT_WIDTH 1
324 #define	FRF_AB_GPIO13_OUT_LBN 53
325 #define	FRF_AB_GPIO13_OUT_WIDTH 1
326 #define	FRF_AB_GPIO12_OUT_LBN 52
327 #define	FRF_AB_GPIO12_OUT_WIDTH 1
328 #define	FRF_AB_GPIO11_OUT_LBN 51
329 #define	FRF_AB_GPIO11_OUT_WIDTH 1
330 #define	FRF_AB_GPIO10_OUT_LBN 50
331 #define	FRF_AB_GPIO10_OUT_WIDTH 1
332 #define	FRF_AB_GPIO9_OUT_LBN 49
333 #define	FRF_AB_GPIO9_OUT_WIDTH 1
334 #define	FRF_AB_GPIO8_OUT_LBN 48
335 #define	FRF_AB_GPIO8_OUT_WIDTH 1
336 #define	FRF_AB_GPIO15_IN_LBN 47
337 #define	FRF_AB_GPIO15_IN_WIDTH 1
338 #define	FRF_AB_GPIO14_IN_LBN 46
339 #define	FRF_AB_GPIO14_IN_WIDTH 1
340 #define	FRF_AB_GPIO13_IN_LBN 45
341 #define	FRF_AB_GPIO13_IN_WIDTH 1
342 #define	FRF_AB_GPIO12_IN_LBN 44
343 #define	FRF_AB_GPIO12_IN_WIDTH 1
344 #define	FRF_AB_GPIO11_IN_LBN 43
345 #define	FRF_AB_GPIO11_IN_WIDTH 1
346 #define	FRF_AB_GPIO10_IN_LBN 42
347 #define	FRF_AB_GPIO10_IN_WIDTH 1
348 #define	FRF_AB_GPIO9_IN_LBN 41
349 #define	FRF_AB_GPIO9_IN_WIDTH 1
350 #define	FRF_AB_GPIO8_IN_LBN 40
351 #define	FRF_AB_GPIO8_IN_WIDTH 1
352 #define	FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
353 #define	FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
354 #define	FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
355 #define	FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
356 #define	FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
357 #define	FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
358 #define	FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
359 #define	FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
360 #define	FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
361 #define	FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
362 #define	FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
363 #define	FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
364 #define	FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
365 #define	FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
366 #define	FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
367 #define	FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
368 #define	FRF_AB_CLK156_OUT_EN_LBN 31
369 #define	FRF_AB_CLK156_OUT_EN_WIDTH 1
370 #define	FRF_AB_USE_NIC_CLK_LBN 30
371 #define	FRF_AB_USE_NIC_CLK_WIDTH 1
372 #define	FRF_AB_GPIO5_OEN_LBN 29
373 #define	FRF_AB_GPIO5_OEN_WIDTH 1
374 #define	FRF_AB_GPIO4_OEN_LBN 28
375 #define	FRF_AB_GPIO4_OEN_WIDTH 1
376 #define	FRF_AB_GPIO3_OEN_LBN 27
377 #define	FRF_AB_GPIO3_OEN_WIDTH 1
378 #define	FRF_AB_GPIO2_OEN_LBN 26
379 #define	FRF_AB_GPIO2_OEN_WIDTH 1
380 #define	FRF_AB_GPIO1_OEN_LBN 25
381 #define	FRF_AB_GPIO1_OEN_WIDTH 1
382 #define	FRF_AB_GPIO0_OEN_LBN 24
383 #define	FRF_AB_GPIO0_OEN_WIDTH 1
384 #define	FRF_AB_GPIO7_OUT_LBN 23
385 #define	FRF_AB_GPIO7_OUT_WIDTH 1
386 #define	FRF_AB_GPIO6_OUT_LBN 22
387 #define	FRF_AB_GPIO6_OUT_WIDTH 1
388 #define	FRF_AB_GPIO5_OUT_LBN 21
389 #define	FRF_AB_GPIO5_OUT_WIDTH 1
390 #define	FRF_AB_GPIO4_OUT_LBN 20
391 #define	FRF_AB_GPIO4_OUT_WIDTH 1
392 #define	FRF_AB_GPIO3_OUT_LBN 19
393 #define	FRF_AB_GPIO3_OUT_WIDTH 1
394 #define	FRF_AB_GPIO2_OUT_LBN 18
395 #define	FRF_AB_GPIO2_OUT_WIDTH 1
396 #define	FRF_AB_GPIO1_OUT_LBN 17
397 #define	FRF_AB_GPIO1_OUT_WIDTH 1
398 #define	FRF_AB_GPIO0_OUT_LBN 16
399 #define	FRF_AB_GPIO0_OUT_WIDTH 1
400 #define	FRF_AB_GPIO7_IN_LBN 15
401 #define	FRF_AB_GPIO7_IN_WIDTH 1
402 #define	FRF_AB_GPIO6_IN_LBN 14
403 #define	FRF_AB_GPIO6_IN_WIDTH 1
404 #define	FRF_AB_GPIO5_IN_LBN 13
405 #define	FRF_AB_GPIO5_IN_WIDTH 1
406 #define	FRF_AB_GPIO4_IN_LBN 12
407 #define	FRF_AB_GPIO4_IN_WIDTH 1
408 #define	FRF_AB_GPIO3_IN_LBN 11
409 #define	FRF_AB_GPIO3_IN_WIDTH 1
410 #define	FRF_AB_GPIO2_IN_LBN 10
411 #define	FRF_AB_GPIO2_IN_WIDTH 1
412 #define	FRF_AB_GPIO1_IN_LBN 9
413 #define	FRF_AB_GPIO1_IN_WIDTH 1
414 #define	FRF_AB_GPIO0_IN_LBN 8
415 #define	FRF_AB_GPIO0_IN_WIDTH 1
416 #define	FRF_AB_GPIO7_PWRUP_VALUE_LBN 7
417 #define	FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1
418 #define	FRF_AB_GPIO6_PWRUP_VALUE_LBN 6
419 #define	FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1
420 #define	FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
421 #define	FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
422 #define	FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
423 #define	FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
424 #define	FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
425 #define	FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
426 #define	FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
427 #define	FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
428 #define	FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
429 #define	FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
430 #define	FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
431 #define	FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
432 
433 /* GLB_CTL_REG: Global control register */
434 #define	FR_AB_GLB_CTL 0x00000220
435 #define	FRF_AB_EXT_PHY_RST_CTL_LBN 63
436 #define	FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
437 #define	FRF_AB_XAUI_SD_RST_CTL_LBN 62
438 #define	FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
439 #define	FRF_AB_PCIE_SD_RST_CTL_LBN 61
440 #define	FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
441 #define	FRF_AA_PCIX_RST_CTL_LBN 60
442 #define	FRF_AA_PCIX_RST_CTL_WIDTH 1
443 #define	FRF_BB_BIU_RST_CTL_LBN 60
444 #define	FRF_BB_BIU_RST_CTL_WIDTH 1
445 #define	FRF_AB_PCIE_STKY_RST_CTL_LBN 59
446 #define	FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
447 #define	FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
448 #define	FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
449 #define	FRF_AB_PCIE_CORE_RST_CTL_LBN 57
450 #define	FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
451 #define	FRF_AB_XGRX_RST_CTL_LBN 56
452 #define	FRF_AB_XGRX_RST_CTL_WIDTH 1
453 #define	FRF_AB_XGTX_RST_CTL_LBN 55
454 #define	FRF_AB_XGTX_RST_CTL_WIDTH 1
455 #define	FRF_AB_EM_RST_CTL_LBN 54
456 #define	FRF_AB_EM_RST_CTL_WIDTH 1
457 #define	FRF_AB_EV_RST_CTL_LBN 53
458 #define	FRF_AB_EV_RST_CTL_WIDTH 1
459 #define	FRF_AB_SR_RST_CTL_LBN 52
460 #define	FRF_AB_SR_RST_CTL_WIDTH 1
461 #define	FRF_AB_RX_RST_CTL_LBN 51
462 #define	FRF_AB_RX_RST_CTL_WIDTH 1
463 #define	FRF_AB_TX_RST_CTL_LBN 50
464 #define	FRF_AB_TX_RST_CTL_WIDTH 1
465 #define	FRF_AB_EE_RST_CTL_LBN 49
466 #define	FRF_AB_EE_RST_CTL_WIDTH 1
467 #define	FRF_AB_CS_RST_CTL_LBN 48
468 #define	FRF_AB_CS_RST_CTL_WIDTH 1
469 #define	FRF_AB_HOT_RST_CTL_LBN 40
470 #define	FRF_AB_HOT_RST_CTL_WIDTH 2
471 #define	FRF_AB_RST_EXT_PHY_LBN 31
472 #define	FRF_AB_RST_EXT_PHY_WIDTH 1
473 #define	FRF_AB_RST_XAUI_SD_LBN 30
474 #define	FRF_AB_RST_XAUI_SD_WIDTH 1
475 #define	FRF_AB_RST_PCIE_SD_LBN 29
476 #define	FRF_AB_RST_PCIE_SD_WIDTH 1
477 #define	FRF_AA_RST_PCIX_LBN 28
478 #define	FRF_AA_RST_PCIX_WIDTH 1
479 #define	FRF_BB_RST_BIU_LBN 28
480 #define	FRF_BB_RST_BIU_WIDTH 1
481 #define	FRF_AB_RST_PCIE_STKY_LBN 27
482 #define	FRF_AB_RST_PCIE_STKY_WIDTH 1
483 #define	FRF_AB_RST_PCIE_NSTKY_LBN 26
484 #define	FRF_AB_RST_PCIE_NSTKY_WIDTH 1
485 #define	FRF_AB_RST_PCIE_CORE_LBN 25
486 #define	FRF_AB_RST_PCIE_CORE_WIDTH 1
487 #define	FRF_AB_RST_XGRX_LBN 24
488 #define	FRF_AB_RST_XGRX_WIDTH 1
489 #define	FRF_AB_RST_XGTX_LBN 23
490 #define	FRF_AB_RST_XGTX_WIDTH 1
491 #define	FRF_AB_RST_EM_LBN 22
492 #define	FRF_AB_RST_EM_WIDTH 1
493 #define	FRF_AB_RST_EV_LBN 21
494 #define	FRF_AB_RST_EV_WIDTH 1
495 #define	FRF_AB_RST_SR_LBN 20
496 #define	FRF_AB_RST_SR_WIDTH 1
497 #define	FRF_AB_RST_RX_LBN 19
498 #define	FRF_AB_RST_RX_WIDTH 1
499 #define	FRF_AB_RST_TX_LBN 18
500 #define	FRF_AB_RST_TX_WIDTH 1
501 #define	FRF_AB_RST_SF_LBN 17
502 #define	FRF_AB_RST_SF_WIDTH 1
503 #define	FRF_AB_RST_CS_LBN 16
504 #define	FRF_AB_RST_CS_WIDTH 1
505 #define	FRF_AB_INT_RST_DUR_LBN 4
506 #define	FRF_AB_INT_RST_DUR_WIDTH 3
507 #define	FRF_AB_EXT_PHY_RST_DUR_LBN 1
508 #define	FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
509 #define	FFE_AB_EXT_PHY_RST_DUR_10240US 7
510 #define	FFE_AB_EXT_PHY_RST_DUR_5120US 6
511 #define	FFE_AB_EXT_PHY_RST_DUR_2560US 5
512 #define	FFE_AB_EXT_PHY_RST_DUR_1280US 4
513 #define	FFE_AB_EXT_PHY_RST_DUR_640US 3
514 #define	FFE_AB_EXT_PHY_RST_DUR_320US 2
515 #define	FFE_AB_EXT_PHY_RST_DUR_160US 1
516 #define	FFE_AB_EXT_PHY_RST_DUR_80US 0
517 #define	FRF_AB_SWRST_LBN 0
518 #define	FRF_AB_SWRST_WIDTH 1
519 
520 /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */
521 #define	FR_AZ_FATAL_INTR_KER 0x00000230
522 #define	FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
523 #define	FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
524 #define	FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
525 #define	FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
526 #define	FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
527 #define	FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
528 #define	FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
529 #define	FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
530 #define	FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
531 #define	FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
532 #define	FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
533 #define	FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
534 #define	FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
535 #define	FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
536 #define	FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
537 #define	FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
538 #define	FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
539 #define	FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
540 #define	FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
541 #define	FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
542 #define	FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
543 #define	FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
544 #define	FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
545 #define	FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
546 #define	FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
547 #define	FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
548 #define	FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
549 #define	FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
550 #define	FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
551 #define	FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
552 #define	FRF_AB_PCI_BUSERR_INT_KER_LBN 11
553 #define	FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
554 #define	FRF_CZ_MBU_PERR_INT_KER_LBN 11
555 #define	FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
556 #define	FRF_AZ_SRAM_OOB_INT_KER_LBN 10
557 #define	FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
558 #define	FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
559 #define	FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
560 #define	FRF_AZ_MEM_PERR_INT_KER_LBN 8
561 #define	FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
562 #define	FRF_AZ_RBUF_OWN_INT_KER_LBN 7
563 #define	FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
564 #define	FRF_AZ_TBUF_OWN_INT_KER_LBN 6
565 #define	FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
566 #define	FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
567 #define	FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
568 #define	FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
569 #define	FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
570 #define	FRF_AZ_EVQ_OWN_INT_KER_LBN 3
571 #define	FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
572 #define	FRF_AZ_EVF_OFLO_INT_KER_LBN 2
573 #define	FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
574 #define	FRF_AZ_ILL_ADR_INT_KER_LBN 1
575 #define	FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
576 #define	FRF_AZ_SRM_PERR_INT_KER_LBN 0
577 #define	FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
578 
579 /* FATAL_INTR_REG_CHAR: Fatal interrupt register for Char */
580 #define	FR_BZ_FATAL_INTR_CHAR 0x00000240
581 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
582 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
583 #define	FRF_BB_PCI_BUSERR_INT_CHAR_EN_LBN 43
584 #define	FRF_BB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
585 #define	FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
586 #define	FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
587 #define	FRF_BZ_SRAM_OOB_INT_CHAR_EN_LBN 42
588 #define	FRF_BZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
589 #define	FRF_BZ_BUFID_OOB_INT_CHAR_EN_LBN 41
590 #define	FRF_BZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
591 #define	FRF_BZ_MEM_PERR_INT_CHAR_EN_LBN 40
592 #define	FRF_BZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
593 #define	FRF_BZ_RBUF_OWN_INT_CHAR_EN_LBN 39
594 #define	FRF_BZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
595 #define	FRF_BZ_TBUF_OWN_INT_CHAR_EN_LBN 38
596 #define	FRF_BZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
597 #define	FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
598 #define	FRF_BZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
599 #define	FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
600 #define	FRF_BZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
601 #define	FRF_BZ_EVQ_OWN_INT_CHAR_EN_LBN 35
602 #define	FRF_BZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
603 #define	FRF_BZ_EVF_OFLO_INT_CHAR_EN_LBN 34
604 #define	FRF_BZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
605 #define	FRF_BZ_ILL_ADR_INT_CHAR_EN_LBN 33
606 #define	FRF_BZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
607 #define	FRF_BZ_SRM_PERR_INT_CHAR_EN_LBN 32
608 #define	FRF_BZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
609 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
610 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
611 #define	FRF_BB_PCI_BUSERR_INT_CHAR_LBN 11
612 #define	FRF_BB_PCI_BUSERR_INT_CHAR_WIDTH 1
613 #define	FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
614 #define	FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
615 #define	FRF_BZ_SRAM_OOB_INT_CHAR_LBN 10
616 #define	FRF_BZ_SRAM_OOB_INT_CHAR_WIDTH 1
617 #define	FRF_BZ_BUFID_DC_OOB_INT_CHAR_LBN 9
618 #define	FRF_BZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
619 #define	FRF_BZ_MEM_PERR_INT_CHAR_LBN 8
620 #define	FRF_BZ_MEM_PERR_INT_CHAR_WIDTH 1
621 #define	FRF_BZ_RBUF_OWN_INT_CHAR_LBN 7
622 #define	FRF_BZ_RBUF_OWN_INT_CHAR_WIDTH 1
623 #define	FRF_BZ_TBUF_OWN_INT_CHAR_LBN 6
624 #define	FRF_BZ_TBUF_OWN_INT_CHAR_WIDTH 1
625 #define	FRF_BZ_RDESCQ_OWN_INT_CHAR_LBN 5
626 #define	FRF_BZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
627 #define	FRF_BZ_TDESCQ_OWN_INT_CHAR_LBN 4
628 #define	FRF_BZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
629 #define	FRF_BZ_EVQ_OWN_INT_CHAR_LBN 3
630 #define	FRF_BZ_EVQ_OWN_INT_CHAR_WIDTH 1
631 #define	FRF_BZ_EVF_OFLO_INT_CHAR_LBN 2
632 #define	FRF_BZ_EVF_OFLO_INT_CHAR_WIDTH 1
633 #define	FRF_BZ_ILL_ADR_INT_CHAR_LBN 1
634 #define	FRF_BZ_ILL_ADR_INT_CHAR_WIDTH 1
635 #define	FRF_BZ_SRM_PERR_INT_CHAR_LBN 0
636 #define	FRF_BZ_SRM_PERR_INT_CHAR_WIDTH 1
637 
638 /* DP_CTRL_REG: Datapath control register */
639 #define	FR_BZ_DP_CTRL 0x00000250
640 #define	FRF_BZ_FLS_EVQ_ID_LBN 0
641 #define	FRF_BZ_FLS_EVQ_ID_WIDTH 12
642 
643 /* MEM_STAT_REG: Memory status register */
644 #define	FR_AZ_MEM_STAT 0x00000260
645 #define	FRF_AB_MEM_PERR_VEC_LBN 53
646 #define	FRF_AB_MEM_PERR_VEC_WIDTH 38
647 #define	FRF_AB_MBIST_CORR_LBN 38
648 #define	FRF_AB_MBIST_CORR_WIDTH 15
649 #define	FRF_AB_MBIST_ERR_LBN 0
650 #define	FRF_AB_MBIST_ERR_WIDTH 40
651 #define	FRF_CZ_MEM_PERR_VEC_LBN 0
652 #define	FRF_CZ_MEM_PERR_VEC_WIDTH 35
653 
654 /* CS_DEBUG_REG: Debug register */
655 #define	FR_AZ_CS_DEBUG 0x00000270
656 #define	FRF_AB_GLB_DEBUG2_SEL_LBN 50
657 #define	FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
658 #define	FRF_AB_DEBUG_BLK_SEL2_LBN 47
659 #define	FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
660 #define	FRF_AB_DEBUG_BLK_SEL1_LBN 44
661 #define	FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
662 #define	FRF_AB_DEBUG_BLK_SEL0_LBN 41
663 #define	FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
664 #define	FRF_CZ_CS_PORT_NUM_LBN 40
665 #define	FRF_CZ_CS_PORT_NUM_WIDTH 2
666 #define	FRF_AB_MISC_DEBUG_ADDR_LBN 36
667 #define	FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
668 #define	FRF_AB_SERDES_DEBUG_ADDR_LBN 31
669 #define	FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
670 #define	FRF_CZ_CS_PORT_FPE_LBN 1
671 #define	FRF_CZ_CS_PORT_FPE_WIDTH 35
672 #define	FRF_AB_EM_DEBUG_ADDR_LBN 26
673 #define	FRF_AB_EM_DEBUG_ADDR_WIDTH 5
674 #define	FRF_AB_SR_DEBUG_ADDR_LBN 21
675 #define	FRF_AB_SR_DEBUG_ADDR_WIDTH 5
676 #define	FRF_AB_EV_DEBUG_ADDR_LBN 16
677 #define	FRF_AB_EV_DEBUG_ADDR_WIDTH 5
678 #define	FRF_AB_RX_DEBUG_ADDR_LBN 11
679 #define	FRF_AB_RX_DEBUG_ADDR_WIDTH 5
680 #define	FRF_AB_TX_DEBUG_ADDR_LBN 6
681 #define	FRF_AB_TX_DEBUG_ADDR_WIDTH 5
682 #define	FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
683 #define	FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
684 #define	FRF_AZ_CS_DEBUG_EN_LBN 0
685 #define	FRF_AZ_CS_DEBUG_EN_WIDTH 1
686 
687 /* DRIVER_REG: Driver scratch register [0-7] */
688 #define	FR_AZ_DRIVER 0x00000280
689 #define	FR_AZ_DRIVER_STEP 16
690 #define	FR_AZ_DRIVER_ROWS 8
691 #define	FRF_AZ_DRIVER_DW0_LBN 0
692 #define	FRF_AZ_DRIVER_DW0_WIDTH 32
693 
694 /* ALTERA_BUILD_REG: Altera build register */
695 #define	FR_AZ_ALTERA_BUILD 0x00000300
696 #define	FRF_AZ_ALTERA_BUILD_VER_LBN 0
697 #define	FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
698 
699 /* CSR_SPARE_REG: Spare register */
700 #define	FR_AZ_CSR_SPARE 0x00000310
701 #define	FRF_AB_MEM_PERR_EN_LBN 64
702 #define	FRF_AB_MEM_PERR_EN_WIDTH 38
703 #define	FRF_CZ_MEM_PERR_EN_LBN 64
704 #define	FRF_CZ_MEM_PERR_EN_WIDTH 35
705 #define	FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72
706 #define	FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2
707 #define	FRF_AZ_CSR_SPARE_BITS_LBN 0
708 #define	FRF_AZ_CSR_SPARE_BITS_WIDTH 32
709 
710 /* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */
711 #define	FR_AB_PCIE_SD_CTL0123 0x00000320
712 #define	FRF_AB_PCIE_TESTSIG_H_LBN 96
713 #define	FRF_AB_PCIE_TESTSIG_H_WIDTH 19
714 #define	FRF_AB_PCIE_TESTSIG_L_LBN 64
715 #define	FRF_AB_PCIE_TESTSIG_L_WIDTH 19
716 #define	FRF_AB_PCIE_OFFSET_LBN 56
717 #define	FRF_AB_PCIE_OFFSET_WIDTH 8
718 #define	FRF_AB_PCIE_OFFSETEN_H_LBN 55
719 #define	FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
720 #define	FRF_AB_PCIE_OFFSETEN_L_LBN 54
721 #define	FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
722 #define	FRF_AB_PCIE_HIVMODE_H_LBN 53
723 #define	FRF_AB_PCIE_HIVMODE_H_WIDTH 1
724 #define	FRF_AB_PCIE_HIVMODE_L_LBN 52
725 #define	FRF_AB_PCIE_HIVMODE_L_WIDTH 1
726 #define	FRF_AB_PCIE_PARRESET_H_LBN 51
727 #define	FRF_AB_PCIE_PARRESET_H_WIDTH 1
728 #define	FRF_AB_PCIE_PARRESET_L_LBN 50
729 #define	FRF_AB_PCIE_PARRESET_L_WIDTH 1
730 #define	FRF_AB_PCIE_LPBKWDRV_H_LBN 49
731 #define	FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
732 #define	FRF_AB_PCIE_LPBKWDRV_L_LBN 48
733 #define	FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
734 #define	FRF_AB_PCIE_LPBK_LBN 40
735 #define	FRF_AB_PCIE_LPBK_WIDTH 8
736 #define	FRF_AB_PCIE_PARLPBK_LBN 32
737 #define	FRF_AB_PCIE_PARLPBK_WIDTH 8
738 #define	FRF_AB_PCIE_RXTERMADJ_H_LBN 30
739 #define	FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
740 #define	FRF_AB_PCIE_RXTERMADJ_L_LBN 28
741 #define	FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
742 #define	FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
743 #define	FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
744 #define	FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
745 #define	FFE_AB_PCIE_RXTERMADJ_NOMNL 0
746 #define	FRF_AB_PCIE_TXTERMADJ_H_LBN 26
747 #define	FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
748 #define	FRF_AB_PCIE_TXTERMADJ_L_LBN 24
749 #define	FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
750 #define	FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
751 #define	FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
752 #define	FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
753 #define	FFE_AB_PCIE_TXTERMADJ_NOMNL 0
754 #define	FRF_AB_PCIE_RXEQCTL_H_LBN 18
755 #define	FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
756 #define	FRF_AB_PCIE_RXEQCTL_L_LBN 16
757 #define	FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
758 #define	FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
759 #define	FFE_AB_PCIE_RXEQCTL_OFF 2
760 #define	FFE_AB_PCIE_RXEQCTL_MIN 1
761 #define	FFE_AB_PCIE_RXEQCTL_MAX 0
762 #define	FRF_AB_PCIE_HIDRV_LBN 8
763 #define	FRF_AB_PCIE_HIDRV_WIDTH 8
764 #define	FRF_AB_PCIE_LODRV_LBN 0
765 #define	FRF_AB_PCIE_LODRV_WIDTH 8
766 
767 /* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */
768 #define	FR_AB_PCIE_SD_CTL45 0x00000330
769 #define	FRF_AB_PCIE_DTX7_LBN 60
770 #define	FRF_AB_PCIE_DTX7_WIDTH 4
771 #define	FRF_AB_PCIE_DTX6_LBN 56
772 #define	FRF_AB_PCIE_DTX6_WIDTH 4
773 #define	FRF_AB_PCIE_DTX5_LBN 52
774 #define	FRF_AB_PCIE_DTX5_WIDTH 4
775 #define	FRF_AB_PCIE_DTX4_LBN 48
776 #define	FRF_AB_PCIE_DTX4_WIDTH 4
777 #define	FRF_AB_PCIE_DTX3_LBN 44
778 #define	FRF_AB_PCIE_DTX3_WIDTH 4
779 #define	FRF_AB_PCIE_DTX2_LBN 40
780 #define	FRF_AB_PCIE_DTX2_WIDTH 4
781 #define	FRF_AB_PCIE_DTX1_LBN 36
782 #define	FRF_AB_PCIE_DTX1_WIDTH 4
783 #define	FRF_AB_PCIE_DTX0_LBN 32
784 #define	FRF_AB_PCIE_DTX0_WIDTH 4
785 #define	FRF_AB_PCIE_DEQ7_LBN 28
786 #define	FRF_AB_PCIE_DEQ7_WIDTH 4
787 #define	FRF_AB_PCIE_DEQ6_LBN 24
788 #define	FRF_AB_PCIE_DEQ6_WIDTH 4
789 #define	FRF_AB_PCIE_DEQ5_LBN 20
790 #define	FRF_AB_PCIE_DEQ5_WIDTH 4
791 #define	FRF_AB_PCIE_DEQ4_LBN 16
792 #define	FRF_AB_PCIE_DEQ4_WIDTH 4
793 #define	FRF_AB_PCIE_DEQ3_LBN 12
794 #define	FRF_AB_PCIE_DEQ3_WIDTH 4
795 #define	FRF_AB_PCIE_DEQ2_LBN 8
796 #define	FRF_AB_PCIE_DEQ2_WIDTH 4
797 #define	FRF_AB_PCIE_DEQ1_LBN 4
798 #define	FRF_AB_PCIE_DEQ1_WIDTH 4
799 #define	FRF_AB_PCIE_DEQ0_LBN 0
800 #define	FRF_AB_PCIE_DEQ0_WIDTH 4
801 
802 /* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */
803 #define	FR_AB_PCIE_PCS_CTL_STAT 0x00000340
804 #define	FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
805 #define	FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
806 #define	FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
807 #define	FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
808 #define	FRF_AB_PCIE_PRBSERR_LBN 40
809 #define	FRF_AB_PCIE_PRBSERR_WIDTH 8
810 #define	FRF_AB_PCIE_PRBSERRH0_LBN 32
811 #define	FRF_AB_PCIE_PRBSERRH0_WIDTH 8
812 #define	FRF_AB_PCIE_FASTINIT_H_LBN 15
813 #define	FRF_AB_PCIE_FASTINIT_H_WIDTH 1
814 #define	FRF_AB_PCIE_FASTINIT_L_LBN 14
815 #define	FRF_AB_PCIE_FASTINIT_L_WIDTH 1
816 #define	FRF_AB_PCIE_CTCDISABLE_H_LBN 13
817 #define	FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
818 #define	FRF_AB_PCIE_CTCDISABLE_L_LBN 12
819 #define	FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
820 #define	FRF_AB_PCIE_PRBSSYNC_H_LBN 11
821 #define	FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
822 #define	FRF_AB_PCIE_PRBSSYNC_L_LBN 10
823 #define	FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
824 #define	FRF_AB_PCIE_PRBSERRACK_H_LBN 9
825 #define	FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
826 #define	FRF_AB_PCIE_PRBSERRACK_L_LBN 8
827 #define	FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
828 #define	FRF_AB_PCIE_PRBSSEL_LBN 0
829 #define	FRF_AB_PCIE_PRBSSEL_WIDTH 8
830 
831 /* DEBUG_DATA_OUT_REG: Live Debug and Debug 2 out ports */
832 #define	FR_BB_DEBUG_DATA_OUT 0x00000350
833 #define	FRF_BB_DEBUG2_PORT_LBN 25
834 #define	FRF_BB_DEBUG2_PORT_WIDTH 15
835 #define	FRF_BB_DEBUG1_PORT_LBN 0
836 #define	FRF_BB_DEBUG1_PORT_WIDTH 25
837 
838 /* EVQ_RPTR_REGP0: Event queue read pointer register */
839 #define	FR_BZ_EVQ_RPTR_P0 0x00000400
840 #define	FR_BZ_EVQ_RPTR_P0_STEP 8192
841 #define	FR_BZ_EVQ_RPTR_P0_ROWS 1024
842 /* EVQ_RPTR_REG_KER: Event queue read pointer register */
843 #define	FR_AA_EVQ_RPTR_KER 0x00011b00
844 #define	FR_AA_EVQ_RPTR_KER_STEP 4
845 #define	FR_AA_EVQ_RPTR_KER_ROWS 4
846 /* EVQ_RPTR_REG: Event queue read pointer register */
847 #define	FR_BZ_EVQ_RPTR 0x00fa0000
848 #define	FR_BZ_EVQ_RPTR_STEP 16
849 #define	FR_BB_EVQ_RPTR_ROWS 4096
850 #define	FR_CZ_EVQ_RPTR_ROWS 1024
851 /* EVQ_RPTR_REGP123: Event queue read pointer register */
852 #define	FR_BB_EVQ_RPTR_P123 0x01000400
853 #define	FR_BB_EVQ_RPTR_P123_STEP 8192
854 #define	FR_BB_EVQ_RPTR_P123_ROWS 3072
855 #define	FRF_AZ_EVQ_RPTR_VLD_LBN 15
856 #define	FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
857 #define	FRF_AZ_EVQ_RPTR_LBN 0
858 #define	FRF_AZ_EVQ_RPTR_WIDTH 15
859 
860 /* TIMER_COMMAND_REGP0: Timer Command Registers */
861 #define	FR_BZ_TIMER_COMMAND_P0 0x00000420
862 #define	FR_BZ_TIMER_COMMAND_P0_STEP 8192
863 #define	FR_BZ_TIMER_COMMAND_P0_ROWS 1024
864 /* TIMER_COMMAND_REG_KER: Timer Command Registers */
865 #define	FR_AA_TIMER_COMMAND_KER 0x00000420
866 #define	FR_AA_TIMER_COMMAND_KER_STEP 8192
867 #define	FR_AA_TIMER_COMMAND_KER_ROWS 4
868 /* TIMER_COMMAND_REGP123: Timer Command Registers */
869 #define	FR_BB_TIMER_COMMAND_P123 0x01000420
870 #define	FR_BB_TIMER_COMMAND_P123_STEP 8192
871 #define	FR_BB_TIMER_COMMAND_P123_ROWS 3072
872 #define	FRF_CZ_TC_TIMER_MODE_LBN 14
873 #define	FRF_CZ_TC_TIMER_MODE_WIDTH 2
874 #define	FRF_AB_TC_TIMER_MODE_LBN 12
875 #define	FRF_AB_TC_TIMER_MODE_WIDTH 2
876 #define	FRF_CZ_TC_TIMER_VAL_LBN 0
877 #define	FRF_CZ_TC_TIMER_VAL_WIDTH 14
878 #define	FRF_AB_TC_TIMER_VAL_LBN 0
879 #define	FRF_AB_TC_TIMER_VAL_WIDTH 12
880 
881 /* DRV_EV_REG: Driver generated event register */
882 #define	FR_AZ_DRV_EV 0x00000440
883 #define	FRF_AZ_DRV_EV_QID_LBN 64
884 #define	FRF_AZ_DRV_EV_QID_WIDTH 12
885 #define	FRF_AZ_DRV_EV_DATA_LBN 0
886 #define	FRF_AZ_DRV_EV_DATA_WIDTH 64
887 
888 /* EVQ_CTL_REG: Event queue control register */
889 #define	FR_AZ_EVQ_CTL 0x00000450
890 #define	FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
891 #define	FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
892 #define	FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
893 #define	FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
894 #define	FRF_AZ_EVQ_OWNERR_CTL_LBN 14
895 #define	FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
896 #define	FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
897 #define	FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
898 #define	FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
899 #define	FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
900 
901 /* EVQ_CNT1_REG: Event counter 1 register */
902 #define	FR_AZ_EVQ_CNT1 0x00000460
903 #define	FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
904 #define	FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
905 #define	FRF_AZ_EVQ_CNT_TOBIU_LBN 100
906 #define	FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
907 #define	FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
908 #define	FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
909 #define	FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
910 #define	FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
911 #define	FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
912 #define	FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
913 #define	FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
914 #define	FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
915 #define	FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
916 #define	FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
917 
918 /* EVQ_CNT2_REG: Event counter 2 register */
919 #define	FR_AZ_EVQ_CNT2 0x00000470
920 #define	FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
921 #define	FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
922 #define	FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
923 #define	FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
924 #define	FRF_AZ_EVQ_RDY_CNT_LBN 80
925 #define	FRF_AZ_EVQ_RDY_CNT_WIDTH 4
926 #define	FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
927 #define	FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
928 #define	FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
929 #define	FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
930 #define	FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
931 #define	FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
932 #define	FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
933 #define	FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
934 
935 /* USR_EV_REG: Event mailbox register */
936 #define	FR_CZ_USR_EV 0x00000540
937 #define	FR_CZ_USR_EV_STEP 8192
938 #define	FR_CZ_USR_EV_ROWS 1024
939 #define	FRF_CZ_USR_EV_DATA_LBN 0
940 #define	FRF_CZ_USR_EV_DATA_WIDTH 32
941 
942 /* BUF_TBL_CFG_REG: Buffer table configuration register */
943 #define	FR_AZ_BUF_TBL_CFG 0x00000600
944 #define	FRF_AZ_BUF_TBL_MODE_LBN 3
945 #define	FRF_AZ_BUF_TBL_MODE_WIDTH 1
946 
947 /* SRM_RX_DC_CFG_REG: SRAM receive descriptor cache configuration register */
948 #define	FR_AZ_SRM_RX_DC_CFG 0x00000610
949 #define	FRF_AZ_SRM_CLK_TMP_EN_LBN 21
950 #define	FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
951 #define	FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
952 #define	FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
953 
954 /* SRM_TX_DC_CFG_REG: SRAM transmit descriptor cache configuration register */
955 #define	FR_AZ_SRM_TX_DC_CFG 0x00000620
956 #define	FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
957 #define	FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
958 
959 /* SRM_CFG_REG: SRAM configuration register */
960 #define	FR_AZ_SRM_CFG 0x00000630
961 #define	FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
962 #define	FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
963 #define	FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
964 #define	FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
965 #define	FRF_AZ_SRM_INIT_EN_LBN 3
966 #define	FRF_AZ_SRM_INIT_EN_WIDTH 1
967 #define	FRF_AZ_SRM_NUM_BANK_LBN 2
968 #define	FRF_AZ_SRM_NUM_BANK_WIDTH 1
969 #define	FRF_AZ_SRM_BANK_SIZE_LBN 0
970 #define	FRF_AZ_SRM_BANK_SIZE_WIDTH 2
971 
972 /* BUF_TBL_UPD_REG: Buffer table update register */
973 #define	FR_AZ_BUF_TBL_UPD 0x00000650
974 #define	FRF_AZ_BUF_UPD_CMD_LBN 63
975 #define	FRF_AZ_BUF_UPD_CMD_WIDTH 1
976 #define	FRF_AZ_BUF_CLR_CMD_LBN 62
977 #define	FRF_AZ_BUF_CLR_CMD_WIDTH 1
978 #define	FRF_AZ_BUF_CLR_END_ID_LBN 32
979 #define	FRF_AZ_BUF_CLR_END_ID_WIDTH 20
980 #define	FRF_AZ_BUF_CLR_START_ID_LBN 0
981 #define	FRF_AZ_BUF_CLR_START_ID_WIDTH 20
982 
983 /* SRM_UPD_EVQ_REG: Buffer table update register */
984 #define	FR_AZ_SRM_UPD_EVQ 0x00000660
985 #define	FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
986 #define	FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
987 
988 /* SRAM_PARITY_REG: SRAM parity register. */
989 #define	FR_AZ_SRAM_PARITY 0x00000670
990 #define	FRF_CZ_BYPASS_ECC_LBN 3
991 #define	FRF_CZ_BYPASS_ECC_WIDTH 1
992 #define	FRF_CZ_SEC_INT_LBN 2
993 #define	FRF_CZ_SEC_INT_WIDTH 1
994 #define	FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
995 #define	FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
996 #define	FRF_AB_FORCE_SRAM_PERR_LBN 0
997 #define	FRF_AB_FORCE_SRAM_PERR_WIDTH 1
998 #define	FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
999 #define	FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
1000 
1001 /* RX_CFG_REG: Receive configuration register */
1002 #define	FR_AZ_RX_CFG 0x00000800
1003 #define	FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72
1004 #define	FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14
1005 #define	FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
1006 #define	FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
1007 #define	FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
1008 #define	FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
1009 #define	FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
1010 #define	FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
1011 #define	FRF_CZ_RX_PRE_RFF_IPG_LBN 49
1012 #define	FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
1013 #define	FRF_BZ_RX_TCP_SUP_LBN 48
1014 #define	FRF_BZ_RX_TCP_SUP_WIDTH 1
1015 #define	FRF_BZ_RX_INGR_EN_LBN 47
1016 #define	FRF_BZ_RX_INGR_EN_WIDTH 1
1017 #define	FRF_BZ_RX_IP_HASH_LBN 46
1018 #define	FRF_BZ_RX_IP_HASH_WIDTH 1
1019 #define	FRF_BZ_RX_HASH_ALG_LBN 45
1020 #define	FRF_BZ_RX_HASH_ALG_WIDTH 1
1021 #define	FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
1022 #define	FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
1023 #define	FRF_BZ_RX_DESC_PUSH_EN_LBN 43
1024 #define	FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
1025 #define	FRF_BZ_RX_RDW_PATCH_EN_LBN 42
1026 #define	FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
1027 #define	FRF_BB_RX_PCI_BURST_SIZE_LBN 39
1028 #define	FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
1029 #define	FRF_BZ_RX_OWNERR_CTL_LBN 38
1030 #define	FRF_BZ_RX_OWNERR_CTL_WIDTH 1
1031 #define	FRF_BZ_RX_XON_TX_TH_LBN 33
1032 #define	FRF_BZ_RX_XON_TX_TH_WIDTH 5
1033 #define	FRF_AA_RX_DESC_PUSH_EN_LBN 35
1034 #define	FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
1035 #define	FRF_AA_RX_RDW_PATCH_EN_LBN 34
1036 #define	FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
1037 #define	FRF_AA_RX_PCI_BURST_SIZE_LBN 31
1038 #define	FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
1039 #define	FRF_BZ_RX_XOFF_TX_TH_LBN 28
1040 #define	FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
1041 #define	FRF_AA_RX_OWNERR_CTL_LBN 30
1042 #define	FRF_AA_RX_OWNERR_CTL_WIDTH 1
1043 #define	FRF_AA_RX_XON_TX_TH_LBN 25
1044 #define	FRF_AA_RX_XON_TX_TH_WIDTH 5
1045 #define	FRF_BZ_RX_USR_BUF_SIZE_LBN 19
1046 #define	FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
1047 #define	FRF_AA_RX_XOFF_TX_TH_LBN 20
1048 #define	FRF_AA_RX_XOFF_TX_TH_WIDTH 5
1049 #define	FRF_AA_RX_USR_BUF_SIZE_LBN 11
1050 #define	FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
1051 #define	FRF_BZ_RX_XON_MAC_TH_LBN 10
1052 #define	FRF_BZ_RX_XON_MAC_TH_WIDTH 9
1053 #define	FRF_AA_RX_XON_MAC_TH_LBN 6
1054 #define	FRF_AA_RX_XON_MAC_TH_WIDTH 5
1055 #define	FRF_BZ_RX_XOFF_MAC_TH_LBN 1
1056 #define	FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
1057 #define	FRF_AA_RX_XOFF_MAC_TH_LBN 1
1058 #define	FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
1059 #define	FRF_AZ_RX_XOFF_MAC_EN_LBN 0
1060 #define	FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
1061 
1062 /* RX_FILTER_CTL_REG: Receive filter control registers */
1063 #define	FR_BZ_RX_FILTER_CTL 0x00000810
1064 #define	FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
1065 #define	FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
1066 #define	FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
1067 #define	FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
1068 #define	FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
1069 #define	FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
1070 #define	FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
1071 #define	FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
1072 #define	FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
1073 #define	FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
1074 #define	FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
1075 #define	FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1076 #define	FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
1077 #define	FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1078 #define	FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
1079 #define	FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
1080 #define	FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
1081 #define	FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1082 #define	FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
1083 #define	FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1084 #define	FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
1085 #define	FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
1086 #define	FRF_BZ_UDP_FULL_SRCH_LIMIT_LBN 32
1087 #define	FRF_BZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
1088 #define	FRF_BZ_NUM_KER_LBN 24
1089 #define	FRF_BZ_NUM_KER_WIDTH 2
1090 #define	FRF_BZ_UDP_WILD_SRCH_LIMIT_LBN 16
1091 #define	FRF_BZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
1092 #define	FRF_BZ_TCP_WILD_SRCH_LIMIT_LBN 8
1093 #define	FRF_BZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
1094 #define	FRF_BZ_TCP_FULL_SRCH_LIMIT_LBN 0
1095 #define	FRF_BZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
1096 
1097 /* RX_FLUSH_DESCQ_REG: Receive flush descriptor queue register */
1098 #define	FR_AZ_RX_FLUSH_DESCQ 0x00000820
1099 #define	FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
1100 #define	FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
1101 #define	FRF_AZ_RX_FLUSH_DESCQ_LBN 0
1102 #define	FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
1103 
1104 /* RX_DESC_UPD_REGP0: Receive descriptor update register. */
1105 #define	FR_BZ_RX_DESC_UPD_P0 0x00000830
1106 #define	FR_BZ_RX_DESC_UPD_P0_STEP 8192
1107 #define	FR_BZ_RX_DESC_UPD_P0_ROWS 1024
1108 /* RX_DESC_UPD_REG_KER: Receive descriptor update register. */
1109 #define	FR_AA_RX_DESC_UPD_KER 0x00000830
1110 #define	FR_AA_RX_DESC_UPD_KER_STEP 8192
1111 #define	FR_AA_RX_DESC_UPD_KER_ROWS 4
1112 /* RX_DESC_UPD_REGP123: Receive descriptor update register. */
1113 #define	FR_BB_RX_DESC_UPD_P123 0x01000830
1114 #define	FR_BB_RX_DESC_UPD_P123_STEP 8192
1115 #define	FR_BB_RX_DESC_UPD_P123_ROWS 3072
1116 #define	FRF_AZ_RX_DESC_WPTR_LBN 96
1117 #define	FRF_AZ_RX_DESC_WPTR_WIDTH 12
1118 #define	FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
1119 #define	FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
1120 #define	FRF_AZ_RX_DESC_LBN 0
1121 #define	FRF_AZ_RX_DESC_WIDTH 64
1122 
1123 /* RX_DC_CFG_REG: Receive descriptor cache configuration register */
1124 #define	FR_AZ_RX_DC_CFG 0x00000840
1125 #define	FRF_AB_RX_MAX_PF_LBN 2
1126 #define	FRF_AB_RX_MAX_PF_WIDTH 2
1127 #define	FRF_AZ_RX_DC_SIZE_LBN 0
1128 #define	FRF_AZ_RX_DC_SIZE_WIDTH 2
1129 #define	FFE_AZ_RX_DC_SIZE_64 3
1130 #define	FFE_AZ_RX_DC_SIZE_32 2
1131 #define	FFE_AZ_RX_DC_SIZE_16 1
1132 #define	FFE_AZ_RX_DC_SIZE_8 0
1133 
1134 /* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */
1135 #define	FR_AZ_RX_DC_PF_WM 0x00000850
1136 #define	FRF_AZ_RX_DC_PF_HWM_LBN 6
1137 #define	FRF_AZ_RX_DC_PF_HWM_WIDTH 6
1138 #define	FRF_AZ_RX_DC_PF_LWM_LBN 0
1139 #define	FRF_AZ_RX_DC_PF_LWM_WIDTH 6
1140 
1141 /* RX_RSS_TKEY_REG: RSS Toeplitz hash key */
1142 #define	FR_BZ_RX_RSS_TKEY 0x00000860
1143 #define	FRF_BZ_RX_RSS_TKEY_HI_LBN 64
1144 #define	FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64
1145 #define	FRF_BZ_RX_RSS_TKEY_LO_LBN 0
1146 #define	FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64
1147 
1148 /* RX_NODESC_DROP_REG: Receive dropped packet counter register */
1149 #define	FR_AZ_RX_NODESC_DROP 0x00000880
1150 #define	FRF_CZ_RX_NODESC_DROP_CNT_LBN 0
1151 #define	FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32
1152 #define	FRF_AB_RX_NODESC_DROP_CNT_LBN 0
1153 #define	FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16
1154 
1155 /* RX_SELF_RST_REG: Receive self reset register */
1156 #define	FR_AA_RX_SELF_RST 0x00000890
1157 #define	FRF_AA_RX_ISCSI_DIS_LBN 17
1158 #define	FRF_AA_RX_ISCSI_DIS_WIDTH 1
1159 #define	FRF_AA_RX_SW_RST_REG_LBN 16
1160 #define	FRF_AA_RX_SW_RST_REG_WIDTH 1
1161 #define FRF_AA_RX_NODESC_WAIT_DIS_LBN 9
1162 #define FRF_AA_RX_NODESC_WAIT_DIS_WIDTH 1
1163 #define	FRF_AA_RX_SELF_RST_EN_LBN 8
1164 #define	FRF_AA_RX_SELF_RST_EN_WIDTH 1
1165 #define	FRF_AA_RX_MAX_PF_LAT_LBN 4
1166 #define	FRF_AA_RX_MAX_PF_LAT_WIDTH 4
1167 #define	FRF_AA_RX_MAX_LU_LAT_LBN 0
1168 #define	FRF_AA_RX_MAX_LU_LAT_WIDTH 4
1169 
1170 /* RX_DEBUG_REG: undocumented register */
1171 #define	FR_AZ_RX_DEBUG 0x000008a0
1172 #define	FRF_AZ_RX_DEBUG_LBN 0
1173 #define	FRF_AZ_RX_DEBUG_WIDTH 64
1174 
1175 /* RX_PUSH_DROP_REG: Receive descriptor push dropped counter register */
1176 #define	FR_AZ_RX_PUSH_DROP 0x000008b0
1177 #define	FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
1178 #define	FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
1179 
1180 /* RX_RSS_IPV6_REG1: IPv6 RSS Toeplitz hash key low bytes */
1181 #define	FR_CZ_RX_RSS_IPV6_REG1 0x000008d0
1182 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
1183 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
1184 
1185 /* RX_RSS_IPV6_REG2: IPv6 RSS Toeplitz hash key middle bytes */
1186 #define	FR_CZ_RX_RSS_IPV6_REG2 0x000008e0
1187 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
1188 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
1189 
1190 /* RX_RSS_IPV6_REG3: IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings */
1191 #define	FR_CZ_RX_RSS_IPV6_REG3 0x000008f0
1192 #define	FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
1193 #define	FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
1194 #define	FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
1195 #define	FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
1196 #define	FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
1197 #define	FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
1198 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
1199 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
1200 
1201 /* TX_FLUSH_DESCQ_REG: Transmit flush descriptor queue register */
1202 #define	FR_AZ_TX_FLUSH_DESCQ 0x00000a00
1203 #define	FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
1204 #define	FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
1205 #define	FRF_AZ_TX_FLUSH_DESCQ_LBN 0
1206 #define	FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
1207 
1208 /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */
1209 #define	FR_BZ_TX_DESC_UPD_P0 0x00000a10
1210 #define	FR_BZ_TX_DESC_UPD_P0_STEP 8192
1211 #define	FR_BZ_TX_DESC_UPD_P0_ROWS 1024
1212 /* TX_DESC_UPD_REG_KER: Transmit descriptor update register. */
1213 #define	FR_AA_TX_DESC_UPD_KER 0x00000a10
1214 #define	FR_AA_TX_DESC_UPD_KER_STEP 8192
1215 #define	FR_AA_TX_DESC_UPD_KER_ROWS 8
1216 /* TX_DESC_UPD_REGP123: Transmit descriptor update register. */
1217 #define	FR_BB_TX_DESC_UPD_P123 0x01000a10
1218 #define	FR_BB_TX_DESC_UPD_P123_STEP 8192
1219 #define	FR_BB_TX_DESC_UPD_P123_ROWS 3072
1220 #define	FRF_AZ_TX_DESC_WPTR_LBN 96
1221 #define	FRF_AZ_TX_DESC_WPTR_WIDTH 12
1222 #define	FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
1223 #define	FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
1224 #define	FRF_AZ_TX_DESC_LBN 0
1225 #define	FRF_AZ_TX_DESC_WIDTH 95
1226 
1227 /* TX_DC_CFG_REG: Transmit descriptor cache configuration register */
1228 #define	FR_AZ_TX_DC_CFG 0x00000a20
1229 #define	FRF_AZ_TX_DC_SIZE_LBN 0
1230 #define	FRF_AZ_TX_DC_SIZE_WIDTH 2
1231 #define	FFE_AZ_TX_DC_SIZE_32 2
1232 #define	FFE_AZ_TX_DC_SIZE_16 1
1233 #define	FFE_AZ_TX_DC_SIZE_8 0
1234 
1235 /* TX_CHKSM_CFG_REG: Transmit checksum configuration register */
1236 #define	FR_AA_TX_CHKSM_CFG 0x00000a30
1237 #define	FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
1238 #define	FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
1239 #define	FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
1240 #define	FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
1241 #define	FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
1242 #define	FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
1243 #define	FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
1244 #define	FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
1245 
1246 /* TX_CFG_REG: Transmit configuration register */
1247 #define	FR_AZ_TX_CFG 0x00000a50
1248 #define	FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
1249 #define	FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
1250 #define	FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
1251 #define	FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
1252 #define	FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
1253 #define	FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1254 #define	FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
1255 #define	FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1256 #define	FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
1257 #define	FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1258 #define	FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
1259 #define	FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1260 #define	FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
1261 #define	FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1262 #define	FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
1263 #define	FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1264 #define	FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
1265 #define	FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
1266 #define	FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
1267 #define	FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
1268 #define	FRF_CZ_TX_FILTER_EN_BIT_LBN 47
1269 #define	FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
1270 #define	FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
1271 #define	FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
1272 #define	FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
1273 #define	FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
1274 #define	FRF_AZ_TX_P1_PRI_EN_LBN 4
1275 #define	FRF_AZ_TX_P1_PRI_EN_WIDTH 1
1276 #define	FRF_AZ_TX_OWNERR_CTL_LBN 2
1277 #define	FRF_AZ_TX_OWNERR_CTL_WIDTH 1
1278 #define	FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
1279 #define	FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
1280 #define	FRF_AZ_TX_IP_ID_REP_EN_LBN 0
1281 #define	FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
1282 
1283 /* TX_PUSH_DROP_REG: Transmit push dropped register */
1284 #define	FR_AZ_TX_PUSH_DROP 0x00000a60
1285 #define	FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
1286 #define	FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
1287 
1288 /* TX_RESERVED_REG: Transmit configuration register */
1289 #define	FR_AZ_TX_RESERVED 0x00000a80
1290 #define	FRF_AZ_TX_EVT_CNT_LBN 121
1291 #define	FRF_AZ_TX_EVT_CNT_WIDTH 7
1292 #define	FRF_AZ_TX_PREF_AGE_CNT_LBN 119
1293 #define	FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
1294 #define	FRF_AZ_TX_RD_COMP_TMR_LBN 96
1295 #define	FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
1296 #define	FRF_AZ_TX_PUSH_EN_LBN 89
1297 #define	FRF_AZ_TX_PUSH_EN_WIDTH 1
1298 #define	FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
1299 #define	FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
1300 #define	FRF_AZ_TX_D_FF_FULL_P0_LBN 85
1301 #define	FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
1302 #define	FRF_AZ_TX_DMAR_ST_P0_LBN 81
1303 #define	FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
1304 #define	FRF_AZ_TX_DMAQ_ST_LBN 78
1305 #define	FRF_AZ_TX_DMAQ_ST_WIDTH 1
1306 #define	FRF_AZ_TX_RX_SPACER_LBN 64
1307 #define	FRF_AZ_TX_RX_SPACER_WIDTH 8
1308 #define	FRF_AZ_TX_DROP_ABORT_EN_LBN 60
1309 #define	FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
1310 #define	FRF_AZ_TX_SOFT_EVT_EN_LBN 59
1311 #define	FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
1312 #define	FRF_AZ_TX_PS_EVT_DIS_LBN 58
1313 #define	FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
1314 #define	FRF_AZ_TX_RX_SPACER_EN_LBN 57
1315 #define	FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
1316 #define	FRF_AZ_TX_XP_TIMER_LBN 52
1317 #define	FRF_AZ_TX_XP_TIMER_WIDTH 5
1318 #define	FRF_AZ_TX_PREF_SPACER_LBN 44
1319 #define	FRF_AZ_TX_PREF_SPACER_WIDTH 8
1320 #define	FRF_AZ_TX_PREF_WD_TMR_LBN 22
1321 #define	FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
1322 #define	FRF_AZ_TX_ONLY1TAG_LBN 21
1323 #define	FRF_AZ_TX_ONLY1TAG_WIDTH 1
1324 #define	FRF_AZ_TX_PREF_THRESHOLD_LBN 19
1325 #define	FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
1326 #define	FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
1327 #define	FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
1328 #define	FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
1329 #define	FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
1330 #define	FRF_AA_TX_DMA_FF_THR_LBN 16
1331 #define	FRF_AA_TX_DMA_FF_THR_WIDTH 1
1332 #define	FRF_AZ_TX_DMA_SPACER_LBN 8
1333 #define	FRF_AZ_TX_DMA_SPACER_WIDTH 8
1334 #define	FRF_AA_TX_TCP_DIS_LBN 7
1335 #define	FRF_AA_TX_TCP_DIS_WIDTH 1
1336 #define	FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
1337 #define	FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
1338 #define	FRF_AA_TX_IP_DIS_LBN 6
1339 #define	FRF_AA_TX_IP_DIS_WIDTH 1
1340 #define	FRF_AZ_TX_MAX_CPL_LBN 2
1341 #define	FRF_AZ_TX_MAX_CPL_WIDTH 2
1342 #define	FFE_AZ_TX_MAX_CPL_16 3
1343 #define	FFE_AZ_TX_MAX_CPL_8 2
1344 #define	FFE_AZ_TX_MAX_CPL_4 1
1345 #define	FFE_AZ_TX_MAX_CPL_NOLIMIT 0
1346 #define	FRF_AZ_TX_MAX_PREF_LBN 0
1347 #define	FRF_AZ_TX_MAX_PREF_WIDTH 2
1348 #define	FFE_AZ_TX_MAX_PREF_32 3
1349 #define	FFE_AZ_TX_MAX_PREF_16 2
1350 #define	FFE_AZ_TX_MAX_PREF_8 1
1351 #define	FFE_AZ_TX_MAX_PREF_OFF 0
1352 
1353 /* TX_PACE_REG: Transmit pace control register */
1354 #define	FR_BZ_TX_PACE 0x00000a90
1355 #define	FRF_BZ_TX_PACE_SB_NOT_AF_LBN 19
1356 #define	FRF_BZ_TX_PACE_SB_NOT_AF_WIDTH 10
1357 #define	FRF_BZ_TX_PACE_SB_AF_LBN 9
1358 #define	FRF_BZ_TX_PACE_SB_AF_WIDTH 10
1359 #define	FRF_BZ_TX_PACE_FB_BASE_LBN 5
1360 #define	FRF_BZ_TX_PACE_FB_BASE_WIDTH 4
1361 #define	FRF_BZ_TX_PACE_BIN_TH_LBN 0
1362 #define	FRF_BZ_TX_PACE_BIN_TH_WIDTH 5
1363 
1364 /* TX_PACE_DROP_QID_REG: PACE Drop QID Counter */
1365 #define	FR_BZ_TX_PACE_DROP_QID 0x00000aa0
1366 #define	FRF_BZ_TX_PACE_QID_DRP_CNT_LBN 0
1367 #define	FRF_BZ_TX_PACE_QID_DRP_CNT_WIDTH 16
1368 
1369 /* TX_VLAN_REG: Transmit VLAN tag register */
1370 #define	FR_BB_TX_VLAN 0x00000ae0
1371 #define	FRF_BB_TX_VLAN_EN_LBN 127
1372 #define	FRF_BB_TX_VLAN_EN_WIDTH 1
1373 #define	FRF_BB_TX_VLAN7_PORT1_EN_LBN 125
1374 #define	FRF_BB_TX_VLAN7_PORT1_EN_WIDTH 1
1375 #define	FRF_BB_TX_VLAN7_PORT0_EN_LBN 124
1376 #define	FRF_BB_TX_VLAN7_PORT0_EN_WIDTH 1
1377 #define	FRF_BB_TX_VLAN7_LBN 112
1378 #define	FRF_BB_TX_VLAN7_WIDTH 12
1379 #define	FRF_BB_TX_VLAN6_PORT1_EN_LBN 109
1380 #define	FRF_BB_TX_VLAN6_PORT1_EN_WIDTH 1
1381 #define	FRF_BB_TX_VLAN6_PORT0_EN_LBN 108
1382 #define	FRF_BB_TX_VLAN6_PORT0_EN_WIDTH 1
1383 #define	FRF_BB_TX_VLAN6_LBN 96
1384 #define	FRF_BB_TX_VLAN6_WIDTH 12
1385 #define	FRF_BB_TX_VLAN5_PORT1_EN_LBN 93
1386 #define	FRF_BB_TX_VLAN5_PORT1_EN_WIDTH 1
1387 #define	FRF_BB_TX_VLAN5_PORT0_EN_LBN 92
1388 #define	FRF_BB_TX_VLAN5_PORT0_EN_WIDTH 1
1389 #define	FRF_BB_TX_VLAN5_LBN 80
1390 #define	FRF_BB_TX_VLAN5_WIDTH 12
1391 #define	FRF_BB_TX_VLAN4_PORT1_EN_LBN 77
1392 #define	FRF_BB_TX_VLAN4_PORT1_EN_WIDTH 1
1393 #define	FRF_BB_TX_VLAN4_PORT0_EN_LBN 76
1394 #define	FRF_BB_TX_VLAN4_PORT0_EN_WIDTH 1
1395 #define	FRF_BB_TX_VLAN4_LBN 64
1396 #define	FRF_BB_TX_VLAN4_WIDTH 12
1397 #define	FRF_BB_TX_VLAN3_PORT1_EN_LBN 61
1398 #define	FRF_BB_TX_VLAN3_PORT1_EN_WIDTH 1
1399 #define	FRF_BB_TX_VLAN3_PORT0_EN_LBN 60
1400 #define	FRF_BB_TX_VLAN3_PORT0_EN_WIDTH 1
1401 #define	FRF_BB_TX_VLAN3_LBN 48
1402 #define	FRF_BB_TX_VLAN3_WIDTH 12
1403 #define	FRF_BB_TX_VLAN2_PORT1_EN_LBN 45
1404 #define	FRF_BB_TX_VLAN2_PORT1_EN_WIDTH 1
1405 #define	FRF_BB_TX_VLAN2_PORT0_EN_LBN 44
1406 #define	FRF_BB_TX_VLAN2_PORT0_EN_WIDTH 1
1407 #define	FRF_BB_TX_VLAN2_LBN 32
1408 #define	FRF_BB_TX_VLAN2_WIDTH 12
1409 #define	FRF_BB_TX_VLAN1_PORT1_EN_LBN 29
1410 #define	FRF_BB_TX_VLAN1_PORT1_EN_WIDTH 1
1411 #define	FRF_BB_TX_VLAN1_PORT0_EN_LBN 28
1412 #define	FRF_BB_TX_VLAN1_PORT0_EN_WIDTH 1
1413 #define	FRF_BB_TX_VLAN1_LBN 16
1414 #define	FRF_BB_TX_VLAN1_WIDTH 12
1415 #define	FRF_BB_TX_VLAN0_PORT1_EN_LBN 13
1416 #define	FRF_BB_TX_VLAN0_PORT1_EN_WIDTH 1
1417 #define	FRF_BB_TX_VLAN0_PORT0_EN_LBN 12
1418 #define	FRF_BB_TX_VLAN0_PORT0_EN_WIDTH 1
1419 #define	FRF_BB_TX_VLAN0_LBN 0
1420 #define	FRF_BB_TX_VLAN0_WIDTH 12
1421 
1422 /* TX_IPFIL_PORTEN_REG: Transmit filter control register */
1423 #define	FR_BZ_TX_IPFIL_PORTEN 0x00000af0
1424 #define	FRF_BZ_TX_MADR0_FIL_EN_LBN 64
1425 #define	FRF_BZ_TX_MADR0_FIL_EN_WIDTH 1
1426 #define	FRF_BB_TX_IPFIL31_PORT_EN_LBN 62
1427 #define	FRF_BB_TX_IPFIL31_PORT_EN_WIDTH 1
1428 #define	FRF_BB_TX_IPFIL30_PORT_EN_LBN 60
1429 #define	FRF_BB_TX_IPFIL30_PORT_EN_WIDTH 1
1430 #define	FRF_BB_TX_IPFIL29_PORT_EN_LBN 58
1431 #define	FRF_BB_TX_IPFIL29_PORT_EN_WIDTH 1
1432 #define	FRF_BB_TX_IPFIL28_PORT_EN_LBN 56
1433 #define	FRF_BB_TX_IPFIL28_PORT_EN_WIDTH 1
1434 #define	FRF_BB_TX_IPFIL27_PORT_EN_LBN 54
1435 #define	FRF_BB_TX_IPFIL27_PORT_EN_WIDTH 1
1436 #define	FRF_BB_TX_IPFIL26_PORT_EN_LBN 52
1437 #define	FRF_BB_TX_IPFIL26_PORT_EN_WIDTH 1
1438 #define	FRF_BB_TX_IPFIL25_PORT_EN_LBN 50
1439 #define	FRF_BB_TX_IPFIL25_PORT_EN_WIDTH 1
1440 #define	FRF_BB_TX_IPFIL24_PORT_EN_LBN 48
1441 #define	FRF_BB_TX_IPFIL24_PORT_EN_WIDTH 1
1442 #define	FRF_BB_TX_IPFIL23_PORT_EN_LBN 46
1443 #define	FRF_BB_TX_IPFIL23_PORT_EN_WIDTH 1
1444 #define	FRF_BB_TX_IPFIL22_PORT_EN_LBN 44
1445 #define	FRF_BB_TX_IPFIL22_PORT_EN_WIDTH 1
1446 #define	FRF_BB_TX_IPFIL21_PORT_EN_LBN 42
1447 #define	FRF_BB_TX_IPFIL21_PORT_EN_WIDTH 1
1448 #define	FRF_BB_TX_IPFIL20_PORT_EN_LBN 40
1449 #define	FRF_BB_TX_IPFIL20_PORT_EN_WIDTH 1
1450 #define	FRF_BB_TX_IPFIL19_PORT_EN_LBN 38
1451 #define	FRF_BB_TX_IPFIL19_PORT_EN_WIDTH 1
1452 #define	FRF_BB_TX_IPFIL18_PORT_EN_LBN 36
1453 #define	FRF_BB_TX_IPFIL18_PORT_EN_WIDTH 1
1454 #define	FRF_BB_TX_IPFIL17_PORT_EN_LBN 34
1455 #define	FRF_BB_TX_IPFIL17_PORT_EN_WIDTH 1
1456 #define	FRF_BB_TX_IPFIL16_PORT_EN_LBN 32
1457 #define	FRF_BB_TX_IPFIL16_PORT_EN_WIDTH 1
1458 #define	FRF_BB_TX_IPFIL15_PORT_EN_LBN 30
1459 #define	FRF_BB_TX_IPFIL15_PORT_EN_WIDTH 1
1460 #define	FRF_BB_TX_IPFIL14_PORT_EN_LBN 28
1461 #define	FRF_BB_TX_IPFIL14_PORT_EN_WIDTH 1
1462 #define	FRF_BB_TX_IPFIL13_PORT_EN_LBN 26
1463 #define	FRF_BB_TX_IPFIL13_PORT_EN_WIDTH 1
1464 #define	FRF_BB_TX_IPFIL12_PORT_EN_LBN 24
1465 #define	FRF_BB_TX_IPFIL12_PORT_EN_WIDTH 1
1466 #define	FRF_BB_TX_IPFIL11_PORT_EN_LBN 22
1467 #define	FRF_BB_TX_IPFIL11_PORT_EN_WIDTH 1
1468 #define	FRF_BB_TX_IPFIL10_PORT_EN_LBN 20
1469 #define	FRF_BB_TX_IPFIL10_PORT_EN_WIDTH 1
1470 #define	FRF_BB_TX_IPFIL9_PORT_EN_LBN 18
1471 #define	FRF_BB_TX_IPFIL9_PORT_EN_WIDTH 1
1472 #define	FRF_BB_TX_IPFIL8_PORT_EN_LBN 16
1473 #define	FRF_BB_TX_IPFIL8_PORT_EN_WIDTH 1
1474 #define	FRF_BB_TX_IPFIL7_PORT_EN_LBN 14
1475 #define	FRF_BB_TX_IPFIL7_PORT_EN_WIDTH 1
1476 #define	FRF_BB_TX_IPFIL6_PORT_EN_LBN 12
1477 #define	FRF_BB_TX_IPFIL6_PORT_EN_WIDTH 1
1478 #define	FRF_BB_TX_IPFIL5_PORT_EN_LBN 10
1479 #define	FRF_BB_TX_IPFIL5_PORT_EN_WIDTH 1
1480 #define	FRF_BB_TX_IPFIL4_PORT_EN_LBN 8
1481 #define	FRF_BB_TX_IPFIL4_PORT_EN_WIDTH 1
1482 #define	FRF_BB_TX_IPFIL3_PORT_EN_LBN 6
1483 #define	FRF_BB_TX_IPFIL3_PORT_EN_WIDTH 1
1484 #define	FRF_BB_TX_IPFIL2_PORT_EN_LBN 4
1485 #define	FRF_BB_TX_IPFIL2_PORT_EN_WIDTH 1
1486 #define	FRF_BB_TX_IPFIL1_PORT_EN_LBN 2
1487 #define	FRF_BB_TX_IPFIL1_PORT_EN_WIDTH 1
1488 #define	FRF_BB_TX_IPFIL0_PORT_EN_LBN 0
1489 #define	FRF_BB_TX_IPFIL0_PORT_EN_WIDTH 1
1490 
1491 /* TX_IPFIL_TBL: Transmit IP source address filter table */
1492 #define	FR_BB_TX_IPFIL_TBL 0x00000b00
1493 #define	FR_BB_TX_IPFIL_TBL_STEP 16
1494 #define	FR_BB_TX_IPFIL_TBL_ROWS 16
1495 #define	FRF_BB_TX_IPFIL_MASK_1_LBN 96
1496 #define	FRF_BB_TX_IPFIL_MASK_1_WIDTH 32
1497 #define	FRF_BB_TX_IP_SRC_ADR_1_LBN 64
1498 #define	FRF_BB_TX_IP_SRC_ADR_1_WIDTH 32
1499 #define	FRF_BB_TX_IPFIL_MASK_0_LBN 32
1500 #define	FRF_BB_TX_IPFIL_MASK_0_WIDTH 32
1501 #define	FRF_BB_TX_IP_SRC_ADR_0_LBN 0
1502 #define	FRF_BB_TX_IP_SRC_ADR_0_WIDTH 32
1503 
1504 /* MD_TXD_REG: PHY management transmit data register */
1505 #define	FR_AB_MD_TXD 0x00000c00
1506 #define	FRF_AB_MD_TXD_LBN 0
1507 #define	FRF_AB_MD_TXD_WIDTH 16
1508 
1509 /* MD_RXD_REG: PHY management receive data register */
1510 #define	FR_AB_MD_RXD 0x00000c10
1511 #define	FRF_AB_MD_RXD_LBN 0
1512 #define	FRF_AB_MD_RXD_WIDTH 16
1513 
1514 /* MD_CS_REG: PHY management configuration & status register */
1515 #define	FR_AB_MD_CS 0x00000c20
1516 #define	FRF_AB_MD_RD_EN_CMD_LBN 15
1517 #define	FRF_AB_MD_RD_EN_CMD_WIDTH 1
1518 #define	FRF_AB_MD_WR_EN_CMD_LBN 14
1519 #define	FRF_AB_MD_WR_EN_CMD_WIDTH 1
1520 #define	FRF_AB_MD_ADDR_CMD_LBN 13
1521 #define	FRF_AB_MD_ADDR_CMD_WIDTH 1
1522 #define	FRF_AB_MD_PT_LBN 7
1523 #define	FRF_AB_MD_PT_WIDTH 3
1524 #define	FRF_AB_MD_PL_LBN 6
1525 #define	FRF_AB_MD_PL_WIDTH 1
1526 #define	FRF_AB_MD_INT_CLR_LBN 5
1527 #define	FRF_AB_MD_INT_CLR_WIDTH 1
1528 #define	FRF_AB_MD_GC_LBN 4
1529 #define	FRF_AB_MD_GC_WIDTH 1
1530 #define	FRF_AB_MD_PRSP_LBN 3
1531 #define	FRF_AB_MD_PRSP_WIDTH 1
1532 #define	FRF_AB_MD_RIC_LBN 2
1533 #define	FRF_AB_MD_RIC_WIDTH 1
1534 #define	FRF_AB_MD_RDC_LBN 1
1535 #define	FRF_AB_MD_RDC_WIDTH 1
1536 #define	FRF_AB_MD_WRC_LBN 0
1537 #define	FRF_AB_MD_WRC_WIDTH 1
1538 
1539 /* MD_PHY_ADR_REG: PHY management PHY address register */
1540 #define	FR_AB_MD_PHY_ADR 0x00000c30
1541 #define	FRF_AB_MD_PHY_ADR_LBN 0
1542 #define	FRF_AB_MD_PHY_ADR_WIDTH 16
1543 
1544 /* MD_ID_REG: PHY management ID register */
1545 #define	FR_AB_MD_ID 0x00000c40
1546 #define	FRF_AB_MD_PRT_ADR_LBN 11
1547 #define	FRF_AB_MD_PRT_ADR_WIDTH 5
1548 #define	FRF_AB_MD_DEV_ADR_LBN 6
1549 #define	FRF_AB_MD_DEV_ADR_WIDTH 5
1550 
1551 /* MD_STAT_REG: PHY management status & mask register */
1552 #define	FR_AB_MD_STAT 0x00000c50
1553 #define	FRF_AB_MD_PINT_LBN 4
1554 #define	FRF_AB_MD_PINT_WIDTH 1
1555 #define	FRF_AB_MD_DONE_LBN 3
1556 #define	FRF_AB_MD_DONE_WIDTH 1
1557 #define	FRF_AB_MD_BSERR_LBN 2
1558 #define	FRF_AB_MD_BSERR_WIDTH 1
1559 #define	FRF_AB_MD_LNFL_LBN 1
1560 #define	FRF_AB_MD_LNFL_WIDTH 1
1561 #define	FRF_AB_MD_BSY_LBN 0
1562 #define	FRF_AB_MD_BSY_WIDTH 1
1563 
1564 /* MAC_STAT_DMA_REG: Port MAC statistical counter DMA register */
1565 #define	FR_AB_MAC_STAT_DMA 0x00000c60
1566 #define	FRF_AB_MAC_STAT_DMA_CMD_LBN 48
1567 #define	FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
1568 #define	FRF_AB_MAC_STAT_DMA_ADR_LBN 0
1569 #define	FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
1570 
1571 /* MAC_CTRL_REG: Port MAC control register */
1572 #define	FR_AB_MAC_CTRL 0x00000c80
1573 #define	FRF_AB_MAC_XOFF_VAL_LBN 16
1574 #define	FRF_AB_MAC_XOFF_VAL_WIDTH 16
1575 #define	FRF_BB_TXFIFO_DRAIN_EN_LBN 7
1576 #define	FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
1577 #define	FRF_AB_MAC_XG_DISTXCRC_LBN 5
1578 #define	FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
1579 #define	FRF_AB_MAC_BCAD_ACPT_LBN 4
1580 #define	FRF_AB_MAC_BCAD_ACPT_WIDTH 1
1581 #define	FRF_AB_MAC_UC_PROM_LBN 3
1582 #define	FRF_AB_MAC_UC_PROM_WIDTH 1
1583 #define	FRF_AB_MAC_LINK_STATUS_LBN 2
1584 #define	FRF_AB_MAC_LINK_STATUS_WIDTH 1
1585 #define	FRF_AB_MAC_SPEED_LBN 0
1586 #define	FRF_AB_MAC_SPEED_WIDTH 2
1587 #define	FFE_AB_MAC_SPEED_10G 3
1588 #define	FFE_AB_MAC_SPEED_1G 2
1589 #define	FFE_AB_MAC_SPEED_100M 1
1590 #define	FFE_AB_MAC_SPEED_10M 0
1591 
1592 /* GEN_MODE_REG: General Purpose mode register (external interrupt mask) */
1593 #define	FR_BB_GEN_MODE 0x00000c90
1594 #define	FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
1595 #define	FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
1596 #define	FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
1597 #define	FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
1598 #define	FRF_BB_XFP_PHY_INT_MASK_LBN 1
1599 #define	FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
1600 #define	FRF_BB_XG_PHY_INT_MASK_LBN 0
1601 #define	FRF_BB_XG_PHY_INT_MASK_WIDTH 1
1602 
1603 /* MAC_MC_HASH_REG0: Multicast address hash table */
1604 #define	FR_AB_MAC_MC_HASH_REG0 0x00000ca0
1605 #define	FRF_AB_MAC_MCAST_HASH0_LBN 0
1606 #define	FRF_AB_MAC_MCAST_HASH0_WIDTH 128
1607 
1608 /* MAC_MC_HASH_REG1: Multicast address hash table */
1609 #define	FR_AB_MAC_MC_HASH_REG1 0x00000cb0
1610 #define	FRF_AB_MAC_MCAST_HASH1_LBN 0
1611 #define	FRF_AB_MAC_MCAST_HASH1_WIDTH 128
1612 
1613 /* GM_CFG1_REG: GMAC configuration register 1 */
1614 #define	FR_AB_GM_CFG1 0x00000e00
1615 #define	FRF_AB_GM_SW_RST_LBN 31
1616 #define	FRF_AB_GM_SW_RST_WIDTH 1
1617 #define	FRF_AB_GM_SIM_RST_LBN 30
1618 #define	FRF_AB_GM_SIM_RST_WIDTH 1
1619 #define	FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
1620 #define	FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
1621 #define	FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
1622 #define	FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
1623 #define	FRF_AB_GM_RST_RX_FUNC_LBN 17
1624 #define	FRF_AB_GM_RST_RX_FUNC_WIDTH 1
1625 #define	FRF_AB_GM_RST_TX_FUNC_LBN 16
1626 #define	FRF_AB_GM_RST_TX_FUNC_WIDTH 1
1627 #define	FRF_AB_GM_LOOP_LBN 8
1628 #define	FRF_AB_GM_LOOP_WIDTH 1
1629 #define	FRF_AB_GM_RX_FC_EN_LBN 5
1630 #define	FRF_AB_GM_RX_FC_EN_WIDTH 1
1631 #define	FRF_AB_GM_TX_FC_EN_LBN 4
1632 #define	FRF_AB_GM_TX_FC_EN_WIDTH 1
1633 #define	FRF_AB_GM_SYNC_RXEN_LBN 3
1634 #define	FRF_AB_GM_SYNC_RXEN_WIDTH 1
1635 #define	FRF_AB_GM_RX_EN_LBN 2
1636 #define	FRF_AB_GM_RX_EN_WIDTH 1
1637 #define	FRF_AB_GM_SYNC_TXEN_LBN 1
1638 #define	FRF_AB_GM_SYNC_TXEN_WIDTH 1
1639 #define	FRF_AB_GM_TX_EN_LBN 0
1640 #define	FRF_AB_GM_TX_EN_WIDTH 1
1641 
1642 /* GM_CFG2_REG: GMAC configuration register 2 */
1643 #define	FR_AB_GM_CFG2 0x00000e10
1644 #define	FRF_AB_GM_PAMBL_LEN_LBN 12
1645 #define	FRF_AB_GM_PAMBL_LEN_WIDTH 4
1646 #define	FRF_AB_GM_IF_MODE_LBN 8
1647 #define	FRF_AB_GM_IF_MODE_WIDTH 2
1648 #define	FFE_AB_IF_MODE_BYTE_MODE 2
1649 #define	FFE_AB_IF_MODE_NIBBLE_MODE 1
1650 #define	FRF_AB_GM_HUGE_FRM_EN_LBN 5
1651 #define	FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
1652 #define	FRF_AB_GM_LEN_CHK_LBN 4
1653 #define	FRF_AB_GM_LEN_CHK_WIDTH 1
1654 #define	FRF_AB_GM_PAD_CRC_EN_LBN 2
1655 #define	FRF_AB_GM_PAD_CRC_EN_WIDTH 1
1656 #define	FRF_AB_GM_CRC_EN_LBN 1
1657 #define	FRF_AB_GM_CRC_EN_WIDTH 1
1658 #define	FRF_AB_GM_FD_LBN 0
1659 #define	FRF_AB_GM_FD_WIDTH 1
1660 
1661 /* GM_IPG_REG: GMAC IPG register */
1662 #define	FR_AB_GM_IPG 0x00000e20
1663 #define	FRF_AB_GM_NONB2B_IPG1_LBN 24
1664 #define	FRF_AB_GM_NONB2B_IPG1_WIDTH 7
1665 #define	FRF_AB_GM_NONB2B_IPG2_LBN 16
1666 #define	FRF_AB_GM_NONB2B_IPG2_WIDTH 7
1667 #define	FRF_AB_GM_MIN_IPG_ENF_LBN 8
1668 #define	FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
1669 #define	FRF_AB_GM_B2B_IPG_LBN 0
1670 #define	FRF_AB_GM_B2B_IPG_WIDTH 7
1671 
1672 /* GM_HD_REG: GMAC half duplex register */
1673 #define	FR_AB_GM_HD 0x00000e30
1674 #define	FRF_AB_GM_ALT_BOFF_VAL_LBN 20
1675 #define	FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
1676 #define	FRF_AB_GM_ALT_BOFF_EN_LBN 19
1677 #define	FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
1678 #define	FRF_AB_GM_BP_NO_BOFF_LBN 18
1679 #define	FRF_AB_GM_BP_NO_BOFF_WIDTH 1
1680 #define	FRF_AB_GM_DIS_BOFF_LBN 17
1681 #define	FRF_AB_GM_DIS_BOFF_WIDTH 1
1682 #define	FRF_AB_GM_EXDEF_TX_EN_LBN 16
1683 #define	FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
1684 #define	FRF_AB_GM_RTRY_LIMIT_LBN 12
1685 #define	FRF_AB_GM_RTRY_LIMIT_WIDTH 4
1686 #define	FRF_AB_GM_COL_WIN_LBN 0
1687 #define	FRF_AB_GM_COL_WIN_WIDTH 10
1688 
1689 /* GM_MAX_FLEN_REG: GMAC maximum frame length register */
1690 #define	FR_AB_GM_MAX_FLEN 0x00000e40
1691 #define	FRF_AB_GM_MAX_FLEN_LBN 0
1692 #define	FRF_AB_GM_MAX_FLEN_WIDTH 16
1693 
1694 /* GM_TEST_REG: GMAC test register */
1695 #define	FR_AB_GM_TEST 0x00000e70
1696 #define	FRF_AB_GM_MAX_BOFF_LBN 3
1697 #define	FRF_AB_GM_MAX_BOFF_WIDTH 1
1698 #define	FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
1699 #define	FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
1700 #define	FRF_AB_GM_TEST_PAUSE_LBN 1
1701 #define	FRF_AB_GM_TEST_PAUSE_WIDTH 1
1702 #define	FRF_AB_GM_SHORT_SLOT_LBN 0
1703 #define	FRF_AB_GM_SHORT_SLOT_WIDTH 1
1704 
1705 /* GM_ADR1_REG: GMAC station address register 1 */
1706 #define	FR_AB_GM_ADR1 0x00000f00
1707 #define	FRF_AB_GM_ADR_B0_LBN 24
1708 #define	FRF_AB_GM_ADR_B0_WIDTH 8
1709 #define	FRF_AB_GM_ADR_B1_LBN 16
1710 #define	FRF_AB_GM_ADR_B1_WIDTH 8
1711 #define	FRF_AB_GM_ADR_B2_LBN 8
1712 #define	FRF_AB_GM_ADR_B2_WIDTH 8
1713 #define	FRF_AB_GM_ADR_B3_LBN 0
1714 #define	FRF_AB_GM_ADR_B3_WIDTH 8
1715 
1716 /* GM_ADR2_REG: GMAC station address register 2 */
1717 #define	FR_AB_GM_ADR2 0x00000f10
1718 #define	FRF_AB_GM_ADR_B4_LBN 24
1719 #define	FRF_AB_GM_ADR_B4_WIDTH 8
1720 #define	FRF_AB_GM_ADR_B5_LBN 16
1721 #define	FRF_AB_GM_ADR_B5_WIDTH 8
1722 
1723 /* GMF_CFG0_REG: GMAC FIFO configuration register 0 */
1724 #define	FR_AB_GMF_CFG0 0x00000f20
1725 #define	FRF_AB_GMF_FTFENRPLY_LBN 20
1726 #define	FRF_AB_GMF_FTFENRPLY_WIDTH 1
1727 #define	FRF_AB_GMF_STFENRPLY_LBN 19
1728 #define	FRF_AB_GMF_STFENRPLY_WIDTH 1
1729 #define	FRF_AB_GMF_FRFENRPLY_LBN 18
1730 #define	FRF_AB_GMF_FRFENRPLY_WIDTH 1
1731 #define	FRF_AB_GMF_SRFENRPLY_LBN 17
1732 #define	FRF_AB_GMF_SRFENRPLY_WIDTH 1
1733 #define	FRF_AB_GMF_WTMENRPLY_LBN 16
1734 #define	FRF_AB_GMF_WTMENRPLY_WIDTH 1
1735 #define	FRF_AB_GMF_FTFENREQ_LBN 12
1736 #define	FRF_AB_GMF_FTFENREQ_WIDTH 1
1737 #define	FRF_AB_GMF_STFENREQ_LBN 11
1738 #define	FRF_AB_GMF_STFENREQ_WIDTH 1
1739 #define	FRF_AB_GMF_FRFENREQ_LBN 10
1740 #define	FRF_AB_GMF_FRFENREQ_WIDTH 1
1741 #define	FRF_AB_GMF_SRFENREQ_LBN 9
1742 #define	FRF_AB_GMF_SRFENREQ_WIDTH 1
1743 #define	FRF_AB_GMF_WTMENREQ_LBN 8
1744 #define	FRF_AB_GMF_WTMENREQ_WIDTH 1
1745 #define	FRF_AB_GMF_HSTRSTFT_LBN 4
1746 #define	FRF_AB_GMF_HSTRSTFT_WIDTH 1
1747 #define	FRF_AB_GMF_HSTRSTST_LBN 3
1748 #define	FRF_AB_GMF_HSTRSTST_WIDTH 1
1749 #define	FRF_AB_GMF_HSTRSTFR_LBN 2
1750 #define	FRF_AB_GMF_HSTRSTFR_WIDTH 1
1751 #define	FRF_AB_GMF_HSTRSTSR_LBN 1
1752 #define	FRF_AB_GMF_HSTRSTSR_WIDTH 1
1753 #define	FRF_AB_GMF_HSTRSTWT_LBN 0
1754 #define	FRF_AB_GMF_HSTRSTWT_WIDTH 1
1755 
1756 /* GMF_CFG1_REG: GMAC FIFO configuration register 1 */
1757 #define	FR_AB_GMF_CFG1 0x00000f30
1758 #define	FRF_AB_GMF_CFGFRTH_LBN 16
1759 #define	FRF_AB_GMF_CFGFRTH_WIDTH 5
1760 #define	FRF_AB_GMF_CFGXOFFRTX_LBN 0
1761 #define	FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
1762 
1763 /* GMF_CFG2_REG: GMAC FIFO configuration register 2 */
1764 #define	FR_AB_GMF_CFG2 0x00000f40
1765 #define	FRF_AB_GMF_CFGHWM_LBN 16
1766 #define	FRF_AB_GMF_CFGHWM_WIDTH 6
1767 #define	FRF_AB_GMF_CFGLWM_LBN 0
1768 #define	FRF_AB_GMF_CFGLWM_WIDTH 6
1769 
1770 /* GMF_CFG3_REG: GMAC FIFO configuration register 3 */
1771 #define	FR_AB_GMF_CFG3 0x00000f50
1772 #define	FRF_AB_GMF_CFGHWMFT_LBN 16
1773 #define	FRF_AB_GMF_CFGHWMFT_WIDTH 6
1774 #define	FRF_AB_GMF_CFGFTTH_LBN 0
1775 #define	FRF_AB_GMF_CFGFTTH_WIDTH 6
1776 
1777 /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */
1778 #define	FR_AB_GMF_CFG4 0x00000f60
1779 #define	FRF_AB_GMF_HSTFLTRFRM_LBN 0
1780 #define	FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
1781 
1782 /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */
1783 #define	FR_AB_GMF_CFG5 0x00000f70
1784 #define	FRF_AB_GMF_CFGHDPLX_LBN 22
1785 #define	FRF_AB_GMF_CFGHDPLX_WIDTH 1
1786 #define	FRF_AB_GMF_SRFULL_LBN 21
1787 #define	FRF_AB_GMF_SRFULL_WIDTH 1
1788 #define	FRF_AB_GMF_HSTSRFULLCLR_LBN 20
1789 #define	FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
1790 #define	FRF_AB_GMF_CFGBYTMODE_LBN 19
1791 #define	FRF_AB_GMF_CFGBYTMODE_WIDTH 1
1792 #define	FRF_AB_GMF_HSTDRPLT64_LBN 18
1793 #define	FRF_AB_GMF_HSTDRPLT64_WIDTH 1
1794 #define	FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
1795 #define	FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
1796 
1797 /* TX_SRC_MAC_TBL: Transmit IP source address filter table */
1798 #define	FR_BB_TX_SRC_MAC_TBL 0x00001000
1799 #define	FR_BB_TX_SRC_MAC_TBL_STEP 16
1800 #define	FR_BB_TX_SRC_MAC_TBL_ROWS 16
1801 #define	FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
1802 #define	FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
1803 #define	FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
1804 #define	FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
1805 
1806 /* TX_SRC_MAC_CTL_REG: Transmit MAC source address filter control */
1807 #define	FR_BB_TX_SRC_MAC_CTL 0x00001100
1808 #define	FRF_BB_TX_SRC_DROP_CTR_LBN 16
1809 #define	FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
1810 #define	FRF_BB_TX_SRC_FLTR_EN_LBN 15
1811 #define	FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
1812 #define	FRF_BB_TX_DROP_CTR_CLR_LBN 12
1813 #define	FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
1814 #define	FRF_BB_TX_MAC_QID_SEL_LBN 0
1815 #define	FRF_BB_TX_MAC_QID_SEL_WIDTH 3
1816 
1817 /* XM_ADR_LO_REG: XGMAC address register low */
1818 #define	FR_AB_XM_ADR_LO 0x00001200
1819 #define	FRF_AB_XM_ADR_LO_LBN 0
1820 #define	FRF_AB_XM_ADR_LO_WIDTH 32
1821 
1822 /* XM_ADR_HI_REG: XGMAC address register high */
1823 #define	FR_AB_XM_ADR_HI 0x00001210
1824 #define	FRF_AB_XM_ADR_HI_LBN 0
1825 #define	FRF_AB_XM_ADR_HI_WIDTH 16
1826 
1827 /* XM_GLB_CFG_REG: XGMAC global configuration */
1828 #define	FR_AB_XM_GLB_CFG 0x00001220
1829 #define	FRF_AB_XM_RMTFLT_GEN_LBN 17
1830 #define	FRF_AB_XM_RMTFLT_GEN_WIDTH 1
1831 #define	FRF_AB_XM_DEBUG_MODE_LBN 16
1832 #define	FRF_AB_XM_DEBUG_MODE_WIDTH 1
1833 #define	FRF_AB_XM_RX_STAT_EN_LBN 11
1834 #define	FRF_AB_XM_RX_STAT_EN_WIDTH 1
1835 #define	FRF_AB_XM_TX_STAT_EN_LBN 10
1836 #define	FRF_AB_XM_TX_STAT_EN_WIDTH 1
1837 #define	FRF_AB_XM_RX_JUMBO_MODE_LBN 6
1838 #define	FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
1839 #define	FRF_AB_XM_WAN_MODE_LBN 5
1840 #define	FRF_AB_XM_WAN_MODE_WIDTH 1
1841 #define	FRF_AB_XM_INTCLR_MODE_LBN 3
1842 #define	FRF_AB_XM_INTCLR_MODE_WIDTH 1
1843 #define	FRF_AB_XM_CORE_RST_LBN 0
1844 #define	FRF_AB_XM_CORE_RST_WIDTH 1
1845 
1846 /* XM_TX_CFG_REG: XGMAC transmit configuration */
1847 #define	FR_AB_XM_TX_CFG 0x00001230
1848 #define	FRF_AB_XM_TX_PROG_LBN 24
1849 #define	FRF_AB_XM_TX_PROG_WIDTH 1
1850 #define	FRF_AB_XM_IPG_LBN 16
1851 #define	FRF_AB_XM_IPG_WIDTH 4
1852 #define	FRF_AB_XM_FCNTL_LBN 10
1853 #define	FRF_AB_XM_FCNTL_WIDTH 1
1854 #define	FRF_AB_XM_TXCRC_LBN 8
1855 #define	FRF_AB_XM_TXCRC_WIDTH 1
1856 #define	FRF_AB_XM_EDRC_LBN 6
1857 #define	FRF_AB_XM_EDRC_WIDTH 1
1858 #define	FRF_AB_XM_AUTO_PAD_LBN 5
1859 #define	FRF_AB_XM_AUTO_PAD_WIDTH 1
1860 #define	FRF_AB_XM_TX_PRMBL_LBN 2
1861 #define	FRF_AB_XM_TX_PRMBL_WIDTH 1
1862 #define	FRF_AB_XM_TXEN_LBN 1
1863 #define	FRF_AB_XM_TXEN_WIDTH 1
1864 #define	FRF_AB_XM_TX_RST_LBN 0
1865 #define	FRF_AB_XM_TX_RST_WIDTH 1
1866 
1867 /* XM_RX_CFG_REG: XGMAC receive configuration */
1868 #define	FR_AB_XM_RX_CFG 0x00001240
1869 #define	FRF_AB_XM_PASS_LENERR_LBN 26
1870 #define	FRF_AB_XM_PASS_LENERR_WIDTH 1
1871 #define	FRF_AB_XM_PASS_CRC_ERR_LBN 25
1872 #define	FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
1873 #define	FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
1874 #define	FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
1875 #define	FRF_AB_XM_REJ_BCAST_LBN 20
1876 #define	FRF_AB_XM_REJ_BCAST_WIDTH 1
1877 #define	FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
1878 #define	FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
1879 #define	FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
1880 #define	FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
1881 #define	FRF_AB_XM_AUTO_DEPAD_LBN 8
1882 #define	FRF_AB_XM_AUTO_DEPAD_WIDTH 1
1883 #define	FRF_AB_XM_RXCRC_LBN 3
1884 #define	FRF_AB_XM_RXCRC_WIDTH 1
1885 #define	FRF_AB_XM_RX_PRMBL_LBN 2
1886 #define	FRF_AB_XM_RX_PRMBL_WIDTH 1
1887 #define	FRF_AB_XM_RXEN_LBN 1
1888 #define	FRF_AB_XM_RXEN_WIDTH 1
1889 #define	FRF_AB_XM_RX_RST_LBN 0
1890 #define	FRF_AB_XM_RX_RST_WIDTH 1
1891 
1892 /* XM_MGT_INT_MASK: documentation to be written for sum_XM_MGT_INT_MASK */
1893 #define	FR_AB_XM_MGT_INT_MASK 0x00001250
1894 #define	FRF_AB_XM_MSK_STA_INTR_LBN 16
1895 #define	FRF_AB_XM_MSK_STA_INTR_WIDTH 1
1896 #define	FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
1897 #define	FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
1898 #define	FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
1899 #define	FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
1900 #define	FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
1901 #define	FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
1902 #define	FRF_AB_XM_MSK_RMTFLT_LBN 1
1903 #define	FRF_AB_XM_MSK_RMTFLT_WIDTH 1
1904 #define	FRF_AB_XM_MSK_LCLFLT_LBN 0
1905 #define	FRF_AB_XM_MSK_LCLFLT_WIDTH 1
1906 
1907 /* XM_FC_REG: XGMAC flow control register */
1908 #define	FR_AB_XM_FC 0x00001270
1909 #define	FRF_AB_XM_PAUSE_TIME_LBN 16
1910 #define	FRF_AB_XM_PAUSE_TIME_WIDTH 16
1911 #define	FRF_AB_XM_RX_MAC_STAT_LBN 11
1912 #define	FRF_AB_XM_RX_MAC_STAT_WIDTH 1
1913 #define	FRF_AB_XM_TX_MAC_STAT_LBN 10
1914 #define	FRF_AB_XM_TX_MAC_STAT_WIDTH 1
1915 #define	FRF_AB_XM_MCNTL_PASS_LBN 8
1916 #define	FRF_AB_XM_MCNTL_PASS_WIDTH 2
1917 #define	FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
1918 #define	FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
1919 #define	FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
1920 #define	FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
1921 #define	FRF_AB_XM_ZPAUSE_LBN 2
1922 #define	FRF_AB_XM_ZPAUSE_WIDTH 1
1923 #define	FRF_AB_XM_XMIT_PAUSE_LBN 1
1924 #define	FRF_AB_XM_XMIT_PAUSE_WIDTH 1
1925 #define	FRF_AB_XM_DIS_FCNTL_LBN 0
1926 #define	FRF_AB_XM_DIS_FCNTL_WIDTH 1
1927 
1928 /* XM_PAUSE_TIME_REG: XGMAC pause time register */
1929 #define	FR_AB_XM_PAUSE_TIME 0x00001290
1930 #define	FRF_AB_XM_TX_PAUSE_CNT_LBN 16
1931 #define	FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
1932 #define	FRF_AB_XM_RX_PAUSE_CNT_LBN 0
1933 #define	FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
1934 
1935 /* XM_TX_PARAM_REG: XGMAC transmit parameter register */
1936 #define	FR_AB_XM_TX_PARAM 0x000012d0
1937 #define	FRF_AB_XM_TX_JUMBO_MODE_LBN 31
1938 #define	FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
1939 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
1940 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
1941 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
1942 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
1943 #define	FRF_AB_XM_PAD_CHAR_LBN 0
1944 #define	FRF_AB_XM_PAD_CHAR_WIDTH 8
1945 
1946 /* XM_RX_PARAM_REG: XGMAC receive parameter register */
1947 #define	FR_AB_XM_RX_PARAM 0x000012e0
1948 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
1949 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
1950 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
1951 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
1952 
1953 /* XM_MGT_INT_MSK_REG: XGMAC management interrupt mask register */
1954 #define	FR_AB_XM_MGT_INT_MSK 0x000012f0
1955 #define	FRF_AB_XM_STAT_CNTR_OF_LBN 9
1956 #define	FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
1957 #define	FRF_AB_XM_STAT_CNTR_HF_LBN 8
1958 #define	FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
1959 #define	FRF_AB_XM_PRMBLE_ERR_LBN 2
1960 #define	FRF_AB_XM_PRMBLE_ERR_WIDTH 1
1961 #define	FRF_AB_XM_RMTFLT_LBN 1
1962 #define	FRF_AB_XM_RMTFLT_WIDTH 1
1963 #define	FRF_AB_XM_LCLFLT_LBN 0
1964 #define	FRF_AB_XM_LCLFLT_WIDTH 1
1965 
1966 /* XX_PWR_RST_REG: XGXS/XAUI powerdown/reset register */
1967 #define	FR_AB_XX_PWR_RST 0x00001300
1968 #define	FRF_AB_XX_PWRDND_SIG_LBN 31
1969 #define	FRF_AB_XX_PWRDND_SIG_WIDTH 1
1970 #define	FRF_AB_XX_PWRDNC_SIG_LBN 30
1971 #define	FRF_AB_XX_PWRDNC_SIG_WIDTH 1
1972 #define	FRF_AB_XX_PWRDNB_SIG_LBN 29
1973 #define	FRF_AB_XX_PWRDNB_SIG_WIDTH 1
1974 #define	FRF_AB_XX_PWRDNA_SIG_LBN 28
1975 #define	FRF_AB_XX_PWRDNA_SIG_WIDTH 1
1976 #define	FRF_AB_XX_SIM_MODE_LBN 27
1977 #define	FRF_AB_XX_SIM_MODE_WIDTH 1
1978 #define	FRF_AB_XX_RSTPLLCD_SIG_LBN 25
1979 #define	FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1
1980 #define	FRF_AB_XX_RSTPLLAB_SIG_LBN 24
1981 #define	FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1
1982 #define	FRF_AB_XX_RESETD_SIG_LBN 23
1983 #define	FRF_AB_XX_RESETD_SIG_WIDTH 1
1984 #define	FRF_AB_XX_RESETC_SIG_LBN 22
1985 #define	FRF_AB_XX_RESETC_SIG_WIDTH 1
1986 #define	FRF_AB_XX_RESETB_SIG_LBN 21
1987 #define	FRF_AB_XX_RESETB_SIG_WIDTH 1
1988 #define	FRF_AB_XX_RESETA_SIG_LBN 20
1989 #define	FRF_AB_XX_RESETA_SIG_WIDTH 1
1990 #define	FRF_AB_XX_RSTXGXSRX_SIG_LBN 18
1991 #define	FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1
1992 #define	FRF_AB_XX_RSTXGXSTX_SIG_LBN 17
1993 #define	FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1
1994 #define	FRF_AB_XX_SD_RST_ACT_LBN 16
1995 #define	FRF_AB_XX_SD_RST_ACT_WIDTH 1
1996 #define	FRF_AB_XX_PWRDND_EN_LBN 15
1997 #define	FRF_AB_XX_PWRDND_EN_WIDTH 1
1998 #define	FRF_AB_XX_PWRDNC_EN_LBN 14
1999 #define	FRF_AB_XX_PWRDNC_EN_WIDTH 1
2000 #define	FRF_AB_XX_PWRDNB_EN_LBN 13
2001 #define	FRF_AB_XX_PWRDNB_EN_WIDTH 1
2002 #define	FRF_AB_XX_PWRDNA_EN_LBN 12
2003 #define	FRF_AB_XX_PWRDNA_EN_WIDTH 1
2004 #define	FRF_AB_XX_RSTPLLCD_EN_LBN 9
2005 #define	FRF_AB_XX_RSTPLLCD_EN_WIDTH 1
2006 #define	FRF_AB_XX_RSTPLLAB_EN_LBN 8
2007 #define	FRF_AB_XX_RSTPLLAB_EN_WIDTH 1
2008 #define	FRF_AB_XX_RESETD_EN_LBN 7
2009 #define	FRF_AB_XX_RESETD_EN_WIDTH 1
2010 #define	FRF_AB_XX_RESETC_EN_LBN 6
2011 #define	FRF_AB_XX_RESETC_EN_WIDTH 1
2012 #define	FRF_AB_XX_RESETB_EN_LBN 5
2013 #define	FRF_AB_XX_RESETB_EN_WIDTH 1
2014 #define	FRF_AB_XX_RESETA_EN_LBN 4
2015 #define	FRF_AB_XX_RESETA_EN_WIDTH 1
2016 #define	FRF_AB_XX_RSTXGXSRX_EN_LBN 2
2017 #define	FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1
2018 #define	FRF_AB_XX_RSTXGXSTX_EN_LBN 1
2019 #define	FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1
2020 #define	FRF_AB_XX_RST_XX_EN_LBN 0
2021 #define	FRF_AB_XX_RST_XX_EN_WIDTH 1
2022 
2023 /* XX_SD_CTL_REG: XGXS/XAUI powerdown/reset control register */
2024 #define	FR_AB_XX_SD_CTL 0x00001310
2025 #define	FRF_AB_XX_TERMADJ1_LBN 17
2026 #define	FRF_AB_XX_TERMADJ1_WIDTH 1
2027 #define	FRF_AB_XX_TERMADJ0_LBN 16
2028 #define	FRF_AB_XX_TERMADJ0_WIDTH 1
2029 #define	FRF_AB_XX_HIDRVD_LBN 15
2030 #define	FRF_AB_XX_HIDRVD_WIDTH 1
2031 #define	FRF_AB_XX_LODRVD_LBN 14
2032 #define	FRF_AB_XX_LODRVD_WIDTH 1
2033 #define	FRF_AB_XX_HIDRVC_LBN 13
2034 #define	FRF_AB_XX_HIDRVC_WIDTH 1
2035 #define	FRF_AB_XX_LODRVC_LBN 12
2036 #define	FRF_AB_XX_LODRVC_WIDTH 1
2037 #define	FRF_AB_XX_HIDRVB_LBN 11
2038 #define	FRF_AB_XX_HIDRVB_WIDTH 1
2039 #define	FRF_AB_XX_LODRVB_LBN 10
2040 #define	FRF_AB_XX_LODRVB_WIDTH 1
2041 #define	FRF_AB_XX_HIDRVA_LBN 9
2042 #define	FRF_AB_XX_HIDRVA_WIDTH 1
2043 #define	FRF_AB_XX_LODRVA_LBN 8
2044 #define	FRF_AB_XX_LODRVA_WIDTH 1
2045 #define	FRF_AB_XX_LPBKD_LBN 3
2046 #define	FRF_AB_XX_LPBKD_WIDTH 1
2047 #define	FRF_AB_XX_LPBKC_LBN 2
2048 #define	FRF_AB_XX_LPBKC_WIDTH 1
2049 #define	FRF_AB_XX_LPBKB_LBN 1
2050 #define	FRF_AB_XX_LPBKB_WIDTH 1
2051 #define	FRF_AB_XX_LPBKA_LBN 0
2052 #define	FRF_AB_XX_LPBKA_WIDTH 1
2053 
2054 /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */
2055 #define	FR_AB_XX_TXDRV_CTL 0x00001320
2056 #define	FRF_AB_XX_DEQD_LBN 28
2057 #define	FRF_AB_XX_DEQD_WIDTH 4
2058 #define	FRF_AB_XX_DEQC_LBN 24
2059 #define	FRF_AB_XX_DEQC_WIDTH 4
2060 #define	FRF_AB_XX_DEQB_LBN 20
2061 #define	FRF_AB_XX_DEQB_WIDTH 4
2062 #define	FRF_AB_XX_DEQA_LBN 16
2063 #define	FRF_AB_XX_DEQA_WIDTH 4
2064 #define	FRF_AB_XX_DTXD_LBN 12
2065 #define	FRF_AB_XX_DTXD_WIDTH 4
2066 #define	FRF_AB_XX_DTXC_LBN 8
2067 #define	FRF_AB_XX_DTXC_WIDTH 4
2068 #define	FRF_AB_XX_DTXB_LBN 4
2069 #define	FRF_AB_XX_DTXB_WIDTH 4
2070 #define	FRF_AB_XX_DTXA_LBN 0
2071 #define	FRF_AB_XX_DTXA_WIDTH 4
2072 
2073 /* XX_PRBS_CTL_REG: documentation to be written for sum_XX_PRBS_CTL_REG */
2074 #define	FR_AB_XX_PRBS_CTL 0x00001330
2075 #define	FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30
2076 #define	FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2
2077 #define	FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29
2078 #define	FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1
2079 #define	FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28
2080 #define	FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1
2081 #define	FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26
2082 #define	FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2
2083 #define	FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25
2084 #define	FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1
2085 #define	FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24
2086 #define	FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1
2087 #define	FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22
2088 #define	FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2
2089 #define	FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21
2090 #define	FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1
2091 #define	FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20
2092 #define	FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1
2093 #define	FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18
2094 #define	FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2
2095 #define	FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17
2096 #define	FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1
2097 #define	FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16
2098 #define	FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1
2099 #define	FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14
2100 #define	FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2
2101 #define	FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13
2102 #define	FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1
2103 #define	FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12
2104 #define	FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1
2105 #define	FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10
2106 #define	FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2
2107 #define	FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9
2108 #define	FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1
2109 #define	FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8
2110 #define	FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1
2111 #define	FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6
2112 #define	FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2
2113 #define	FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5
2114 #define	FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1
2115 #define	FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4
2116 #define	FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1
2117 #define	FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2
2118 #define	FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2
2119 #define	FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1
2120 #define	FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1
2121 #define	FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0
2122 #define	FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1
2123 
2124 /* XX_PRBS_CHK_REG: documentation to be written for sum_XX_PRBS_CHK_REG */
2125 #define	FR_AB_XX_PRBS_CHK 0x00001340
2126 #define	FRF_AB_XX_REV_LB_EN_LBN 16
2127 #define	FRF_AB_XX_REV_LB_EN_WIDTH 1
2128 #define	FRF_AB_XX_CH3_DEG_DET_LBN 15
2129 #define	FRF_AB_XX_CH3_DEG_DET_WIDTH 1
2130 #define	FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14
2131 #define	FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1
2132 #define	FRF_AB_XX_CH3_PRBS_FRUN_LBN 13
2133 #define	FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1
2134 #define	FRF_AB_XX_CH3_ERR_CHK_LBN 12
2135 #define	FRF_AB_XX_CH3_ERR_CHK_WIDTH 1
2136 #define	FRF_AB_XX_CH2_DEG_DET_LBN 11
2137 #define	FRF_AB_XX_CH2_DEG_DET_WIDTH 1
2138 #define	FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10
2139 #define	FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1
2140 #define	FRF_AB_XX_CH2_PRBS_FRUN_LBN 9
2141 #define	FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1
2142 #define	FRF_AB_XX_CH2_ERR_CHK_LBN 8
2143 #define	FRF_AB_XX_CH2_ERR_CHK_WIDTH 1
2144 #define	FRF_AB_XX_CH1_DEG_DET_LBN 7
2145 #define	FRF_AB_XX_CH1_DEG_DET_WIDTH 1
2146 #define	FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6
2147 #define	FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1
2148 #define	FRF_AB_XX_CH1_PRBS_FRUN_LBN 5
2149 #define	FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1
2150 #define	FRF_AB_XX_CH1_ERR_CHK_LBN 4
2151 #define	FRF_AB_XX_CH1_ERR_CHK_WIDTH 1
2152 #define	FRF_AB_XX_CH0_DEG_DET_LBN 3
2153 #define	FRF_AB_XX_CH0_DEG_DET_WIDTH 1
2154 #define	FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2
2155 #define	FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1
2156 #define	FRF_AB_XX_CH0_PRBS_FRUN_LBN 1
2157 #define	FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1
2158 #define	FRF_AB_XX_CH0_ERR_CHK_LBN 0
2159 #define	FRF_AB_XX_CH0_ERR_CHK_WIDTH 1
2160 
2161 /* XX_PRBS_ERR_REG: documentation to be written for sum_XX_PRBS_ERR_REG */
2162 #define	FR_AB_XX_PRBS_ERR 0x00001350
2163 #define	FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24
2164 #define	FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8
2165 #define	FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16
2166 #define	FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8
2167 #define	FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8
2168 #define	FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8
2169 #define	FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0
2170 #define	FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8
2171 
2172 /* XX_CORE_STAT_REG: XAUI XGXS core status register */
2173 #define	FR_AB_XX_CORE_STAT 0x00001360
2174 #define	FRF_AB_XX_FORCE_SIG3_LBN 31
2175 #define	FRF_AB_XX_FORCE_SIG3_WIDTH 1
2176 #define	FRF_AB_XX_FORCE_SIG3_VAL_LBN 30
2177 #define	FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1
2178 #define	FRF_AB_XX_FORCE_SIG2_LBN 29
2179 #define	FRF_AB_XX_FORCE_SIG2_WIDTH 1
2180 #define	FRF_AB_XX_FORCE_SIG2_VAL_LBN 28
2181 #define	FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1
2182 #define	FRF_AB_XX_FORCE_SIG1_LBN 27
2183 #define	FRF_AB_XX_FORCE_SIG1_WIDTH 1
2184 #define	FRF_AB_XX_FORCE_SIG1_VAL_LBN 26
2185 #define	FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1
2186 #define	FRF_AB_XX_FORCE_SIG0_LBN 25
2187 #define	FRF_AB_XX_FORCE_SIG0_WIDTH 1
2188 #define	FRF_AB_XX_FORCE_SIG0_VAL_LBN 24
2189 #define	FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1
2190 #define	FRF_AB_XX_XGXS_LB_EN_LBN 23
2191 #define	FRF_AB_XX_XGXS_LB_EN_WIDTH 1
2192 #define	FRF_AB_XX_XGMII_LB_EN_LBN 22
2193 #define	FRF_AB_XX_XGMII_LB_EN_WIDTH 1
2194 #define	FRF_AB_XX_MATCH_FAULT_LBN 21
2195 #define	FRF_AB_XX_MATCH_FAULT_WIDTH 1
2196 #define	FRF_AB_XX_ALIGN_DONE_LBN 20
2197 #define	FRF_AB_XX_ALIGN_DONE_WIDTH 1
2198 #define	FRF_AB_XX_SYNC_STAT3_LBN 19
2199 #define	FRF_AB_XX_SYNC_STAT3_WIDTH 1
2200 #define	FRF_AB_XX_SYNC_STAT2_LBN 18
2201 #define	FRF_AB_XX_SYNC_STAT2_WIDTH 1
2202 #define	FRF_AB_XX_SYNC_STAT1_LBN 17
2203 #define	FRF_AB_XX_SYNC_STAT1_WIDTH 1
2204 #define	FRF_AB_XX_SYNC_STAT0_LBN 16
2205 #define	FRF_AB_XX_SYNC_STAT0_WIDTH 1
2206 #define	FRF_AB_XX_COMMA_DET_CH3_LBN 15
2207 #define	FRF_AB_XX_COMMA_DET_CH3_WIDTH 1
2208 #define	FRF_AB_XX_COMMA_DET_CH2_LBN 14
2209 #define	FRF_AB_XX_COMMA_DET_CH2_WIDTH 1
2210 #define	FRF_AB_XX_COMMA_DET_CH1_LBN 13
2211 #define	FRF_AB_XX_COMMA_DET_CH1_WIDTH 1
2212 #define	FRF_AB_XX_COMMA_DET_CH0_LBN 12
2213 #define	FRF_AB_XX_COMMA_DET_CH0_WIDTH 1
2214 #define	FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11
2215 #define	FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1
2216 #define	FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10
2217 #define	FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1
2218 #define	FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9
2219 #define	FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1
2220 #define	FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8
2221 #define	FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1
2222 #define	FRF_AB_XX_CHAR_ERR_CH3_LBN 7
2223 #define	FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1
2224 #define	FRF_AB_XX_CHAR_ERR_CH2_LBN 6
2225 #define	FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1
2226 #define	FRF_AB_XX_CHAR_ERR_CH1_LBN 5
2227 #define	FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1
2228 #define	FRF_AB_XX_CHAR_ERR_CH0_LBN 4
2229 #define	FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1
2230 #define	FRF_AB_XX_DISPERR_CH3_LBN 3
2231 #define	FRF_AB_XX_DISPERR_CH3_WIDTH 1
2232 #define	FRF_AB_XX_DISPERR_CH2_LBN 2
2233 #define	FRF_AB_XX_DISPERR_CH2_WIDTH 1
2234 #define	FRF_AB_XX_DISPERR_CH1_LBN 1
2235 #define	FRF_AB_XX_DISPERR_CH1_WIDTH 1
2236 #define	FRF_AB_XX_DISPERR_CH0_LBN 0
2237 #define	FRF_AB_XX_DISPERR_CH0_WIDTH 1
2238 
2239 /* RX_DESC_PTR_TBL_KER: Receive descriptor pointer table */
2240 #define	FR_AA_RX_DESC_PTR_TBL_KER 0x00011800
2241 #define	FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
2242 #define	FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
2243 /* RX_DESC_PTR_TBL: Receive descriptor pointer table */
2244 #define	FR_BZ_RX_DESC_PTR_TBL 0x00f40000
2245 #define	FR_BZ_RX_DESC_PTR_TBL_STEP 16
2246 #define	FR_BB_RX_DESC_PTR_TBL_ROWS 4096
2247 #define	FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
2248 #define	FRF_CZ_RX_HDR_SPLIT_LBN 90
2249 #define	FRF_CZ_RX_HDR_SPLIT_WIDTH 1
2250 #define	FRF_AA_RX_RESET_LBN 89
2251 #define	FRF_AA_RX_RESET_WIDTH 1
2252 #define	FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
2253 #define	FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
2254 #define	FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
2255 #define	FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
2256 #define	FRF_AZ_RX_DESC_PREF_ACT_LBN 86
2257 #define	FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
2258 #define	FRF_AZ_RX_DC_HW_RPTR_LBN 80
2259 #define	FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
2260 #define	FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
2261 #define	FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
2262 #define	FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
2263 #define	FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
2264 #define	FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
2265 #define	FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
2266 #define	FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
2267 #define	FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
2268 #define	FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
2269 #define	FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
2270 #define	FRF_AZ_RX_DESCQ_LABEL_LBN 5
2271 #define	FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
2272 #define	FRF_AZ_RX_DESCQ_SIZE_LBN 3
2273 #define	FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
2274 #define	FFE_AZ_RX_DESCQ_SIZE_4K 3
2275 #define	FFE_AZ_RX_DESCQ_SIZE_2K 2
2276 #define	FFE_AZ_RX_DESCQ_SIZE_1K 1
2277 #define	FFE_AZ_RX_DESCQ_SIZE_512 0
2278 #define	FRF_AZ_RX_DESCQ_TYPE_LBN 2
2279 #define	FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
2280 #define	FRF_AZ_RX_DESCQ_JUMBO_LBN 1
2281 #define	FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
2282 #define	FRF_AZ_RX_DESCQ_EN_LBN 0
2283 #define	FRF_AZ_RX_DESCQ_EN_WIDTH 1
2284 
2285 /* TX_DESC_PTR_TBL_KER: Transmit descriptor pointer */
2286 #define	FR_AA_TX_DESC_PTR_TBL_KER 0x00011900
2287 #define	FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
2288 #define	FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
2289 /* TX_DESC_PTR_TBL: Transmit descriptor pointer */
2290 #define	FR_BZ_TX_DESC_PTR_TBL 0x00f50000
2291 #define	FR_BZ_TX_DESC_PTR_TBL_STEP 16
2292 #define	FR_BB_TX_DESC_PTR_TBL_ROWS 4096
2293 #define	FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
2294 #define	FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
2295 #define	FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
2296 #define	FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
2297 #define	FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
2298 #define	FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
2299 #define	FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
2300 #define	FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
2301 #define	FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
2302 #define	FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
2303 #define	FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
2304 #define	FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
2305 #define	FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
2306 #define	FRF_AZ_TX_DESCQ_EN_LBN 88
2307 #define	FRF_AZ_TX_DESCQ_EN_WIDTH 1
2308 #define	FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
2309 #define	FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
2310 #define	FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
2311 #define	FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
2312 #define	FRF_AZ_TX_DC_HW_RPTR_LBN 80
2313 #define	FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
2314 #define	FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
2315 #define	FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
2316 #define	FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
2317 #define	FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
2318 #define	FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
2319 #define	FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
2320 #define	FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
2321 #define	FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
2322 #define	FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
2323 #define	FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
2324 #define	FRF_AZ_TX_DESCQ_LABEL_LBN 5
2325 #define	FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
2326 #define	FRF_AZ_TX_DESCQ_SIZE_LBN 3
2327 #define	FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
2328 #define	FFE_AZ_TX_DESCQ_SIZE_4K 3
2329 #define	FFE_AZ_TX_DESCQ_SIZE_2K 2
2330 #define	FFE_AZ_TX_DESCQ_SIZE_1K 1
2331 #define	FFE_AZ_TX_DESCQ_SIZE_512 0
2332 #define	FRF_AZ_TX_DESCQ_TYPE_LBN 1
2333 #define	FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
2334 #define	FRF_AZ_TX_DESCQ_FLUSH_LBN 0
2335 #define	FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
2336 
2337 /* EVQ_PTR_TBL_KER: Event queue pointer table */
2338 #define	FR_AA_EVQ_PTR_TBL_KER 0x00011a00
2339 #define	FR_AA_EVQ_PTR_TBL_KER_STEP 16
2340 #define	FR_AA_EVQ_PTR_TBL_KER_ROWS 4
2341 /* EVQ_PTR_TBL: Event queue pointer table */
2342 #define	FR_BZ_EVQ_PTR_TBL 0x00f60000
2343 #define	FR_BZ_EVQ_PTR_TBL_STEP 16
2344 #define	FR_CZ_EVQ_PTR_TBL_ROWS 1024
2345 #define	FR_BB_EVQ_PTR_TBL_ROWS 4096
2346 #define	FRF_BZ_EVQ_RPTR_IGN_LBN 40
2347 #define	FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
2348 #define	FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39
2349 #define	FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1
2350 #define	FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39
2351 #define	FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1
2352 #define	FRF_AZ_EVQ_NXT_WPTR_LBN 24
2353 #define	FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
2354 #define	FRF_AZ_EVQ_EN_LBN 23
2355 #define	FRF_AZ_EVQ_EN_WIDTH 1
2356 #define	FRF_AZ_EVQ_SIZE_LBN 20
2357 #define	FRF_AZ_EVQ_SIZE_WIDTH 3
2358 #define	FFE_AZ_EVQ_SIZE_32K 6
2359 #define	FFE_AZ_EVQ_SIZE_16K 5
2360 #define	FFE_AZ_EVQ_SIZE_8K 4
2361 #define	FFE_AZ_EVQ_SIZE_4K 3
2362 #define	FFE_AZ_EVQ_SIZE_2K 2
2363 #define	FFE_AZ_EVQ_SIZE_1K 1
2364 #define	FFE_AZ_EVQ_SIZE_512 0
2365 #define	FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
2366 #define	FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
2367 
2368 /* BUF_HALF_TBL_KER: Buffer table in half buffer table mode direct access by driver */
2369 #define	FR_AA_BUF_HALF_TBL_KER 0x00018000
2370 #define	FR_AA_BUF_HALF_TBL_KER_STEP 8
2371 #define	FR_AA_BUF_HALF_TBL_KER_ROWS 4096
2372 /* BUF_HALF_TBL: Buffer table in half buffer table mode direct access by driver */
2373 #define	FR_BZ_BUF_HALF_TBL 0x00800000
2374 #define	FR_BZ_BUF_HALF_TBL_STEP 8
2375 #define	FR_CZ_BUF_HALF_TBL_ROWS 147456
2376 #define	FR_BB_BUF_HALF_TBL_ROWS 524288
2377 #define	FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
2378 #define	FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
2379 #define	FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
2380 #define	FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
2381 #define	FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
2382 #define	FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
2383 #define	FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
2384 #define	FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
2385 
2386 /* BUF_FULL_TBL_KER: Buffer table in full buffer table mode direct access by driver */
2387 #define	FR_AA_BUF_FULL_TBL_KER 0x00018000
2388 #define	FR_AA_BUF_FULL_TBL_KER_STEP 8
2389 #define	FR_AA_BUF_FULL_TBL_KER_ROWS 4096
2390 /* BUF_FULL_TBL: Buffer table in full buffer table mode direct access by driver */
2391 #define	FR_BZ_BUF_FULL_TBL 0x00800000
2392 #define	FR_BZ_BUF_FULL_TBL_STEP 8
2393 #define	FR_CZ_BUF_FULL_TBL_ROWS 147456
2394 #define	FR_BB_BUF_FULL_TBL_ROWS 917504
2395 #define	FRF_AZ_BUF_FULL_UNUSED_LBN 51
2396 #define	FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
2397 #define	FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
2398 #define	FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
2399 #define	FRF_AZ_BUF_ADR_REGION_LBN 48
2400 #define	FRF_AZ_BUF_ADR_REGION_WIDTH 2
2401 #define	FFE_AZ_BUF_ADR_REGN3 3
2402 #define	FFE_AZ_BUF_ADR_REGN2 2
2403 #define	FFE_AZ_BUF_ADR_REGN1 1
2404 #define	FFE_AZ_BUF_ADR_REGN0 0
2405 #define	FRF_AZ_BUF_ADR_FBUF_LBN 14
2406 #define	FRF_AZ_BUF_ADR_FBUF_WIDTH 34
2407 #define	FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
2408 #define	FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
2409 
2410 /* RX_FILTER_TBL0: TCP/IPv4 Receive filter table */
2411 #define	FR_BZ_RX_FILTER_TBL0 0x00f00000
2412 #define	FR_BZ_RX_FILTER_TBL0_STEP 32
2413 #define	FR_BZ_RX_FILTER_TBL0_ROWS 8192
2414 /* RX_FILTER_TBL1: TCP/IPv4 Receive filter table */
2415 #define	FR_BB_RX_FILTER_TBL1 0x00f00010
2416 #define	FR_BB_RX_FILTER_TBL1_STEP 32
2417 #define	FR_BB_RX_FILTER_TBL1_ROWS 8192
2418 #define	FRF_BZ_RSS_EN_LBN 110
2419 #define	FRF_BZ_RSS_EN_WIDTH 1
2420 #define	FRF_BZ_SCATTER_EN_LBN 109
2421 #define	FRF_BZ_SCATTER_EN_WIDTH 1
2422 #define	FRF_BZ_TCP_UDP_LBN 108
2423 #define	FRF_BZ_TCP_UDP_WIDTH 1
2424 #define	FRF_BZ_RXQ_ID_LBN 96
2425 #define	FRF_BZ_RXQ_ID_WIDTH 12
2426 #define	FRF_BZ_DEST_IP_LBN 64
2427 #define	FRF_BZ_DEST_IP_WIDTH 32
2428 #define	FRF_BZ_DEST_PORT_TCP_LBN 48
2429 #define	FRF_BZ_DEST_PORT_TCP_WIDTH 16
2430 #define	FRF_BZ_SRC_IP_LBN 16
2431 #define	FRF_BZ_SRC_IP_WIDTH 32
2432 #define	FRF_BZ_SRC_TCP_DEST_UDP_LBN 0
2433 #define	FRF_BZ_SRC_TCP_DEST_UDP_WIDTH 16
2434 
2435 /* RX_MAC_FILTER_TBL0: Receive Ethernet filter table */
2436 #define	FR_CZ_RX_MAC_FILTER_TBL0 0x00f00010
2437 #define	FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
2438 #define	FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
2439 #define	FRF_CZ_RMFT_RSS_EN_LBN 75
2440 #define	FRF_CZ_RMFT_RSS_EN_WIDTH 1
2441 #define	FRF_CZ_RMFT_SCATTER_EN_LBN 74
2442 #define	FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
2443 #define	FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
2444 #define	FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
2445 #define	FRF_CZ_RMFT_RXQ_ID_LBN 61
2446 #define	FRF_CZ_RMFT_RXQ_ID_WIDTH 12
2447 #define	FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
2448 #define	FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
2449 #define	FRF_CZ_RMFT_DEST_MAC_LBN 12
2450 #define	FRF_CZ_RMFT_DEST_MAC_WIDTH 48
2451 #define	FRF_CZ_RMFT_VLAN_ID_LBN 0
2452 #define	FRF_CZ_RMFT_VLAN_ID_WIDTH 12
2453 
2454 /* TIMER_TBL: Timer table */
2455 #define	FR_BZ_TIMER_TBL 0x00f70000
2456 #define	FR_BZ_TIMER_TBL_STEP 16
2457 #define	FR_CZ_TIMER_TBL_ROWS 1024
2458 #define	FR_BB_TIMER_TBL_ROWS 4096
2459 #define	FRF_CZ_TIMER_Q_EN_LBN 33
2460 #define	FRF_CZ_TIMER_Q_EN_WIDTH 1
2461 #define	FRF_CZ_INT_ARMD_LBN 32
2462 #define	FRF_CZ_INT_ARMD_WIDTH 1
2463 #define	FRF_CZ_INT_PEND_LBN 31
2464 #define	FRF_CZ_INT_PEND_WIDTH 1
2465 #define	FRF_CZ_HOST_NOTIFY_MODE_LBN 30
2466 #define	FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
2467 #define	FRF_CZ_RELOAD_TIMER_VAL_LBN 16
2468 #define	FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
2469 #define	FRF_CZ_TIMER_MODE_LBN 14
2470 #define	FRF_CZ_TIMER_MODE_WIDTH 2
2471 #define	FFE_CZ_TIMER_MODE_INT_HLDOFF 3
2472 #define	FFE_CZ_TIMER_MODE_TRIG_START 2
2473 #define	FFE_CZ_TIMER_MODE_IMMED_START 1
2474 #define	FFE_CZ_TIMER_MODE_DIS 0
2475 #define	FRF_BB_TIMER_MODE_LBN 12
2476 #define	FRF_BB_TIMER_MODE_WIDTH 2
2477 #define	FFE_BB_TIMER_MODE_INT_HLDOFF 2
2478 #define	FFE_BB_TIMER_MODE_TRIG_START 2
2479 #define	FFE_BB_TIMER_MODE_IMMED_START 1
2480 #define	FFE_BB_TIMER_MODE_DIS 0
2481 #define	FRF_CZ_TIMER_VAL_LBN 0
2482 #define	FRF_CZ_TIMER_VAL_WIDTH 14
2483 #define	FRF_BB_TIMER_VAL_LBN 0
2484 #define	FRF_BB_TIMER_VAL_WIDTH 12
2485 
2486 /* TX_PACE_TBL: Transmit pacing table */
2487 #define	FR_BZ_TX_PACE_TBL 0x00f80000
2488 #define	FR_BZ_TX_PACE_TBL_STEP 16
2489 #define	FR_CZ_TX_PACE_TBL_ROWS 1024
2490 #define	FR_BB_TX_PACE_TBL_ROWS 4096
2491 #define	FRF_BZ_TX_PACE_LBN 0
2492 #define	FRF_BZ_TX_PACE_WIDTH 5
2493 
2494 /* RX_INDIRECTION_TBL: RX Indirection Table */
2495 #define	FR_BZ_RX_INDIRECTION_TBL 0x00fb0000
2496 #define	FR_BZ_RX_INDIRECTION_TBL_STEP 16
2497 #define	FR_BZ_RX_INDIRECTION_TBL_ROWS 128
2498 #define	FRF_BZ_IT_QUEUE_LBN 0
2499 #define	FRF_BZ_IT_QUEUE_WIDTH 6
2500 
2501 /* TX_FILTER_TBL0: TCP/IPv4 Transmit filter table */
2502 #define	FR_CZ_TX_FILTER_TBL0 0x00fc0000
2503 #define	FR_CZ_TX_FILTER_TBL0_STEP 16
2504 #define	FR_CZ_TX_FILTER_TBL0_ROWS 8192
2505 #define	FRF_CZ_TIFT_TCP_UDP_LBN 108
2506 #define	FRF_CZ_TIFT_TCP_UDP_WIDTH 1
2507 #define	FRF_CZ_TIFT_TXQ_ID_LBN 96
2508 #define	FRF_CZ_TIFT_TXQ_ID_WIDTH 12
2509 #define	FRF_CZ_TIFT_DEST_IP_LBN 64
2510 #define	FRF_CZ_TIFT_DEST_IP_WIDTH 32
2511 #define	FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
2512 #define	FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
2513 #define	FRF_CZ_TIFT_SRC_IP_LBN 16
2514 #define	FRF_CZ_TIFT_SRC_IP_WIDTH 32
2515 #define	FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
2516 #define	FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
2517 
2518 /* TX_MAC_FILTER_TBL0: Transmit Ethernet filter table */
2519 #define	FR_CZ_TX_MAC_FILTER_TBL0 0x00fe0000
2520 #define	FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
2521 #define	FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
2522 #define	FRF_CZ_TMFT_TXQ_ID_LBN 61
2523 #define	FRF_CZ_TMFT_TXQ_ID_WIDTH 12
2524 #define	FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
2525 #define	FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
2526 #define	FRF_CZ_TMFT_SRC_MAC_LBN 12
2527 #define	FRF_CZ_TMFT_SRC_MAC_WIDTH 48
2528 #define	FRF_CZ_TMFT_VLAN_ID_LBN 0
2529 #define	FRF_CZ_TMFT_VLAN_ID_WIDTH 12
2530 
2531 /* MC_TREG_SMEM: MC Shared Memory */
2532 #define	FR_CZ_MC_TREG_SMEM 0x00ff0000
2533 #define	FR_CZ_MC_TREG_SMEM_STEP 4
2534 #define	FR_CZ_MC_TREG_SMEM_ROWS 512
2535 #define	FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
2536 #define	FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
2537 
2538 /* MSIX_VECTOR_TABLE: MSIX Vector Table */
2539 #define	FR_BB_MSIX_VECTOR_TABLE 0x00ff0000
2540 #define	FR_BZ_MSIX_VECTOR_TABLE_STEP 16
2541 #define	FR_BB_MSIX_VECTOR_TABLE_ROWS 64
2542 /* MSIX_VECTOR_TABLE: MSIX Vector Table */
2543 #define	FR_CZ_MSIX_VECTOR_TABLE 0x00000000
2544 /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
2545 #define	FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
2546 #define	FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
2547 #define	FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
2548 #define	FRF_BZ_MSIX_VECTOR_MASK_LBN 96
2549 #define	FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
2550 #define	FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
2551 #define	FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
2552 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
2553 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
2554 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
2555 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
2556 
2557 /* MSIX_PBA_TABLE: MSIX Pending Bit Array */
2558 #define	FR_BB_MSIX_PBA_TABLE 0x00ff2000
2559 #define	FR_BZ_MSIX_PBA_TABLE_STEP 4
2560 #define	FR_BB_MSIX_PBA_TABLE_ROWS 2
2561 /* MSIX_PBA_TABLE: MSIX Pending Bit Array */
2562 #define	FR_CZ_MSIX_PBA_TABLE 0x00008000
2563 /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
2564 #define	FR_CZ_MSIX_PBA_TABLE_ROWS 32
2565 #define	FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
2566 #define	FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
2567 
2568 /* SRM_DBG_REG: SRAM debug access */
2569 #define	FR_BZ_SRM_DBG 0x03000000
2570 #define	FR_BZ_SRM_DBG_STEP 8
2571 #define	FR_CZ_SRM_DBG_ROWS 262144
2572 #define	FR_BB_SRM_DBG_ROWS 2097152
2573 #define	FRF_BZ_SRM_DBG_LBN 0
2574 #define	FRF_BZ_SRM_DBG_WIDTH 64
2575 
2576 /* TB_MSIX_PBA_TABLE: MSIX Pending Bit Array */
2577 #define	FR_CZ_TB_MSIX_PBA_TABLE 0x00008000
2578 #define	FR_CZ_TB_MSIX_PBA_TABLE_STEP 4
2579 #define	FR_CZ_TB_MSIX_PBA_TABLE_ROWS 1024
2580 #define	FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 0
2581 #define	FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 32
2582 
2583 /* DRIVER_EV */
2584 #define	FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
2585 #define	FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
2586 #define	FSE_BZ_TX_DSC_ERROR_EV 15
2587 #define	FSE_BZ_RX_DSC_ERROR_EV 14
2588 #define	FSE_AA_RX_RECOVER_EV 11
2589 #define	FSE_AZ_TIMER_EV 10
2590 #define	FSE_AZ_TX_PKT_NON_TCP_UDP 9
2591 #define	FSE_AZ_WAKE_UP_EV 6
2592 #define	FSE_AZ_SRM_UPD_DONE_EV 5
2593 #define	FSE_AB_EVQ_NOT_EN_EV 3
2594 #define	FSE_AZ_EVQ_INIT_DONE_EV 2
2595 #define	FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
2596 #define	FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
2597 #define	FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
2598 #define	FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
2599 
2600 /* EVENT_ENTRY */
2601 #define	FSF_AZ_EV_CODE_LBN 60
2602 #define	FSF_AZ_EV_CODE_WIDTH 4
2603 #define	FSE_CZ_EV_CODE_MCDI_EV 12
2604 #define	FSE_CZ_EV_CODE_USER_EV 8
2605 #define	FSE_AZ_EV_CODE_DRV_GEN_EV 7
2606 #define	FSE_AZ_EV_CODE_GLOBAL_EV 6
2607 #define	FSE_AZ_EV_CODE_DRIVER_EV 5
2608 #define	FSE_AZ_EV_CODE_TX_EV 2
2609 #define	FSE_AZ_EV_CODE_RX_EV 0
2610 #define	FSF_AZ_EV_DATA_LBN 0
2611 #define	FSF_AZ_EV_DATA_WIDTH 60
2612 
2613 /* GLOBAL_EV */
2614 #define	FSF_BB_GLB_EV_RX_RECOVERY_LBN 12
2615 #define	FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 1
2616 #define	FSF_AA_GLB_EV_RX_RECOVERY_LBN 11
2617 #define	FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
2618 #define	FSF_BB_GLB_EV_XG_MGT_INTR_LBN 11
2619 #define	FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 1
2620 #define	FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 10
2621 #define	FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 1
2622 #define	FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 9
2623 #define	FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 1
2624 #define	FSF_AB_GLB_EV_G_PHY0_INTR_LBN 7
2625 #define	FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 1
2626 
2627 /* LEGACY_INT_VEC */
2628 #define	FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
2629 #define	FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
2630 #define	FSF_AZ_NET_IVEC_INT_Q_LBN 40
2631 #define	FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
2632 #define	FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
2633 #define	FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
2634 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
2635 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
2636 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
2637 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
2638 
2639 /* MC_XGMAC_FLTR_RULE_DEF */
2640 #define	FSF_CZ_MC_XFRC_MODE_LBN 416
2641 #define	FSF_CZ_MC_XFRC_MODE_WIDTH 1
2642 #define	FSE_CZ_MC_XFRC_MODE_LAYERED 1
2643 #define	FSE_CZ_MC_XFRC_MODE_SIMPLE 0
2644 #define	FSF_CZ_MC_XFRC_HASH_LBN 384
2645 #define	FSF_CZ_MC_XFRC_HASH_WIDTH 32
2646 #define	FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256
2647 #define	FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128
2648 #define	FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128
2649 #define	FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128
2650 #define	FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0
2651 #define	FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128
2652 
2653 /* RX_EV */
2654 #define	FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
2655 #define	FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
2656 #define	FSF_CZ_RX_EV_IPV6_PKT_LBN 57
2657 #define	FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
2658 #define	FSF_AZ_RX_EV_PKT_OK_LBN 56
2659 #define	FSF_AZ_RX_EV_PKT_OK_WIDTH 1
2660 #define	FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
2661 #define	FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
2662 #define	FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
2663 #define	FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
2664 #define	FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
2665 #define	FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
2666 #define	FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
2667 #define	FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
2668 #define	FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
2669 #define	FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
2670 #define	FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
2671 #define	FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
2672 #define	FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
2673 #define	FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
2674 #define	FSF_AA_RX_EV_DRIB_NIB_LBN 49
2675 #define	FSF_AA_RX_EV_DRIB_NIB_WIDTH 1
2676 #define	FSF_AZ_RX_EV_TOBE_DISC_LBN 47
2677 #define	FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
2678 #define	FSF_AZ_RX_EV_PKT_TYPE_LBN 44
2679 #define	FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
2680 #define	FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
2681 #define	FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
2682 #define	FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
2683 #define	FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
2684 #define	FSE_AZ_RX_EV_PKT_TYPE_LLC 1
2685 #define	FSE_AZ_RX_EV_PKT_TYPE_ETH 0
2686 #define	FSF_AZ_RX_EV_HDR_TYPE_LBN 42
2687 #define	FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
2688 #define	FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
2689 #define	FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 2
2690 #define	FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
2691 #define	FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 1
2692 #define	FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
2693 #define	FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 0
2694 #define	FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
2695 #define	FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
2696 #define	FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
2697 #define	FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
2698 #define	FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
2699 #define	FSF_AZ_RX_EV_MCAST_PKT_LBN 39
2700 #define	FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
2701 #define	FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
2702 #define	FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
2703 #define	FSF_AZ_RX_EV_Q_LABEL_LBN 32
2704 #define	FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
2705 #define	FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
2706 #define	FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
2707 #define	FSF_AZ_RX_EV_PORT_LBN 30
2708 #define	FSF_AZ_RX_EV_PORT_WIDTH 1
2709 #define	FSF_AZ_RX_EV_BYTE_CNT_LBN 16
2710 #define	FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
2711 #define	FSF_AZ_RX_EV_SOP_LBN 15
2712 #define	FSF_AZ_RX_EV_SOP_WIDTH 1
2713 #define	FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
2714 #define	FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
2715 #define	FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
2716 #define	FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
2717 #define	FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
2718 #define	FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
2719 #define	FSF_AZ_RX_EV_DESC_PTR_LBN 0
2720 #define	FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
2721 
2722 /* RX_KER_DESC */
2723 #define	FSF_AZ_RX_KER_BUF_SIZE_LBN 48
2724 #define	FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
2725 #define	FSF_AZ_RX_KER_BUF_REGION_LBN 46
2726 #define	FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
2727 #define	FSF_AZ_RX_KER_BUF_ADDR_LBN 0
2728 #define	FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
2729 
2730 /* RX_USER_DESC */
2731 #define	FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
2732 #define	FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
2733 #define	FSF_AZ_RX_USER_BUF_ID_LBN 0
2734 #define	FSF_AZ_RX_USER_BUF_ID_WIDTH 20
2735 
2736 /* TX_EV */
2737 #define	FSF_AZ_TX_EV_PKT_ERR_LBN 38
2738 #define	FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
2739 #define	FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
2740 #define	FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
2741 #define	FSF_AZ_TX_EV_Q_LABEL_LBN 32
2742 #define	FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
2743 #define	FSF_AZ_TX_EV_PORT_LBN 16
2744 #define	FSF_AZ_TX_EV_PORT_WIDTH 1
2745 #define	FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
2746 #define	FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
2747 #define	FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
2748 #define	FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
2749 #define	FSF_AZ_TX_EV_COMP_LBN 12
2750 #define	FSF_AZ_TX_EV_COMP_WIDTH 1
2751 #define	FSF_AZ_TX_EV_DESC_PTR_LBN 0
2752 #define	FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
2753 
2754 /* TX_KER_DESC */
2755 #define	FSF_AZ_TX_KER_CONT_LBN 62
2756 #define	FSF_AZ_TX_KER_CONT_WIDTH 1
2757 #define	FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
2758 #define	FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
2759 #define	FSF_AZ_TX_KER_BUF_REGION_LBN 46
2760 #define	FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
2761 #define	FSF_AZ_TX_KER_BUF_ADDR_LBN 0
2762 #define	FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
2763 
2764 /* TX_USER_DESC */
2765 #define	FSF_AZ_TX_USER_SW_EV_EN_LBN 48
2766 #define	FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
2767 #define	FSF_AZ_TX_USER_CONT_LBN 46
2768 #define	FSF_AZ_TX_USER_CONT_WIDTH 1
2769 #define	FSF_AZ_TX_USER_BYTE_CNT_LBN 33
2770 #define	FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
2771 #define	FSF_AZ_TX_USER_BUF_ID_LBN 13
2772 #define	FSF_AZ_TX_USER_BUF_ID_WIDTH 20
2773 #define	FSF_AZ_TX_USER_BYTE_OFS_LBN 0
2774 #define	FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
2775 
2776 /* USER_EV */
2777 #define	FSF_CZ_USER_QID_LBN 32
2778 #define	FSF_CZ_USER_QID_WIDTH 10
2779 #define	FSF_CZ_USER_EV_REG_VALUE_LBN 0
2780 #define	FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
2781 
2782 /**************************************************************************
2783  *
2784  * Falcon B0 PCIe core indirect registers
2785  *
2786  **************************************************************************
2787  */
2788 
2789 #define FPCR_BB_PCIE_DEVICE_CTRL_STAT 0x68
2790 
2791 #define FPCR_BB_PCIE_LINK_CTRL_STAT 0x70
2792 
2793 #define FPCR_BB_ACK_RPL_TIMER 0x700
2794 #define FPCRF_BB_ACK_TL_LBN 0
2795 #define FPCRF_BB_ACK_TL_WIDTH 16
2796 #define FPCRF_BB_RPL_TL_LBN 16
2797 #define FPCRF_BB_RPL_TL_WIDTH 16
2798 
2799 #define FPCR_BB_ACK_FREQ 0x70C
2800 #define FPCRF_BB_ACK_FREQ_LBN 0
2801 #define FPCRF_BB_ACK_FREQ_WIDTH 7
2802 
2803 /**************************************************************************
2804  *
2805  * Pseudo-registers and fields
2806  *
2807  **************************************************************************
2808  */
2809 
2810 /* Interrupt acknowledge work-around register (A0/A1 only) */
2811 #define FR_AA_WORK_AROUND_BROKEN_PCI_READS 0x0070
2812 
2813 /* EE_SPI_HCMD_REG: SPI host command register */
2814 /* Values for the EE_SPI_HCMD_SF_SEL register field */
2815 #define FFE_AB_SPI_DEVICE_EEPROM 0
2816 #define FFE_AB_SPI_DEVICE_FLASH 1
2817 
2818 /* NIC_STAT_REG: NIC status register */
2819 #define FRF_AB_STRAP_10G_LBN 2
2820 #define FRF_AB_STRAP_10G_WIDTH 1
2821 #define FRF_AA_STRAP_PCIE_LBN 0
2822 #define FRF_AA_STRAP_PCIE_WIDTH 1
2823 
2824 /* FATAL_INTR_REG_KER: Fatal interrupt register for Kernel */
2825 #define FRF_AZ_FATAL_INTR_LBN 0
2826 #define FRF_AZ_FATAL_INTR_WIDTH 12
2827 
2828 /* SRM_CFG_REG: SRAM configuration register */
2829 /* We treat the number of SRAM banks and bank size as a single field */
2830 #define	FRF_AZ_SRM_NB_SZ_LBN FRF_AZ_SRM_BANK_SIZE_LBN
2831 #define	FRF_AZ_SRM_NB_SZ_WIDTH \
2832 	(FRF_AZ_SRM_BANK_SIZE_WIDTH + FRF_AZ_SRM_NUM_BANK_WIDTH)
2833 #define FFE_AB_SRM_NB1_SZ2M 0
2834 #define FFE_AB_SRM_NB1_SZ4M 1
2835 #define FFE_AB_SRM_NB1_SZ8M 2
2836 #define FFE_AB_SRM_NB_SZ_DEF 3
2837 #define FFE_AB_SRM_NB2_SZ4M 4
2838 #define FFE_AB_SRM_NB2_SZ8M 5
2839 #define FFE_AB_SRM_NB2_SZ16M 6
2840 #define FFE_AB_SRM_NB_SZ_RES 7
2841 
2842 /* RX_DESC_UPD_REGP0: Receive descriptor update register. */
2843 /* We write just the last dword of these registers */
2844 #define	FR_AZ_RX_DESC_UPD_DWORD_P0 \
2845 	(BUILD_BUG_ON_ZERO(FR_AA_RX_DESC_UPD_KER != FR_BZ_RX_DESC_UPD_P0) + \
2846 	 FR_BZ_RX_DESC_UPD_P0 + 3 * 4)
2847 #define	FRF_AZ_RX_DESC_WPTR_DWORD_LBN (FRF_AZ_RX_DESC_WPTR_LBN - 3 * 32)
2848 #define	FRF_AZ_RX_DESC_WPTR_DWORD_WIDTH FRF_AZ_RX_DESC_WPTR_WIDTH
2849 
2850 /* TX_DESC_UPD_REGP0: Transmit descriptor update register. */
2851 #define FR_AZ_TX_DESC_UPD_DWORD_P0 \
2852 	(BUILD_BUG_ON_ZERO(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0) + \
2853 	 FR_BZ_TX_DESC_UPD_P0 + 3 * 4)
2854 #define	FRF_AZ_TX_DESC_WPTR_DWORD_LBN (FRF_AZ_TX_DESC_WPTR_LBN - 3 * 32)
2855 #define	FRF_AZ_TX_DESC_WPTR_DWORD_WIDTH FRF_AZ_TX_DESC_WPTR_WIDTH
2856 
2857 /* GMF_CFG4_REG: GMAC FIFO configuration register 4 */
2858 #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_LBN 12
2859 #define FRF_AB_GMF_HSTFLTRFRM_PAUSE_WIDTH 1
2860 
2861 /* GMF_CFG5_REG: GMAC FIFO configuration register 5 */
2862 #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_LBN 12
2863 #define FRF_AB_GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1
2864 
2865 /* XM_TX_PARAM_REG: XGMAC transmit parameter register */
2866 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_LBN FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN
2867 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH + \
2868 					 FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH)
2869 
2870 /* XM_RX_PARAM_REG: XGMAC receive parameter register */
2871 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_LBN FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN
2872 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_WIDTH (FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH + \
2873 					 FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH)
2874 
2875 /* XX_TXDRV_CTL_REG: XAUI SerDes transmit drive control register */
2876 /* Default values */
2877 #define FFE_AB_XX_TXDRV_DEQ_DEF 0xe /* deq=.6 */
2878 #define FFE_AB_XX_TXDRV_DTX_DEF 0x5 /* 1.25 */
2879 #define FFE_AB_XX_SD_CTL_DRV_DEF 0  /* 20mA */
2880 
2881 /* XX_CORE_STAT_REG: XAUI XGXS core status register */
2882 /* XGXS all-lanes status fields */
2883 #define	FRF_AB_XX_SYNC_STAT_LBN FRF_AB_XX_SYNC_STAT0_LBN
2884 #define	FRF_AB_XX_SYNC_STAT_WIDTH 4
2885 #define	FRF_AB_XX_COMMA_DET_LBN FRF_AB_XX_COMMA_DET_CH0_LBN
2886 #define	FRF_AB_XX_COMMA_DET_WIDTH 4
2887 #define	FRF_AB_XX_CHAR_ERR_LBN FRF_AB_XX_CHAR_ERR_CH0_LBN
2888 #define	FRF_AB_XX_CHAR_ERR_WIDTH 4
2889 #define	FRF_AB_XX_DISPERR_LBN FRF_AB_XX_DISPERR_CH0_LBN
2890 #define	FRF_AB_XX_DISPERR_WIDTH 4
2891 #define	FFE_AB_XX_STAT_ALL_LANES 0xf
2892 #define	FRF_AB_XX_FORCE_SIG_LBN FRF_AB_XX_FORCE_SIG0_VAL_LBN
2893 #define	FRF_AB_XX_FORCE_SIG_WIDTH 8
2894 #define	FFE_AB_XX_FORCE_SIG_ALL_LANES 0xff
2895 
2896 /* RX_MAC_FILTER_TBL0 */
2897 /* RMFT_DEST_MAC is wider than 32 bits */
2898 #define FRF_CZ_RMFT_DEST_MAC_LO_LBN FRF_CZ_RMFT_DEST_MAC_LBN
2899 #define FRF_CZ_RMFT_DEST_MAC_LO_WIDTH 32
2900 #define FRF_CZ_RMFT_DEST_MAC_HI_LBN (FRF_CZ_RMFT_DEST_MAC_LBN + 32)
2901 #define FRF_CZ_RMFT_DEST_MAC_HI_WIDTH (FRF_CZ_RMFT_DEST_MAC_WIDTH - 32)
2902 
2903 /* TX_MAC_FILTER_TBL0 */
2904 /* TMFT_SRC_MAC is wider than 32 bits */
2905 #define FRF_CZ_TMFT_SRC_MAC_LO_LBN FRF_CZ_TMFT_SRC_MAC_LBN
2906 #define FRF_CZ_TMFT_SRC_MAC_LO_WIDTH 32
2907 #define FRF_CZ_TMFT_SRC_MAC_HI_LBN (FRF_CZ_TMFT_SRC_MAC_LBN + 32)
2908 #define FRF_CZ_TMFT_SRC_MAC_HI_WIDTH (FRF_CZ_TMFT_SRC_MAC_WIDTH - 32)
2909 
2910 /* TX_PACE_TBL */
2911 /* Values >20 are documented as reserved, but will result in a queue going
2912  * into the fast bin with a pace value of zero. */
2913 #define FFE_BZ_TX_PACE_OFF 0
2914 #define FFE_BZ_TX_PACE_RESERVED 21
2915 
2916 /* DRIVER_EV */
2917 /* Sub-fields of an RX flush completion event */
2918 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12
2919 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
2920 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0
2921 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12
2922 
2923 /* EVENT_ENTRY */
2924 /* Magic number field for event test */
2925 #define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0
2926 #define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32
2927 
2928 /**************************************************************************
2929  *
2930  * Falcon MAC stats
2931  *
2932  **************************************************************************
2933  *
2934  */
2935 
2936 #define GRxGoodOct_offset 0x0
2937 #define GRxGoodOct_WIDTH 48
2938 #define GRxBadOct_offset 0x8
2939 #define GRxBadOct_WIDTH 48
2940 #define GRxMissPkt_offset 0x10
2941 #define GRxMissPkt_WIDTH 32
2942 #define GRxFalseCRS_offset 0x14
2943 #define GRxFalseCRS_WIDTH 32
2944 #define GRxPausePkt_offset 0x18
2945 #define GRxPausePkt_WIDTH 32
2946 #define GRxBadPkt_offset 0x1C
2947 #define GRxBadPkt_WIDTH 32
2948 #define GRxUcastPkt_offset 0x20
2949 #define GRxUcastPkt_WIDTH 32
2950 #define GRxMcastPkt_offset 0x24
2951 #define GRxMcastPkt_WIDTH 32
2952 #define GRxBcastPkt_offset 0x28
2953 #define GRxBcastPkt_WIDTH 32
2954 #define GRxGoodLt64Pkt_offset 0x2C
2955 #define GRxGoodLt64Pkt_WIDTH 32
2956 #define GRxBadLt64Pkt_offset 0x30
2957 #define GRxBadLt64Pkt_WIDTH 32
2958 #define GRx64Pkt_offset 0x34
2959 #define GRx64Pkt_WIDTH 32
2960 #define GRx65to127Pkt_offset 0x38
2961 #define GRx65to127Pkt_WIDTH 32
2962 #define GRx128to255Pkt_offset 0x3C
2963 #define GRx128to255Pkt_WIDTH 32
2964 #define GRx256to511Pkt_offset 0x40
2965 #define GRx256to511Pkt_WIDTH 32
2966 #define GRx512to1023Pkt_offset 0x44
2967 #define GRx512to1023Pkt_WIDTH 32
2968 #define GRx1024to15xxPkt_offset 0x48
2969 #define GRx1024to15xxPkt_WIDTH 32
2970 #define GRx15xxtoJumboPkt_offset 0x4C
2971 #define GRx15xxtoJumboPkt_WIDTH 32
2972 #define GRxGtJumboPkt_offset 0x50
2973 #define GRxGtJumboPkt_WIDTH 32
2974 #define GRxFcsErr64to15xxPkt_offset 0x54
2975 #define GRxFcsErr64to15xxPkt_WIDTH 32
2976 #define GRxFcsErr15xxtoJumboPkt_offset 0x58
2977 #define GRxFcsErr15xxtoJumboPkt_WIDTH 32
2978 #define GRxFcsErrGtJumboPkt_offset 0x5C
2979 #define GRxFcsErrGtJumboPkt_WIDTH 32
2980 #define GTxGoodBadOct_offset 0x80
2981 #define GTxGoodBadOct_WIDTH 48
2982 #define GTxGoodOct_offset 0x88
2983 #define GTxGoodOct_WIDTH 48
2984 #define GTxSglColPkt_offset 0x90
2985 #define GTxSglColPkt_WIDTH 32
2986 #define GTxMultColPkt_offset 0x94
2987 #define GTxMultColPkt_WIDTH 32
2988 #define GTxExColPkt_offset 0x98
2989 #define GTxExColPkt_WIDTH 32
2990 #define GTxDefPkt_offset 0x9C
2991 #define GTxDefPkt_WIDTH 32
2992 #define GTxLateCol_offset 0xA0
2993 #define GTxLateCol_WIDTH 32
2994 #define GTxExDefPkt_offset 0xA4
2995 #define GTxExDefPkt_WIDTH 32
2996 #define GTxPausePkt_offset 0xA8
2997 #define GTxPausePkt_WIDTH 32
2998 #define GTxBadPkt_offset 0xAC
2999 #define GTxBadPkt_WIDTH 32
3000 #define GTxUcastPkt_offset 0xB0
3001 #define GTxUcastPkt_WIDTH 32
3002 #define GTxMcastPkt_offset 0xB4
3003 #define GTxMcastPkt_WIDTH 32
3004 #define GTxBcastPkt_offset 0xB8
3005 #define GTxBcastPkt_WIDTH 32
3006 #define GTxLt64Pkt_offset 0xBC
3007 #define GTxLt64Pkt_WIDTH 32
3008 #define GTx64Pkt_offset 0xC0
3009 #define GTx64Pkt_WIDTH 32
3010 #define GTx65to127Pkt_offset 0xC4
3011 #define GTx65to127Pkt_WIDTH 32
3012 #define GTx128to255Pkt_offset 0xC8
3013 #define GTx128to255Pkt_WIDTH 32
3014 #define GTx256to511Pkt_offset 0xCC
3015 #define GTx256to511Pkt_WIDTH 32
3016 #define GTx512to1023Pkt_offset 0xD0
3017 #define GTx512to1023Pkt_WIDTH 32
3018 #define GTx1024to15xxPkt_offset 0xD4
3019 #define GTx1024to15xxPkt_WIDTH 32
3020 #define GTx15xxtoJumboPkt_offset 0xD8
3021 #define GTx15xxtoJumboPkt_WIDTH 32
3022 #define GTxGtJumboPkt_offset 0xDC
3023 #define GTxGtJumboPkt_WIDTH 32
3024 #define GTxNonTcpUdpPkt_offset 0xE0
3025 #define GTxNonTcpUdpPkt_WIDTH 16
3026 #define GTxMacSrcErrPkt_offset 0xE4
3027 #define GTxMacSrcErrPkt_WIDTH 16
3028 #define GTxIpSrcErrPkt_offset 0xE8
3029 #define GTxIpSrcErrPkt_WIDTH 16
3030 #define GDmaDone_offset 0xEC
3031 #define GDmaDone_WIDTH 32
3032 
3033 #define XgRxOctets_offset 0x0
3034 #define XgRxOctets_WIDTH 48
3035 #define XgRxOctetsOK_offset 0x8
3036 #define XgRxOctetsOK_WIDTH 48
3037 #define XgRxPkts_offset 0x10
3038 #define XgRxPkts_WIDTH 32
3039 #define XgRxPktsOK_offset 0x14
3040 #define XgRxPktsOK_WIDTH 32
3041 #define XgRxBroadcastPkts_offset 0x18
3042 #define XgRxBroadcastPkts_WIDTH 32
3043 #define XgRxMulticastPkts_offset 0x1C
3044 #define XgRxMulticastPkts_WIDTH 32
3045 #define XgRxUnicastPkts_offset 0x20
3046 #define XgRxUnicastPkts_WIDTH 32
3047 #define XgRxUndersizePkts_offset 0x24
3048 #define XgRxUndersizePkts_WIDTH 32
3049 #define XgRxOversizePkts_offset 0x28
3050 #define XgRxOversizePkts_WIDTH 32
3051 #define XgRxJabberPkts_offset 0x2C
3052 #define XgRxJabberPkts_WIDTH 32
3053 #define XgRxUndersizeFCSerrorPkts_offset 0x30
3054 #define XgRxUndersizeFCSerrorPkts_WIDTH 32
3055 #define XgRxDropEvents_offset 0x34
3056 #define XgRxDropEvents_WIDTH 32
3057 #define XgRxFCSerrorPkts_offset 0x38
3058 #define XgRxFCSerrorPkts_WIDTH 32
3059 #define XgRxAlignError_offset 0x3C
3060 #define XgRxAlignError_WIDTH 32
3061 #define XgRxSymbolError_offset 0x40
3062 #define XgRxSymbolError_WIDTH 32
3063 #define XgRxInternalMACError_offset 0x44
3064 #define XgRxInternalMACError_WIDTH 32
3065 #define XgRxControlPkts_offset 0x48
3066 #define XgRxControlPkts_WIDTH 32
3067 #define XgRxPausePkts_offset 0x4C
3068 #define XgRxPausePkts_WIDTH 32
3069 #define XgRxPkts64Octets_offset 0x50
3070 #define XgRxPkts64Octets_WIDTH 32
3071 #define XgRxPkts65to127Octets_offset 0x54
3072 #define XgRxPkts65to127Octets_WIDTH 32
3073 #define XgRxPkts128to255Octets_offset 0x58
3074 #define XgRxPkts128to255Octets_WIDTH 32
3075 #define XgRxPkts256to511Octets_offset 0x5C
3076 #define XgRxPkts256to511Octets_WIDTH 32
3077 #define XgRxPkts512to1023Octets_offset 0x60
3078 #define XgRxPkts512to1023Octets_WIDTH 32
3079 #define XgRxPkts1024to15xxOctets_offset 0x64
3080 #define XgRxPkts1024to15xxOctets_WIDTH 32
3081 #define XgRxPkts15xxtoMaxOctets_offset 0x68
3082 #define XgRxPkts15xxtoMaxOctets_WIDTH 32
3083 #define XgRxLengthError_offset 0x6C
3084 #define XgRxLengthError_WIDTH 32
3085 #define XgTxPkts_offset 0x80
3086 #define XgTxPkts_WIDTH 32
3087 #define XgTxOctets_offset 0x88
3088 #define XgTxOctets_WIDTH 48
3089 #define XgTxMulticastPkts_offset 0x90
3090 #define XgTxMulticastPkts_WIDTH 32
3091 #define XgTxBroadcastPkts_offset 0x94
3092 #define XgTxBroadcastPkts_WIDTH 32
3093 #define XgTxUnicastPkts_offset 0x98
3094 #define XgTxUnicastPkts_WIDTH 32
3095 #define XgTxControlPkts_offset 0x9C
3096 #define XgTxControlPkts_WIDTH 32
3097 #define XgTxPausePkts_offset 0xA0
3098 #define XgTxPausePkts_WIDTH 32
3099 #define XgTxPkts64Octets_offset 0xA4
3100 #define XgTxPkts64Octets_WIDTH 32
3101 #define XgTxPkts65to127Octets_offset 0xA8
3102 #define XgTxPkts65to127Octets_WIDTH 32
3103 #define XgTxPkts128to255Octets_offset 0xAC
3104 #define XgTxPkts128to255Octets_WIDTH 32
3105 #define XgTxPkts256to511Octets_offset 0xB0
3106 #define XgTxPkts256to511Octets_WIDTH 32
3107 #define XgTxPkts512to1023Octets_offset 0xB4
3108 #define XgTxPkts512to1023Octets_WIDTH 32
3109 #define XgTxPkts1024to15xxOctets_offset 0xB8
3110 #define XgTxPkts1024to15xxOctets_WIDTH 32
3111 #define XgTxPkts1519toMaxOctets_offset 0xBC
3112 #define XgTxPkts1519toMaxOctets_WIDTH 32
3113 #define XgTxUndersizePkts_offset 0xC0
3114 #define XgTxUndersizePkts_WIDTH 32
3115 #define XgTxOversizePkts_offset 0xC4
3116 #define XgTxOversizePkts_WIDTH 32
3117 #define XgTxNonTcpUdpPkt_offset 0xC8
3118 #define XgTxNonTcpUdpPkt_WIDTH 16
3119 #define XgTxMacSrcErrPkt_offset 0xCC
3120 #define XgTxMacSrcErrPkt_WIDTH 16
3121 #define XgTxIpSrcErrPkt_offset 0xD0
3122 #define XgTxIpSrcErrPkt_WIDTH 16
3123 #define XgDmaDone_offset 0xD4
3124 #define XgDmaDone_WIDTH 32
3125 
3126 #define FALCON_STATS_NOT_DONE 0x00000000
3127 #define FALCON_STATS_DONE 0xffffffff
3128 
3129 /**************************************************************************
3130  *
3131  * Falcon non-volatile configuration
3132  *
3133  **************************************************************************
3134  */
3135 
3136 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */
3137 struct falcon_nvconfig_board_v2 {
3138 	__le16 nports;
3139 	u8 port0_phy_addr;
3140 	u8 port0_phy_type;
3141 	u8 port1_phy_addr;
3142 	u8 port1_phy_type;
3143 	__le16 asic_sub_revision;
3144 	__le16 board_revision;
3145 } __packed;
3146 
3147 /* Board configuration v3 extra information */
3148 struct falcon_nvconfig_board_v3 {
3149 	__le32 spi_device_type[2];
3150 } __packed;
3151 
3152 /* Bit numbers for spi_device_type */
3153 #define SPI_DEV_TYPE_SIZE_LBN 0
3154 #define SPI_DEV_TYPE_SIZE_WIDTH 5
3155 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6
3156 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
3157 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8
3158 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
3159 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
3160 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
3161 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
3162 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
3163 #define SPI_DEV_TYPE_FIELD(type, field)					\
3164 	(((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
3165 
3166 #define FALCON_NVCONFIG_OFFSET 0x300
3167 
3168 #define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
3169 struct falcon_nvconfig {
3170 	efx_oword_t ee_vpd_cfg_reg;			/* 0x300 */
3171 	u8 mac_address[2][8];			/* 0x310 */
3172 	efx_oword_t pcie_sd_ctl0123_reg;		/* 0x320 */
3173 	efx_oword_t pcie_sd_ctl45_reg;			/* 0x330 */
3174 	efx_oword_t pcie_pcs_ctl_stat_reg;		/* 0x340 */
3175 	efx_oword_t hw_init_reg;			/* 0x350 */
3176 	efx_oword_t nic_stat_reg;			/* 0x360 */
3177 	efx_oword_t glb_ctl_reg;			/* 0x370 */
3178 	efx_oword_t srm_cfg_reg;			/* 0x380 */
3179 	efx_oword_t spare_reg;				/* 0x390 */
3180 	__le16 board_magic_num;			/* 0x3A0 */
3181 	__le16 board_struct_ver;
3182 	__le16 board_checksum;
3183 	struct falcon_nvconfig_board_v2 board_v2;
3184 	efx_oword_t ee_base_page_reg;			/* 0x3B0 */
3185 	struct falcon_nvconfig_board_v3 board_v3;	/* 0x3C0 */
3186 } __packed;
3187 
3188 #endif /* EFX_REGS_H */
3189