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Searched refs:WRITE_REG_CMD (Results 1 – 15 of 15) sorted by relevance

/linux-3.4.99/drivers/staging/rts_pstor/
Dspi.c83 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); in sf_polling_status()
84 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, SPI_TRANSFER0_START | SPI_POLLING_MODE0); in sf_polling_status()
107 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_enable_write()
108 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); in sf_enable_write()
109 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); in sf_enable_write()
132 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_disable_write()
133 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); in sf_disable_write()
134 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); in sf_disable_write()
149 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_program()
150 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); in sf_program()
[all …]
Dxd.c91 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); in xd_read_id()
92 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_ID); in xd_read_id()
118 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); in xd_assign_phy_addr()
119 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); in xd_assign_phy_addr()
120 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 8)); in xd_assign_phy_addr()
121 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF, (u8)(addr >> 16)); in xd_assign_phy_addr()
122 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, in xd_assign_phy_addr()
127 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); in xd_assign_phy_addr()
128 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)(addr >> 8)); in xd_assign_phy_addr()
129 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 16)); in xd_assign_phy_addr()
[all …]
Dsd.c176 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); in sd_send_cmd_get_rsp()
177 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); in sd_send_cmd_get_rsp()
178 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); in sd_send_cmd_get_rsp()
179 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); in sd_send_cmd_get_rsp()
180 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); in sd_send_cmd_get_rsp()
182 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); in sd_send_cmd_get_rsp()
183 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, in sd_send_cmd_get_rsp()
185 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, in sd_send_cmd_get_rsp()
335 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]); in sd_read_data()
338 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); in sd_read_data()
[all …]
Drtsx_card.c772 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
773 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); in switch_ssc_clock()
774 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in switch_ssc_clock()
775 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth); in switch_ssc_clock()
776 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); in switch_ssc_clock()
777 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in switch_ssc_clock()
779 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in switch_ssc_clock()
780 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET); in switch_ssc_clock()
912 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT); in trans_dma_enable()
914 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24)); in trans_dma_enable()
[all …]
Dms.c63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_tpc()
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); in ms_transfer_tpc()
65 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); in ms_transfer_tpc()
66 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); in ms_transfer_tpc()
68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); in ms_transfer_tpc()
128 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_data()
129 rtsx_add_cmd(chip, WRITE_REG_CMD, in ms_transfer_data()
131 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); in ms_transfer_data()
132 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); in ms_transfer_data()
135 rtsx_add_cmd(chip, WRITE_REG_CMD, in ms_transfer_data()
[all …]
Drtsx_chip.h305 #define WRITE_REG_CMD 1 macro
Drtsx_chip.c2244 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr); in rtsx_write_ppbuf()
2258 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr); in rtsx_write_ppbuf()
/linux-3.4.99/drivers/staging/rts5139/
Dxd.c97 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); in xd_read_id()
98 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, in xd_read_id()
134 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); in xd_assign_phy_addr()
135 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, in xd_assign_phy_addr()
137 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, in xd_assign_phy_addr()
139 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF, in xd_assign_phy_addr()
141 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, in xd_assign_phy_addr()
147 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, in xd_assign_phy_addr()
149 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, in xd_assign_phy_addr()
151 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, in xd_assign_phy_addr()
[all …]
Dsd.c123 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
124 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8) (arg >> 24));
125 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8) (arg >> 16));
126 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8) (arg >> 8));
127 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8) arg);
129 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
130 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
132 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
317 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
321 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
[all …]
Drts51x_card.c116 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); in do_reset_xd_card()
117 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK, in do_reset_xd_card()
119 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0); in do_reset_xd_card()
143 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); in do_reset_sd_card()
144 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK, in do_reset_sd_card()
146 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); in do_reset_sd_card()
170 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0); in do_reset_ms_card()
171 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK, in do_reset_ms_card()
173 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0); in do_reset_ms_card()
496 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in switch_ssc_clock()
[all …]
Dsd_cprm.c105 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
106 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8) (arg >> 24));
107 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8) (arg >> 16));
108 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8) (arg >> 8));
109 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8) arg);
111 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
112 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
114 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER,
481 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
482 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
[all …]
Dms.c69 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_tpc()
70 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); in ms_transfer_tpc()
71 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); in ms_transfer_tpc()
72 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, in ms_transfer_tpc()
75 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, in ms_transfer_tpc()
147 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_data()
148 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, in ms_transfer_data()
150 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, in ms_transfer_data()
152 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); in ms_transfer_data()
153 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, in ms_transfer_data()
[all …]
Drts51x_chip.c123 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO, GPIO_OE, GPIO_OE); in rts51x_reset_chip()
126 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_AUTO_BLINK, in rts51x_reset_chip()
130 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DMA1_CTL, in rts51x_reset_chip()
572 rts51x_add_cmd(chip, WRITE_REG_CMD, addr, mask, data); in rts51x_write_register()
761 rts51x_add_cmd(chip, WRITE_REG_CMD, HS_VSTAIN, 0xFF, val); in rts51x_write_phy_register()
762 rts51x_add_cmd(chip, WRITE_REG_CMD, HS_VCONTROL, 0xFF, addr & 0x0F); in rts51x_write_phy_register()
763 rts51x_add_cmd(chip, WRITE_REG_CMD, HS_VLOADM, 0xFF, 0x00); in rts51x_write_phy_register()
764 rts51x_add_cmd(chip, WRITE_REG_CMD, HS_VLOADM, 0xFF, 0x00); in rts51x_write_phy_register()
765 rts51x_add_cmd(chip, WRITE_REG_CMD, HS_VLOADM, 0xFF, 0x01); in rts51x_write_phy_register()
766 rts51x_add_cmd(chip, WRITE_REG_CMD, HS_VCONTROL, 0xFF, in rts51x_write_phy_register()
[all …]
Dms_mg.c561 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, in mg_set_ICV()
563 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, in mg_set_ICV()
568 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, in mg_set_ICV()
Drts51x_chip.h97 #define WRITE_REG_CMD 1 macro