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Searched refs:VPMClock (Results 1 – 3 of 3) sorted by relevance

/linux-3.4.99/arch/arm/mach-bcmring/csp/chipc/
DchipcHw.c112 pPLLReg = &pChipcHw->VPMClock; in chipcHw_getClockFrequency()
332 …pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_d… in chipcHw_setClockFrequency()
336 pPLLReg = &pChipcHw->VPMClock; in chipcHw_setClockFrequency()
518 …phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_… in vpmPhaseAlignA0()
525 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
530 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
534 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
536 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
560 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
564 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
[all …]
/linux-3.4.99/arch/arm/mach-bcmring/include/mach/csp/
DchipcHw_reg.h37 uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */ member
DchipcHw_inline.h858 pPLLReg = &pChipcHw->VPMClock; in chipcHw_setClock()