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Searched refs:VIASR (Results 1 – 12 of 12) sorted by relevance

/linux-3.4.99/drivers/video/via/
Dviamode.c25 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
26 {VIASR, SR15, 0x02, 0x02},
27 {VIASR, SR16, 0xBF, 0x08},
28 {VIASR, SR17, 0xFF, 0x1F},
29 {VIASR, SR18, 0xFF, 0x4E},
30 {VIASR, SR1A, 0xFB, 0x08},
31 {VIASR, SR1E, 0x0F, 0x01},
32 {VIASR, SR2A, 0xFF, 0x00},
58 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
59 {VIASR, SR15, 0x02, 0x02},
[all …]
Dvia_clock.c59 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in cle266_set_primary_pll_encoded()
60 via_write_reg(VIASR, 0x46, data & 0xFF); in cle266_set_primary_pll_encoded()
61 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF); in cle266_set_primary_pll_encoded()
62 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in cle266_set_primary_pll_encoded()
67 via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ in k800_set_primary_pll_encoded()
68 via_write_reg(VIASR, 0x44, data & 0xFF); in k800_set_primary_pll_encoded()
69 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); in k800_set_primary_pll_encoded()
70 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF); in k800_set_primary_pll_encoded()
71 via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ in k800_set_primary_pll_encoded()
76 via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ in cle266_set_secondary_pll_encoded()
[all …]
Ddvi.c58 sr2a = viafb_read_reg(VIASR, SR2A); in viafb_tmds_trasmitter_identify()
59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
65 sr2a = viafb_read_reg(VIASR, SR2A); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
68 sr1e = viafb_read_reg(VIASR, SR1E); in viafb_tmds_trasmitter_identify()
69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
74 sr1e = viafb_read_reg(VIASR, SR1E); in viafb_tmds_trasmitter_identify()
75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
79 sr3e = viafb_read_reg(VIASR, SR3E); in viafb_tmds_trasmitter_identify()
80 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
[all …]
Dvia_utility.c152 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_set_gamma_table()
165 sr1a = (unsigned int)viafb_read_reg(VIASR, SR1A); in viafb_set_gamma_table()
166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
194 viafb_write_reg(SR1A, VIASR, sr1a); in viafb_set_gamma_table()
207 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_get_gamma_table()
220 sr1a = viafb_read_reg(VIASR, SR1A); in viafb_get_gamma_table()
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
233 viafb_write_reg(SR1A, VIASR, sr1a); in viafb_get_gamma_table()
Dvia-gpio.c30 .vg_io_port = VIASR,
36 .vg_io_port = VIASR,
42 .vg_io_port = VIASR,
48 .vg_io_port = VIASR,
54 .vg_io_port = VIASR,
60 .vg_io_port = VIASR,
95 reg = via_read_reg(VIASR, gpio->vg_port_index); in via_gpio_set()
101 via_write_reg(VIASR, gpio->vg_port_index, reg); in via_gpio_set()
126 via_write_reg_mask(VIASR, gpio->vg_port_index, 0, in via_gpio_dir_input()
143 reg = via_read_reg(VIASR, gpio->vg_port_index); in via_gpio_get()
[all …]
Dhw.c683 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); in viafb_set_primary_color_register()
689 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); in viafb_set_secondary_color_register()
728 via_write_reg_mask(VIASR, 0x16, value, 0x40); in set_crt_source()
818 via_write_reg_mask(VIASR, 0x1E, value, 0xC0); in set_dvp0_state()
836 via_write_reg_mask(VIASR, 0x1E, value, 0x30); in set_dvp1_state()
854 via_write_reg_mask(VIASR, 0x2A, value, 0x03); in set_lvds1_state()
872 via_write_reg_mask(VIASR, 0x2A, value, 0x0C); in set_lvds2_state()
975 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
1010 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); in viafb_load_reg()
1039 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); in viafb_load_fetch_count_reg()
[all …]
Dvia-core.c26 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
27 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
28 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
29 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c },
30 [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
39 [VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
40 [VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
41 [VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
42 [VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x2c },
43 [VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
Dviafbdev.c1127 (viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 | in viafb_dvp0_proc_show()
1128 (viafb_read_reg(VIASR, SR1B) & BIT1) >> 1; in viafb_dvp0_proc_show()
1130 (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 | in viafb_dvp0_proc_show()
1131 (viafb_read_reg(VIASR, SR1E) & BIT2) >> 2; in viafb_dvp0_proc_show()
1168 viafb_write_reg_mask(SR2A, VIASR, in viafb_dvp0_proc_write()
1170 viafb_write_reg_mask(SR1B, VIASR, in viafb_dvp0_proc_write()
1174 viafb_write_reg_mask(SR2A, VIASR, in viafb_dvp0_proc_write()
1176 viafb_write_reg_mask(SR1E, VIASR, in viafb_dvp0_proc_write()
1202 dvp1_data_dri = (viafb_read_reg(VIASR, SR65) & 0x0c) >> 2; in viafb_dvp1_proc_show()
1203 dvp1_clk_dri = viafb_read_reg(VIASR, SR65) & 0x03; in viafb_dvp1_proc_show()
[all …]
Dlcd.c720 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30); in viafb_lcd_disable()
741 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20); in viafb_lcd_disable()
784 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30); in viafb_lcd_enable()
806 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20); in viafb_lcd_enable()
Dvia_modesetting.c202 via_write_reg_mask(VIASR, 0x15, value, 0x1C); in via_set_primary_color_depth()
/linux-3.4.99/include/linux/
Dvia-core.h201 #define VIASR 0x3C4 macro
/linux-3.4.99/drivers/media/video/
Dvia-camera.c1268 via_write_reg_mask(VIASR, 0x78, 0, 0x80); in viacam_resume()
1269 via_write_reg_mask(VIASR, 0x1e, 0xc0, 0xc0); in viacam_resume()
1421 via_write_reg_mask(VIASR, 0x78, 0, 0x80); in viacam_probe()
1422 via_write_reg_mask(VIASR, 0x1e, 0xc0, 0xc0); in viacam_probe()