1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
106 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
107 #define UCR2_RXEN (1<<1) /* Receiver enabled */
108 #define UCR2_SRST (1<<0) /* SW reset */
109 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
110 #define UCR3_PARERREN (1<<12) /* Parity enable */
111 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
112 #define UCR3_DSR (1<<10) /* Data set ready */
113 #define UCR3_DCD (1<<9) /* Data carrier detect */
114 #define UCR3_RI (1<<8) /* Ring indicator */
115 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
116 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
117 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
118 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
119 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
123 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
124 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
125 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
126 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
127 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS (1<<14) /* RTS pin status */
140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD (1<<12) /* RTS delta */
142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
146 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
147 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
148 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
149 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
150 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
151 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
152 #define USR2_IDLE (1<<12) /* Idle condition */
153 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
154 #define USR2_WAKE (1<<7) /* Wake */
155 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
156 #define USR2_TXDC (1<<3) /* Transmitter complete */
157 #define USR2_BRCD (1<<2) /* Break condition */
158 #define USR2_ORE (1<<1) /* Overrun error */
159 #define USR2_RDR (1<<0) /* Recv data ready */
160 #define UTS_FRCPERR (1<<13) /* Force parity error */
161 #define UTS_LOOP (1<<12) /* Loop tx and rx */
162 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
163 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
164 #define UTS_TXFULL (1<<4) /* TxFIFO full */
165 #define UTS_RXFULL (1<<3) /* RxFIFO full */
166 #define UTS_SOFTRST (1<<0) /* Software reset */
167
168 /* We've been assigned a range on the "Low-density serial ports" major */
169 #define SERIAL_IMX_MAJOR 207
170 #define MINOR_START 16
171 #define DEV_NAME "ttymxc"
172 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
173
174 /*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180 #define MCTRL_TIMEOUT (250*HZ/1000)
181
182 #define DRIVER_NAME "IMX-uart"
183
184 #define UART_NR 8
185
186 /* i.mx21 type uart runs on all i.mx except i.mx1 */
187 enum imx_uart_type {
188 IMX1_UART,
189 IMX21_UART,
190 };
191
192 /* device type dependent stuff */
193 struct imx_uart_data {
194 unsigned uts_reg;
195 enum imx_uart_type devtype;
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 int txirq,rxirq,rtsirq;
203 unsigned int have_rtscts:1;
204 unsigned int use_irda:1;
205 unsigned int irda_inv_rx:1;
206 unsigned int irda_inv_tx:1;
207 unsigned short trcv_delay; /* transceiver delay */
208 struct clk *clk;
209 struct imx_uart_data *devdata;
210 };
211
212 struct imx_port_ucrs {
213 unsigned int ucr1;
214 unsigned int ucr2;
215 unsigned int ucr3;
216 };
217
218 #ifdef CONFIG_IRDA
219 #define USE_IRDA(sport) ((sport)->use_irda)
220 #else
221 #define USE_IRDA(sport) (0)
222 #endif
223
224 static struct imx_uart_data imx_uart_devdata[] = {
225 [IMX1_UART] = {
226 .uts_reg = IMX1_UTS,
227 .devtype = IMX1_UART,
228 },
229 [IMX21_UART] = {
230 .uts_reg = IMX21_UTS,
231 .devtype = IMX21_UART,
232 },
233 };
234
235 static struct platform_device_id imx_uart_devtype[] = {
236 {
237 .name = "imx1-uart",
238 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
239 }, {
240 .name = "imx21-uart",
241 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
242 }, {
243 /* sentinel */
244 }
245 };
246 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
247
248 static struct of_device_id imx_uart_dt_ids[] = {
249 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
250 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
251 { /* sentinel */ }
252 };
253 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
254
uts_reg(struct imx_port * sport)255 static inline unsigned uts_reg(struct imx_port *sport)
256 {
257 return sport->devdata->uts_reg;
258 }
259
is_imx1_uart(struct imx_port * sport)260 static inline int is_imx1_uart(struct imx_port *sport)
261 {
262 return sport->devdata->devtype == IMX1_UART;
263 }
264
is_imx21_uart(struct imx_port * sport)265 static inline int is_imx21_uart(struct imx_port *sport)
266 {
267 return sport->devdata->devtype == IMX21_UART;
268 }
269
270 /*
271 * Save and restore functions for UCR1, UCR2 and UCR3 registers
272 */
imx_port_ucrs_save(struct uart_port * port,struct imx_port_ucrs * ucr)273 static void imx_port_ucrs_save(struct uart_port *port,
274 struct imx_port_ucrs *ucr)
275 {
276 /* save control registers */
277 ucr->ucr1 = readl(port->membase + UCR1);
278 ucr->ucr2 = readl(port->membase + UCR2);
279 ucr->ucr3 = readl(port->membase + UCR3);
280 }
281
imx_port_ucrs_restore(struct uart_port * port,struct imx_port_ucrs * ucr)282 static void imx_port_ucrs_restore(struct uart_port *port,
283 struct imx_port_ucrs *ucr)
284 {
285 /* restore control registers */
286 writel(ucr->ucr1, port->membase + UCR1);
287 writel(ucr->ucr2, port->membase + UCR2);
288 writel(ucr->ucr3, port->membase + UCR3);
289 }
290
291 /*
292 * Handle any change of modem status signal since we were last called.
293 */
imx_mctrl_check(struct imx_port * sport)294 static void imx_mctrl_check(struct imx_port *sport)
295 {
296 unsigned int status, changed;
297
298 status = sport->port.ops->get_mctrl(&sport->port);
299 changed = status ^ sport->old_status;
300
301 if (changed == 0)
302 return;
303
304 sport->old_status = status;
305
306 if (changed & TIOCM_RI)
307 sport->port.icount.rng++;
308 if (changed & TIOCM_DSR)
309 sport->port.icount.dsr++;
310 if (changed & TIOCM_CAR)
311 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
312 if (changed & TIOCM_CTS)
313 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
314
315 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
316 }
317
318 /*
319 * This is our per-port timeout handler, for checking the
320 * modem status signals.
321 */
imx_timeout(unsigned long data)322 static void imx_timeout(unsigned long data)
323 {
324 struct imx_port *sport = (struct imx_port *)data;
325 unsigned long flags;
326
327 if (sport->port.state) {
328 spin_lock_irqsave(&sport->port.lock, flags);
329 imx_mctrl_check(sport);
330 spin_unlock_irqrestore(&sport->port.lock, flags);
331
332 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
333 }
334 }
335
336 /*
337 * interrupts disabled on entry
338 */
imx_stop_tx(struct uart_port * port)339 static void imx_stop_tx(struct uart_port *port)
340 {
341 struct imx_port *sport = (struct imx_port *)port;
342 unsigned long temp;
343
344 if (USE_IRDA(sport)) {
345 /* half duplex - wait for end of transmission */
346 int n = 256;
347 while ((--n > 0) &&
348 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
349 udelay(5);
350 barrier();
351 }
352 /*
353 * irda transceiver - wait a bit more to avoid
354 * cutoff, hardware dependent
355 */
356 udelay(sport->trcv_delay);
357
358 /*
359 * half duplex - reactivate receive mode,
360 * flush receive pipe echo crap
361 */
362 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
363 temp = readl(sport->port.membase + UCR1);
364 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
365 writel(temp, sport->port.membase + UCR1);
366
367 temp = readl(sport->port.membase + UCR4);
368 temp &= ~(UCR4_TCEN);
369 writel(temp, sport->port.membase + UCR4);
370
371 while (readl(sport->port.membase + URXD0) &
372 URXD_CHARRDY)
373 barrier();
374
375 temp = readl(sport->port.membase + UCR1);
376 temp |= UCR1_RRDYEN;
377 writel(temp, sport->port.membase + UCR1);
378
379 temp = readl(sport->port.membase + UCR4);
380 temp |= UCR4_DREN;
381 writel(temp, sport->port.membase + UCR4);
382 }
383 return;
384 }
385
386 temp = readl(sport->port.membase + UCR1);
387 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
388 }
389
390 /*
391 * interrupts disabled on entry
392 */
imx_stop_rx(struct uart_port * port)393 static void imx_stop_rx(struct uart_port *port)
394 {
395 struct imx_port *sport = (struct imx_port *)port;
396 unsigned long temp;
397
398 temp = readl(sport->port.membase + UCR2);
399 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
400 }
401
402 /*
403 * Set the modem control timer to fire immediately.
404 */
imx_enable_ms(struct uart_port * port)405 static void imx_enable_ms(struct uart_port *port)
406 {
407 struct imx_port *sport = (struct imx_port *)port;
408
409 mod_timer(&sport->timer, jiffies);
410 }
411
imx_transmit_buffer(struct imx_port * sport)412 static inline void imx_transmit_buffer(struct imx_port *sport)
413 {
414 struct circ_buf *xmit = &sport->port.state->xmit;
415
416 while (!uart_circ_empty(xmit) &&
417 !(readl(sport->port.membase + uts_reg(sport))
418 & UTS_TXFULL)) {
419 /* send xmit->buf[xmit->tail]
420 * out the port here */
421 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
422 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
423 sport->port.icount.tx++;
424 }
425
426 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
427 uart_write_wakeup(&sport->port);
428
429 if (uart_circ_empty(xmit))
430 imx_stop_tx(&sport->port);
431 }
432
433 /*
434 * interrupts disabled on entry
435 */
imx_start_tx(struct uart_port * port)436 static void imx_start_tx(struct uart_port *port)
437 {
438 struct imx_port *sport = (struct imx_port *)port;
439 unsigned long temp;
440
441 if (USE_IRDA(sport)) {
442 /* half duplex in IrDA mode; have to disable receive mode */
443 temp = readl(sport->port.membase + UCR4);
444 temp &= ~(UCR4_DREN);
445 writel(temp, sport->port.membase + UCR4);
446
447 temp = readl(sport->port.membase + UCR1);
448 temp &= ~(UCR1_RRDYEN);
449 writel(temp, sport->port.membase + UCR1);
450 }
451
452 temp = readl(sport->port.membase + UCR1);
453 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
454
455 if (USE_IRDA(sport)) {
456 temp = readl(sport->port.membase + UCR1);
457 temp |= UCR1_TRDYEN;
458 writel(temp, sport->port.membase + UCR1);
459
460 temp = readl(sport->port.membase + UCR4);
461 temp |= UCR4_TCEN;
462 writel(temp, sport->port.membase + UCR4);
463 }
464
465 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
466 imx_transmit_buffer(sport);
467 }
468
imx_rtsint(int irq,void * dev_id)469 static irqreturn_t imx_rtsint(int irq, void *dev_id)
470 {
471 struct imx_port *sport = dev_id;
472 unsigned int val;
473 unsigned long flags;
474
475 spin_lock_irqsave(&sport->port.lock, flags);
476
477 writel(USR1_RTSD, sport->port.membase + USR1);
478 val = readl(sport->port.membase + USR1) & USR1_RTSS;
479 uart_handle_cts_change(&sport->port, !!val);
480 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
481
482 spin_unlock_irqrestore(&sport->port.lock, flags);
483 return IRQ_HANDLED;
484 }
485
imx_txint(int irq,void * dev_id)486 static irqreturn_t imx_txint(int irq, void *dev_id)
487 {
488 struct imx_port *sport = dev_id;
489 struct circ_buf *xmit = &sport->port.state->xmit;
490 unsigned long flags;
491
492 spin_lock_irqsave(&sport->port.lock,flags);
493 if (sport->port.x_char)
494 {
495 /* Send next char */
496 writel(sport->port.x_char, sport->port.membase + URTX0);
497 goto out;
498 }
499
500 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
501 imx_stop_tx(&sport->port);
502 goto out;
503 }
504
505 imx_transmit_buffer(sport);
506
507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
508 uart_write_wakeup(&sport->port);
509
510 out:
511 spin_unlock_irqrestore(&sport->port.lock,flags);
512 return IRQ_HANDLED;
513 }
514
imx_rxint(int irq,void * dev_id)515 static irqreturn_t imx_rxint(int irq, void *dev_id)
516 {
517 struct imx_port *sport = dev_id;
518 unsigned int rx,flg,ignored = 0;
519 struct tty_struct *tty = sport->port.state->port.tty;
520 unsigned long flags, temp;
521
522 spin_lock_irqsave(&sport->port.lock,flags);
523
524 while (readl(sport->port.membase + USR2) & USR2_RDR) {
525 flg = TTY_NORMAL;
526 sport->port.icount.rx++;
527
528 rx = readl(sport->port.membase + URXD0);
529
530 temp = readl(sport->port.membase + USR2);
531 if (temp & USR2_BRCD) {
532 writel(USR2_BRCD, sport->port.membase + USR2);
533 if (uart_handle_break(&sport->port))
534 continue;
535 }
536
537 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
538 continue;
539
540 if (unlikely(rx & URXD_ERR)) {
541 if (rx & URXD_BRK)
542 sport->port.icount.brk++;
543 else if (rx & URXD_PRERR)
544 sport->port.icount.parity++;
545 else if (rx & URXD_FRMERR)
546 sport->port.icount.frame++;
547 if (rx & URXD_OVRRUN)
548 sport->port.icount.overrun++;
549
550 if (rx & sport->port.ignore_status_mask) {
551 if (++ignored > 100)
552 goto out;
553 continue;
554 }
555
556 rx &= sport->port.read_status_mask;
557
558 if (rx & URXD_BRK)
559 flg = TTY_BREAK;
560 else if (rx & URXD_PRERR)
561 flg = TTY_PARITY;
562 else if (rx & URXD_FRMERR)
563 flg = TTY_FRAME;
564 if (rx & URXD_OVRRUN)
565 flg = TTY_OVERRUN;
566
567 #ifdef SUPPORT_SYSRQ
568 sport->port.sysrq = 0;
569 #endif
570 }
571
572 tty_insert_flip_char(tty, rx, flg);
573 }
574
575 out:
576 spin_unlock_irqrestore(&sport->port.lock,flags);
577 tty_flip_buffer_push(tty);
578 return IRQ_HANDLED;
579 }
580
imx_int(int irq,void * dev_id)581 static irqreturn_t imx_int(int irq, void *dev_id)
582 {
583 struct imx_port *sport = dev_id;
584 unsigned int sts;
585
586 sts = readl(sport->port.membase + USR1);
587
588 if (sts & USR1_RRDY)
589 imx_rxint(irq, dev_id);
590
591 if (sts & USR1_TRDY &&
592 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
593 imx_txint(irq, dev_id);
594
595 if (sts & USR1_RTSD)
596 imx_rtsint(irq, dev_id);
597
598 if (sts & USR1_AWAKE)
599 writel(USR1_AWAKE, sport->port.membase + USR1);
600
601 return IRQ_HANDLED;
602 }
603
604 /*
605 * Return TIOCSER_TEMT when transmitter is not busy.
606 */
imx_tx_empty(struct uart_port * port)607 static unsigned int imx_tx_empty(struct uart_port *port)
608 {
609 struct imx_port *sport = (struct imx_port *)port;
610
611 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
612 }
613
614 /*
615 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
616 */
imx_get_mctrl(struct uart_port * port)617 static unsigned int imx_get_mctrl(struct uart_port *port)
618 {
619 struct imx_port *sport = (struct imx_port *)port;
620 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
621
622 if (readl(sport->port.membase + USR1) & USR1_RTSS)
623 tmp |= TIOCM_CTS;
624
625 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
626 tmp |= TIOCM_RTS;
627
628 return tmp;
629 }
630
imx_set_mctrl(struct uart_port * port,unsigned int mctrl)631 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
632 {
633 struct imx_port *sport = (struct imx_port *)port;
634 unsigned long temp;
635
636 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
637
638 if (mctrl & TIOCM_RTS)
639 temp |= UCR2_CTS;
640
641 writel(temp, sport->port.membase + UCR2);
642 }
643
644 /*
645 * Interrupts always disabled.
646 */
imx_break_ctl(struct uart_port * port,int break_state)647 static void imx_break_ctl(struct uart_port *port, int break_state)
648 {
649 struct imx_port *sport = (struct imx_port *)port;
650 unsigned long flags, temp;
651
652 spin_lock_irqsave(&sport->port.lock, flags);
653
654 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
655
656 if ( break_state != 0 )
657 temp |= UCR1_SNDBRK;
658
659 writel(temp, sport->port.membase + UCR1);
660
661 spin_unlock_irqrestore(&sport->port.lock, flags);
662 }
663
664 #define TXTL 2 /* reset default */
665 #define RXTL 1 /* reset default */
666
imx_setup_ufcr(struct imx_port * sport,unsigned int mode)667 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
668 {
669 unsigned int val;
670
671 /* set receiver / transmitter trigger level */
672 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
673 val |= TXTL << UFCR_TXTL_SHF | RXTL;
674 writel(val, sport->port.membase + UFCR);
675 return 0;
676 }
677
678 /* half the RX buffer size */
679 #define CTSTL 16
680
imx_startup(struct uart_port * port)681 static int imx_startup(struct uart_port *port)
682 {
683 struct imx_port *sport = (struct imx_port *)port;
684 int retval;
685 unsigned long flags, temp;
686
687 imx_setup_ufcr(sport, 0);
688
689 /* disable the DREN bit (Data Ready interrupt enable) before
690 * requesting IRQs
691 */
692 temp = readl(sport->port.membase + UCR4);
693
694 if (USE_IRDA(sport))
695 temp |= UCR4_IRSC;
696
697 /* set the trigger level for CTS */
698 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
699 temp |= CTSTL<< UCR4_CTSTL_SHF;
700
701 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
702
703 if (USE_IRDA(sport)) {
704 /* reset fifo's and state machines */
705 int i = 100;
706 temp = readl(sport->port.membase + UCR2);
707 temp &= ~UCR2_SRST;
708 writel(temp, sport->port.membase + UCR2);
709 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
710 (--i > 0)) {
711 udelay(1);
712 }
713 }
714
715 /*
716 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
717 * chips only have one interrupt.
718 */
719 if (sport->txirq > 0) {
720 retval = request_irq(sport->rxirq, imx_rxint, 0,
721 DRIVER_NAME, sport);
722 if (retval)
723 goto error_out1;
724
725 retval = request_irq(sport->txirq, imx_txint, 0,
726 DRIVER_NAME, sport);
727 if (retval)
728 goto error_out2;
729
730 /* do not use RTS IRQ on IrDA */
731 if (!USE_IRDA(sport)) {
732 retval = request_irq(sport->rtsirq, imx_rtsint,
733 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
734 IRQF_TRIGGER_FALLING |
735 IRQF_TRIGGER_RISING,
736 DRIVER_NAME, sport);
737 if (retval)
738 goto error_out3;
739 }
740 } else {
741 retval = request_irq(sport->port.irq, imx_int, 0,
742 DRIVER_NAME, sport);
743 if (retval) {
744 free_irq(sport->port.irq, sport);
745 goto error_out1;
746 }
747 }
748
749 spin_lock_irqsave(&sport->port.lock, flags);
750 /*
751 * Finally, clear and enable interrupts
752 */
753 writel(USR1_RTSD, sport->port.membase + USR1);
754
755 temp = readl(sport->port.membase + UCR1);
756 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
757
758 if (USE_IRDA(sport)) {
759 temp |= UCR1_IREN;
760 temp &= ~(UCR1_RTSDEN);
761 }
762
763 writel(temp, sport->port.membase + UCR1);
764
765 temp = readl(sport->port.membase + UCR2);
766 temp |= (UCR2_RXEN | UCR2_TXEN);
767 writel(temp, sport->port.membase + UCR2);
768
769 if (USE_IRDA(sport)) {
770 /* clear RX-FIFO */
771 int i = 64;
772 while ((--i > 0) &&
773 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
774 barrier();
775 }
776 }
777
778 if (is_imx21_uart(sport)) {
779 temp = readl(sport->port.membase + UCR3);
780 temp |= IMX21_UCR3_RXDMUXSEL;
781 writel(temp, sport->port.membase + UCR3);
782 }
783
784 if (USE_IRDA(sport)) {
785 temp = readl(sport->port.membase + UCR4);
786 if (sport->irda_inv_rx)
787 temp |= UCR4_INVR;
788 else
789 temp &= ~(UCR4_INVR);
790 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
791
792 temp = readl(sport->port.membase + UCR3);
793 if (sport->irda_inv_tx)
794 temp |= UCR3_INVT;
795 else
796 temp &= ~(UCR3_INVT);
797 writel(temp, sport->port.membase + UCR3);
798 }
799
800 /*
801 * Enable modem status interrupts
802 */
803 imx_enable_ms(&sport->port);
804 spin_unlock_irqrestore(&sport->port.lock,flags);
805
806 if (USE_IRDA(sport)) {
807 struct imxuart_platform_data *pdata;
808 pdata = sport->port.dev->platform_data;
809 sport->irda_inv_rx = pdata->irda_inv_rx;
810 sport->irda_inv_tx = pdata->irda_inv_tx;
811 sport->trcv_delay = pdata->transceiver_delay;
812 if (pdata->irda_enable)
813 pdata->irda_enable(1);
814 }
815
816 return 0;
817
818 error_out3:
819 if (sport->txirq)
820 free_irq(sport->txirq, sport);
821 error_out2:
822 if (sport->rxirq)
823 free_irq(sport->rxirq, sport);
824 error_out1:
825 return retval;
826 }
827
imx_shutdown(struct uart_port * port)828 static void imx_shutdown(struct uart_port *port)
829 {
830 struct imx_port *sport = (struct imx_port *)port;
831 unsigned long temp;
832 unsigned long flags;
833
834 spin_lock_irqsave(&sport->port.lock, flags);
835 temp = readl(sport->port.membase + UCR2);
836 temp &= ~(UCR2_TXEN);
837 writel(temp, sport->port.membase + UCR2);
838 spin_unlock_irqrestore(&sport->port.lock, flags);
839
840 if (USE_IRDA(sport)) {
841 struct imxuart_platform_data *pdata;
842 pdata = sport->port.dev->platform_data;
843 if (pdata->irda_enable)
844 pdata->irda_enable(0);
845 }
846
847 /*
848 * Stop our timer.
849 */
850 del_timer_sync(&sport->timer);
851
852 /*
853 * Free the interrupts
854 */
855 if (sport->txirq > 0) {
856 if (!USE_IRDA(sport))
857 free_irq(sport->rtsirq, sport);
858 free_irq(sport->txirq, sport);
859 free_irq(sport->rxirq, sport);
860 } else
861 free_irq(sport->port.irq, sport);
862
863 /*
864 * Disable all interrupts, port and break condition.
865 */
866
867 spin_lock_irqsave(&sport->port.lock, flags);
868 temp = readl(sport->port.membase + UCR1);
869 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
870 if (USE_IRDA(sport))
871 temp &= ~(UCR1_IREN);
872
873 writel(temp, sport->port.membase + UCR1);
874 spin_unlock_irqrestore(&sport->port.lock, flags);
875 }
876
877 static void
imx_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)878 imx_set_termios(struct uart_port *port, struct ktermios *termios,
879 struct ktermios *old)
880 {
881 struct imx_port *sport = (struct imx_port *)port;
882 unsigned long flags;
883 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
884 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
885 unsigned int div, ufcr;
886 unsigned long num, denom;
887 uint64_t tdiv64;
888
889 /*
890 * If we don't support modem control lines, don't allow
891 * these to be set.
892 */
893 if (0) {
894 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
895 termios->c_cflag |= CLOCAL;
896 }
897
898 /*
899 * We only support CS7 and CS8.
900 */
901 while ((termios->c_cflag & CSIZE) != CS7 &&
902 (termios->c_cflag & CSIZE) != CS8) {
903 termios->c_cflag &= ~CSIZE;
904 termios->c_cflag |= old_csize;
905 old_csize = CS8;
906 }
907
908 if ((termios->c_cflag & CSIZE) == CS8)
909 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
910 else
911 ucr2 = UCR2_SRST | UCR2_IRTS;
912
913 if (termios->c_cflag & CRTSCTS) {
914 if( sport->have_rtscts ) {
915 ucr2 &= ~UCR2_IRTS;
916 ucr2 |= UCR2_CTSC;
917 } else {
918 termios->c_cflag &= ~CRTSCTS;
919 }
920 }
921
922 if (termios->c_cflag & CSTOPB)
923 ucr2 |= UCR2_STPB;
924 if (termios->c_cflag & PARENB) {
925 ucr2 |= UCR2_PREN;
926 if (termios->c_cflag & PARODD)
927 ucr2 |= UCR2_PROE;
928 }
929
930 del_timer_sync(&sport->timer);
931
932 /*
933 * Ask the core to calculate the divisor for us.
934 */
935 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
936 quot = uart_get_divisor(port, baud);
937
938 spin_lock_irqsave(&sport->port.lock, flags);
939
940 sport->port.read_status_mask = 0;
941 if (termios->c_iflag & INPCK)
942 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
943 if (termios->c_iflag & (BRKINT | PARMRK))
944 sport->port.read_status_mask |= URXD_BRK;
945
946 /*
947 * Characters to ignore
948 */
949 sport->port.ignore_status_mask = 0;
950 if (termios->c_iflag & IGNPAR)
951 sport->port.ignore_status_mask |= URXD_PRERR;
952 if (termios->c_iflag & IGNBRK) {
953 sport->port.ignore_status_mask |= URXD_BRK;
954 /*
955 * If we're ignoring parity and break indicators,
956 * ignore overruns too (for real raw support).
957 */
958 if (termios->c_iflag & IGNPAR)
959 sport->port.ignore_status_mask |= URXD_OVRRUN;
960 }
961
962 /*
963 * Update the per-port timeout.
964 */
965 uart_update_timeout(port, termios->c_cflag, baud);
966
967 /*
968 * disable interrupts and drain transmitter
969 */
970 old_ucr1 = readl(sport->port.membase + UCR1);
971 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
972 sport->port.membase + UCR1);
973
974 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
975 barrier();
976
977 /* then, disable everything */
978 old_txrxen = readl(sport->port.membase + UCR2);
979 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
980 sport->port.membase + UCR2);
981 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
982
983 if (USE_IRDA(sport)) {
984 /*
985 * use maximum available submodule frequency to
986 * avoid missing short pulses due to low sampling rate
987 */
988 div = 1;
989 } else {
990 div = sport->port.uartclk / (baud * 16);
991 if (div > 7)
992 div = 7;
993 if (!div)
994 div = 1;
995 }
996
997 rational_best_approximation(16 * div * baud, sport->port.uartclk,
998 1 << 16, 1 << 16, &num, &denom);
999
1000 tdiv64 = sport->port.uartclk;
1001 tdiv64 *= num;
1002 do_div(tdiv64, denom * 16 * div);
1003 tty_termios_encode_baud_rate(termios,
1004 (speed_t)tdiv64, (speed_t)tdiv64);
1005
1006 num -= 1;
1007 denom -= 1;
1008
1009 ufcr = readl(sport->port.membase + UFCR);
1010 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1011 writel(ufcr, sport->port.membase + UFCR);
1012
1013 writel(num, sport->port.membase + UBIR);
1014 writel(denom, sport->port.membase + UBMR);
1015
1016 if (is_imx21_uart(sport))
1017 writel(sport->port.uartclk / div / 1000,
1018 sport->port.membase + IMX21_ONEMS);
1019
1020 writel(old_ucr1, sport->port.membase + UCR1);
1021
1022 /* set the parity, stop bits and data size */
1023 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1024
1025 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1026 imx_enable_ms(&sport->port);
1027
1028 spin_unlock_irqrestore(&sport->port.lock, flags);
1029 }
1030
imx_type(struct uart_port * port)1031 static const char *imx_type(struct uart_port *port)
1032 {
1033 struct imx_port *sport = (struct imx_port *)port;
1034
1035 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1036 }
1037
1038 /*
1039 * Release the memory region(s) being used by 'port'.
1040 */
imx_release_port(struct uart_port * port)1041 static void imx_release_port(struct uart_port *port)
1042 {
1043 struct platform_device *pdev = to_platform_device(port->dev);
1044 struct resource *mmres;
1045
1046 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1047 release_mem_region(mmres->start, resource_size(mmres));
1048 }
1049
1050 /*
1051 * Request the memory region(s) being used by 'port'.
1052 */
imx_request_port(struct uart_port * port)1053 static int imx_request_port(struct uart_port *port)
1054 {
1055 struct platform_device *pdev = to_platform_device(port->dev);
1056 struct resource *mmres;
1057 void *ret;
1058
1059 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1060 if (!mmres)
1061 return -ENODEV;
1062
1063 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1064
1065 return ret ? 0 : -EBUSY;
1066 }
1067
1068 /*
1069 * Configure/autoconfigure the port.
1070 */
imx_config_port(struct uart_port * port,int flags)1071 static void imx_config_port(struct uart_port *port, int flags)
1072 {
1073 struct imx_port *sport = (struct imx_port *)port;
1074
1075 if (flags & UART_CONFIG_TYPE &&
1076 imx_request_port(&sport->port) == 0)
1077 sport->port.type = PORT_IMX;
1078 }
1079
1080 /*
1081 * Verify the new serial_struct (for TIOCSSERIAL).
1082 * The only change we allow are to the flags and type, and
1083 * even then only between PORT_IMX and PORT_UNKNOWN
1084 */
1085 static int
imx_verify_port(struct uart_port * port,struct serial_struct * ser)1086 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1087 {
1088 struct imx_port *sport = (struct imx_port *)port;
1089 int ret = 0;
1090
1091 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1092 ret = -EINVAL;
1093 if (sport->port.irq != ser->irq)
1094 ret = -EINVAL;
1095 if (ser->io_type != UPIO_MEM)
1096 ret = -EINVAL;
1097 if (sport->port.uartclk / 16 != ser->baud_base)
1098 ret = -EINVAL;
1099 if ((void *)sport->port.mapbase != ser->iomem_base)
1100 ret = -EINVAL;
1101 if (sport->port.iobase != ser->port)
1102 ret = -EINVAL;
1103 if (ser->hub6 != 0)
1104 ret = -EINVAL;
1105 return ret;
1106 }
1107
1108 #if defined(CONFIG_CONSOLE_POLL)
imx_poll_get_char(struct uart_port * port)1109 static int imx_poll_get_char(struct uart_port *port)
1110 {
1111 struct imx_port_ucrs old_ucr;
1112 unsigned int status;
1113 unsigned char c;
1114
1115 /* save control registers */
1116 imx_port_ucrs_save(port, &old_ucr);
1117
1118 /* disable interrupts */
1119 writel(UCR1_UARTEN, port->membase + UCR1);
1120 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1121 port->membase + UCR2);
1122 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1123 port->membase + UCR3);
1124
1125 /* poll */
1126 do {
1127 status = readl(port->membase + USR2);
1128 } while (~status & USR2_RDR);
1129
1130 /* read */
1131 c = readl(port->membase + URXD0);
1132
1133 /* restore control registers */
1134 imx_port_ucrs_restore(port, &old_ucr);
1135
1136 return c;
1137 }
1138
imx_poll_put_char(struct uart_port * port,unsigned char c)1139 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1140 {
1141 struct imx_port_ucrs old_ucr;
1142 unsigned int status;
1143
1144 /* save control registers */
1145 imx_port_ucrs_save(port, &old_ucr);
1146
1147 /* disable interrupts */
1148 writel(UCR1_UARTEN, port->membase + UCR1);
1149 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1150 port->membase + UCR2);
1151 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1152 port->membase + UCR3);
1153
1154 /* drain */
1155 do {
1156 status = readl(port->membase + USR1);
1157 } while (~status & USR1_TRDY);
1158
1159 /* write */
1160 writel(c, port->membase + URTX0);
1161
1162 /* flush */
1163 do {
1164 status = readl(port->membase + USR2);
1165 } while (~status & USR2_TXDC);
1166
1167 /* restore control registers */
1168 imx_port_ucrs_restore(port, &old_ucr);
1169 }
1170 #endif
1171
1172 static struct uart_ops imx_pops = {
1173 .tx_empty = imx_tx_empty,
1174 .set_mctrl = imx_set_mctrl,
1175 .get_mctrl = imx_get_mctrl,
1176 .stop_tx = imx_stop_tx,
1177 .start_tx = imx_start_tx,
1178 .stop_rx = imx_stop_rx,
1179 .enable_ms = imx_enable_ms,
1180 .break_ctl = imx_break_ctl,
1181 .startup = imx_startup,
1182 .shutdown = imx_shutdown,
1183 .set_termios = imx_set_termios,
1184 .type = imx_type,
1185 .release_port = imx_release_port,
1186 .request_port = imx_request_port,
1187 .config_port = imx_config_port,
1188 .verify_port = imx_verify_port,
1189 #if defined(CONFIG_CONSOLE_POLL)
1190 .poll_get_char = imx_poll_get_char,
1191 .poll_put_char = imx_poll_put_char,
1192 #endif
1193 };
1194
1195 static struct imx_port *imx_ports[UART_NR];
1196
1197 #ifdef CONFIG_SERIAL_IMX_CONSOLE
imx_console_putchar(struct uart_port * port,int ch)1198 static void imx_console_putchar(struct uart_port *port, int ch)
1199 {
1200 struct imx_port *sport = (struct imx_port *)port;
1201
1202 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1203 barrier();
1204
1205 writel(ch, sport->port.membase + URTX0);
1206 }
1207
1208 /*
1209 * Interrupts are disabled on entering
1210 */
1211 static void
imx_console_write(struct console * co,const char * s,unsigned int count)1212 imx_console_write(struct console *co, const char *s, unsigned int count)
1213 {
1214 struct imx_port *sport = imx_ports[co->index];
1215 struct imx_port_ucrs old_ucr;
1216 unsigned int ucr1;
1217 unsigned long flags;
1218
1219 spin_lock_irqsave(&sport->port.lock, flags);
1220
1221 /*
1222 * First, save UCR1/2/3 and then disable interrupts
1223 */
1224 imx_port_ucrs_save(&sport->port, &old_ucr);
1225 ucr1 = old_ucr.ucr1;
1226
1227 if (is_imx1_uart(sport))
1228 ucr1 |= IMX1_UCR1_UARTCLKEN;
1229 ucr1 |= UCR1_UARTEN;
1230 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1231
1232 writel(ucr1, sport->port.membase + UCR1);
1233
1234 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1235
1236 uart_console_write(&sport->port, s, count, imx_console_putchar);
1237
1238 /*
1239 * Finally, wait for transmitter to become empty
1240 * and restore UCR1/2/3
1241 */
1242 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1243
1244 imx_port_ucrs_restore(&sport->port, &old_ucr);
1245
1246 spin_unlock_irqrestore(&sport->port.lock, flags);
1247 }
1248
1249 /*
1250 * If the port was already initialised (eg, by a boot loader),
1251 * try to determine the current setup.
1252 */
1253 static void __init
imx_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)1254 imx_console_get_options(struct imx_port *sport, int *baud,
1255 int *parity, int *bits)
1256 {
1257
1258 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1259 /* ok, the port was enabled */
1260 unsigned int ucr2, ubir,ubmr, uartclk;
1261 unsigned int baud_raw;
1262 unsigned int ucfr_rfdiv;
1263
1264 ucr2 = readl(sport->port.membase + UCR2);
1265
1266 *parity = 'n';
1267 if (ucr2 & UCR2_PREN) {
1268 if (ucr2 & UCR2_PROE)
1269 *parity = 'o';
1270 else
1271 *parity = 'e';
1272 }
1273
1274 if (ucr2 & UCR2_WS)
1275 *bits = 8;
1276 else
1277 *bits = 7;
1278
1279 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1280 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1281
1282 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1283 if (ucfr_rfdiv == 6)
1284 ucfr_rfdiv = 7;
1285 else
1286 ucfr_rfdiv = 6 - ucfr_rfdiv;
1287
1288 uartclk = clk_get_rate(sport->clk);
1289 uartclk /= ucfr_rfdiv;
1290
1291 { /*
1292 * The next code provides exact computation of
1293 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1294 * without need of float support or long long division,
1295 * which would be required to prevent 32bit arithmetic overflow
1296 */
1297 unsigned int mul = ubir + 1;
1298 unsigned int div = 16 * (ubmr + 1);
1299 unsigned int rem = uartclk % div;
1300
1301 baud_raw = (uartclk / div) * mul;
1302 baud_raw += (rem * mul + div / 2) / div;
1303 *baud = (baud_raw + 50) / 100 * 100;
1304 }
1305
1306 if(*baud != baud_raw)
1307 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1308 baud_raw, *baud);
1309 }
1310 }
1311
1312 static int __init
imx_console_setup(struct console * co,char * options)1313 imx_console_setup(struct console *co, char *options)
1314 {
1315 struct imx_port *sport;
1316 int baud = 9600;
1317 int bits = 8;
1318 int parity = 'n';
1319 int flow = 'n';
1320
1321 /*
1322 * Check whether an invalid uart number has been specified, and
1323 * if so, search for the first available port that does have
1324 * console support.
1325 */
1326 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1327 co->index = 0;
1328 sport = imx_ports[co->index];
1329 if(sport == NULL)
1330 return -ENODEV;
1331
1332 if (options)
1333 uart_parse_options(options, &baud, &parity, &bits, &flow);
1334 else
1335 imx_console_get_options(sport, &baud, &parity, &bits);
1336
1337 imx_setup_ufcr(sport, 0);
1338
1339 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1340 }
1341
1342 static struct uart_driver imx_reg;
1343 static struct console imx_console = {
1344 .name = DEV_NAME,
1345 .write = imx_console_write,
1346 .device = uart_console_device,
1347 .setup = imx_console_setup,
1348 .flags = CON_PRINTBUFFER,
1349 .index = -1,
1350 .data = &imx_reg,
1351 };
1352
1353 #define IMX_CONSOLE &imx_console
1354 #else
1355 #define IMX_CONSOLE NULL
1356 #endif
1357
1358 static struct uart_driver imx_reg = {
1359 .owner = THIS_MODULE,
1360 .driver_name = DRIVER_NAME,
1361 .dev_name = DEV_NAME,
1362 .major = SERIAL_IMX_MAJOR,
1363 .minor = MINOR_START,
1364 .nr = ARRAY_SIZE(imx_ports),
1365 .cons = IMX_CONSOLE,
1366 };
1367
serial_imx_suspend(struct platform_device * dev,pm_message_t state)1368 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1369 {
1370 struct imx_port *sport = platform_get_drvdata(dev);
1371 unsigned int val;
1372
1373 /* enable wakeup from i.MX UART */
1374 val = readl(sport->port.membase + UCR3);
1375 val |= UCR3_AWAKEN;
1376 writel(val, sport->port.membase + UCR3);
1377
1378 if (sport)
1379 uart_suspend_port(&imx_reg, &sport->port);
1380
1381 return 0;
1382 }
1383
serial_imx_resume(struct platform_device * dev)1384 static int serial_imx_resume(struct platform_device *dev)
1385 {
1386 struct imx_port *sport = platform_get_drvdata(dev);
1387 unsigned int val;
1388
1389 /* disable wakeup from i.MX UART */
1390 val = readl(sport->port.membase + UCR3);
1391 val &= ~UCR3_AWAKEN;
1392 writel(val, sport->port.membase + UCR3);
1393
1394 if (sport)
1395 uart_resume_port(&imx_reg, &sport->port);
1396
1397 return 0;
1398 }
1399
1400 #ifdef CONFIG_OF
1401 /*
1402 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1403 * could successfully get all information from dt or a negative errno.
1404 */
serial_imx_probe_dt(struct imx_port * sport,struct platform_device * pdev)1405 static int serial_imx_probe_dt(struct imx_port *sport,
1406 struct platform_device *pdev)
1407 {
1408 struct device_node *np = pdev->dev.of_node;
1409 const struct of_device_id *of_id =
1410 of_match_device(imx_uart_dt_ids, &pdev->dev);
1411 int ret;
1412
1413 if (!np)
1414 /* no device tree device */
1415 return 1;
1416
1417 ret = of_alias_get_id(np, "serial");
1418 if (ret < 0) {
1419 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1420 return ret;
1421 }
1422 sport->port.line = ret;
1423
1424 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1425 sport->have_rtscts = 1;
1426
1427 if (of_get_property(np, "fsl,irda-mode", NULL))
1428 sport->use_irda = 1;
1429
1430 sport->devdata = of_id->data;
1431
1432 return 0;
1433 }
1434 #else
serial_imx_probe_dt(struct imx_port * sport,struct platform_device * pdev)1435 static inline int serial_imx_probe_dt(struct imx_port *sport,
1436 struct platform_device *pdev)
1437 {
1438 return 1;
1439 }
1440 #endif
1441
serial_imx_probe_pdata(struct imx_port * sport,struct platform_device * pdev)1442 static void serial_imx_probe_pdata(struct imx_port *sport,
1443 struct platform_device *pdev)
1444 {
1445 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1446
1447 sport->port.line = pdev->id;
1448 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1449
1450 if (!pdata)
1451 return;
1452
1453 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1454 sport->have_rtscts = 1;
1455
1456 if (pdata->flags & IMXUART_IRDA)
1457 sport->use_irda = 1;
1458 }
1459
serial_imx_probe(struct platform_device * pdev)1460 static int serial_imx_probe(struct platform_device *pdev)
1461 {
1462 struct imx_port *sport;
1463 struct imxuart_platform_data *pdata;
1464 void __iomem *base;
1465 int ret = 0;
1466 struct resource *res;
1467
1468 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1469 if (!sport)
1470 return -ENOMEM;
1471
1472 ret = serial_imx_probe_dt(sport, pdev);
1473 if (ret > 0)
1474 serial_imx_probe_pdata(sport, pdev);
1475 else if (ret < 0)
1476 goto free;
1477
1478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1479 if (!res) {
1480 ret = -ENODEV;
1481 goto free;
1482 }
1483
1484 base = ioremap(res->start, PAGE_SIZE);
1485 if (!base) {
1486 ret = -ENOMEM;
1487 goto free;
1488 }
1489
1490 sport->port.dev = &pdev->dev;
1491 sport->port.mapbase = res->start;
1492 sport->port.membase = base;
1493 sport->port.type = PORT_IMX,
1494 sport->port.iotype = UPIO_MEM;
1495 sport->port.irq = platform_get_irq(pdev, 0);
1496 sport->rxirq = platform_get_irq(pdev, 0);
1497 sport->txirq = platform_get_irq(pdev, 1);
1498 sport->rtsirq = platform_get_irq(pdev, 2);
1499 sport->port.fifosize = 32;
1500 sport->port.ops = &imx_pops;
1501 sport->port.flags = UPF_BOOT_AUTOCONF;
1502 init_timer(&sport->timer);
1503 sport->timer.function = imx_timeout;
1504 sport->timer.data = (unsigned long)sport;
1505
1506 sport->clk = clk_get(&pdev->dev, "uart");
1507 if (IS_ERR(sport->clk)) {
1508 ret = PTR_ERR(sport->clk);
1509 goto unmap;
1510 }
1511 clk_prepare_enable(sport->clk);
1512
1513 sport->port.uartclk = clk_get_rate(sport->clk);
1514
1515 imx_ports[sport->port.line] = sport;
1516
1517 pdata = pdev->dev.platform_data;
1518 if (pdata && pdata->init) {
1519 ret = pdata->init(pdev);
1520 if (ret)
1521 goto clkput;
1522 }
1523
1524 ret = uart_add_one_port(&imx_reg, &sport->port);
1525 if (ret)
1526 goto deinit;
1527 platform_set_drvdata(pdev, &sport->port);
1528
1529 return 0;
1530 deinit:
1531 if (pdata && pdata->exit)
1532 pdata->exit(pdev);
1533 clkput:
1534 clk_disable_unprepare(sport->clk);
1535 clk_put(sport->clk);
1536 unmap:
1537 iounmap(sport->port.membase);
1538 free:
1539 kfree(sport);
1540
1541 return ret;
1542 }
1543
serial_imx_remove(struct platform_device * pdev)1544 static int serial_imx_remove(struct platform_device *pdev)
1545 {
1546 struct imxuart_platform_data *pdata;
1547 struct imx_port *sport = platform_get_drvdata(pdev);
1548
1549 pdata = pdev->dev.platform_data;
1550
1551 platform_set_drvdata(pdev, NULL);
1552
1553 if (sport) {
1554 uart_remove_one_port(&imx_reg, &sport->port);
1555 clk_disable_unprepare(sport->clk);
1556 clk_put(sport->clk);
1557 }
1558
1559 if (pdata && pdata->exit)
1560 pdata->exit(pdev);
1561
1562 iounmap(sport->port.membase);
1563 kfree(sport);
1564
1565 return 0;
1566 }
1567
1568 static struct platform_driver serial_imx_driver = {
1569 .probe = serial_imx_probe,
1570 .remove = serial_imx_remove,
1571
1572 .suspend = serial_imx_suspend,
1573 .resume = serial_imx_resume,
1574 .id_table = imx_uart_devtype,
1575 .driver = {
1576 .name = "imx-uart",
1577 .owner = THIS_MODULE,
1578 .of_match_table = imx_uart_dt_ids,
1579 },
1580 };
1581
imx_serial_init(void)1582 static int __init imx_serial_init(void)
1583 {
1584 int ret;
1585
1586 printk(KERN_INFO "Serial: IMX driver\n");
1587
1588 ret = uart_register_driver(&imx_reg);
1589 if (ret)
1590 return ret;
1591
1592 ret = platform_driver_register(&serial_imx_driver);
1593 if (ret != 0)
1594 uart_unregister_driver(&imx_reg);
1595
1596 return ret;
1597 }
1598
imx_serial_exit(void)1599 static void __exit imx_serial_exit(void)
1600 {
1601 platform_driver_unregister(&serial_imx_driver);
1602 uart_unregister_driver(&imx_reg);
1603 }
1604
1605 module_init(imx_serial_init);
1606 module_exit(imx_serial_exit);
1607
1608 MODULE_AUTHOR("Sascha Hauer");
1609 MODULE_DESCRIPTION("IMX generic serial port driver");
1610 MODULE_LICENSE("GPL");
1611 MODULE_ALIAS("platform:imx-uart");
1612