1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 * (C) Copyright 2002 Hewlett-Packard Company
7 *
8 * Bus Glue for pxa27x
9 *
10 * Written by Christopher Hoover <ch@hpl.hp.com>
11 * Based on fragments of previous driver by Russell King et al.
12 *
13 * Modified for LH7A404 from ohci-sa1111.c
14 * by Durgesh Pattamatta <pattamattad@sharpsec.com>
15 *
16 * Modified for pxa27x from ohci-lh7a404.c
17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
18 *
19 * This file is licenced under the GPL.
20 */
21
22 #include <linux/device.h>
23 #include <linux/signal.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <mach/hardware.h>
27 #include <mach/ohci.h>
28 #include <mach/pxa3xx-u2d.h>
29
30 /*
31 * UHC: USB Host Controller (OHCI-like) register definitions
32 */
33 #define UHCREV (0x0000) /* UHC HCI Spec Revision */
34 #define UHCHCON (0x0004) /* UHC Host Control Register */
35 #define UHCCOMS (0x0008) /* UHC Command Status Register */
36 #define UHCINTS (0x000C) /* UHC Interrupt Status Register */
37 #define UHCINTE (0x0010) /* UHC Interrupt Enable */
38 #define UHCINTD (0x0014) /* UHC Interrupt Disable */
39 #define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
40 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
41 #define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
42 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
43 #define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
44 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
45 #define UHCDHEAD (0x0030) /* UHC Done Head */
46 #define UHCFMI (0x0034) /* UHC Frame Interval */
47 #define UHCFMR (0x0038) /* UHC Frame Remaining */
48 #define UHCFMN (0x003C) /* UHC Frame Number */
49 #define UHCPERS (0x0040) /* UHC Periodic Start */
50 #define UHCLS (0x0044) /* UHC Low Speed Threshold */
51
52 #define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
53 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
54 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
55 #define UHCRHDA_POTPGT(x) \
56 (((x) & 0xff) << 24) /* Power On To Power Good Time */
57
58 #define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
59 #define UHCRHS (0x0050) /* UHC Root Hub Status */
60 #define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
61 #define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
62 #define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
63
64 #define UHCSTAT (0x0060) /* UHC Status Register */
65 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
66 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
67 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
68 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
69 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
70 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
71 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
72 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
73 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
74
75 #define UHCHR (0x0064) /* UHC Reset Register */
76 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
77 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
78 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
79 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
80 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
81 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
82 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
83 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
84 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
85 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
86 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
87
88 #define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
89 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
90 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
91 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
92 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
93 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
94 Interrupt Enable*/
95 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
96 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
97
98 #define UHCHIT (0x006C) /* UHC Interrupt Test register */
99
100 #define PXA_UHC_MAX_PORTNUM 3
101
102 struct pxa27x_ohci {
103 /* must be 1st member here for hcd_to_ohci() to work */
104 struct ohci_hcd ohci;
105
106 struct device *dev;
107 struct clk *clk;
108 void __iomem *mmio_base;
109 };
110
111 #define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
112
113 /*
114 PMM_NPS_MODE -- PMM Non-power switching mode
115 Ports are powered continuously.
116
117 PMM_GLOBAL_MODE -- PMM global switching mode
118 All ports are powered at the same time.
119
120 PMM_PERPORT_MODE -- PMM per port switching mode
121 Ports are powered individually.
122 */
pxa27x_ohci_select_pmm(struct pxa27x_ohci * ohci,int mode)123 static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
124 {
125 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
126 uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
127
128 switch (mode) {
129 case PMM_NPS_MODE:
130 uhcrhda |= RH_A_NPS;
131 break;
132 case PMM_GLOBAL_MODE:
133 uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
134 break;
135 case PMM_PERPORT_MODE:
136 uhcrhda &= ~(RH_A_NPS);
137 uhcrhda |= RH_A_PSM;
138
139 /* Set port power control mask bits, only 3 ports. */
140 uhcrhdb |= (0x7<<17);
141 break;
142 default:
143 printk( KERN_ERR
144 "Invalid mode %d, set to non-power switch mode.\n",
145 mode );
146
147 uhcrhda |= RH_A_NPS;
148 }
149
150 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
151 __raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
152 return 0;
153 }
154
155 extern int usb_disabled(void);
156
157 /*-------------------------------------------------------------------------*/
158
pxa27x_setup_hc(struct pxa27x_ohci * ohci,struct pxaohci_platform_data * inf)159 static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
160 struct pxaohci_platform_data *inf)
161 {
162 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
163 uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
164
165 if (inf->flags & ENABLE_PORT1)
166 uhchr &= ~UHCHR_SSEP1;
167
168 if (inf->flags & ENABLE_PORT2)
169 uhchr &= ~UHCHR_SSEP2;
170
171 if (inf->flags & ENABLE_PORT3)
172 uhchr &= ~UHCHR_SSEP3;
173
174 if (inf->flags & POWER_CONTROL_LOW)
175 uhchr |= UHCHR_PCPL;
176
177 if (inf->flags & POWER_SENSE_LOW)
178 uhchr |= UHCHR_PSPL;
179
180 if (inf->flags & NO_OC_PROTECTION)
181 uhcrhda |= UHCRHDA_NOCP;
182 else
183 uhcrhda &= ~UHCRHDA_NOCP;
184
185 if (inf->flags & OC_MODE_PERPORT)
186 uhcrhda |= UHCRHDA_OCPM;
187 else
188 uhcrhda &= ~UHCRHDA_OCPM;
189
190 if (inf->power_on_delay) {
191 uhcrhda &= ~UHCRHDA_POTPGT(0xff);
192 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
193 }
194
195 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
196 __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
197 }
198
pxa27x_reset_hc(struct pxa27x_ohci * ohci)199 static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
200 {
201 uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
202
203 __raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
204 udelay(11);
205 __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
206 }
207
208 #ifdef CONFIG_PXA27x
209 extern void pxa27x_clear_otgph(void);
210 #else
211 #define pxa27x_clear_otgph() do {} while (0)
212 #endif
213
pxa27x_start_hc(struct pxa27x_ohci * ohci,struct device * dev)214 static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
215 {
216 int retval = 0;
217 struct pxaohci_platform_data *inf;
218 uint32_t uhchr;
219
220 inf = dev->platform_data;
221
222 clk_prepare_enable(ohci->clk);
223
224 pxa27x_reset_hc(ohci);
225
226 uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
227 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
228
229 while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
230 cpu_relax();
231
232 pxa27x_setup_hc(ohci, inf);
233
234 if (inf->init)
235 retval = inf->init(dev);
236
237 if (retval < 0)
238 return retval;
239
240 if (cpu_is_pxa3xx())
241 pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);
242
243 uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
244 __raw_writel(uhchr, ohci->mmio_base + UHCHR);
245 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
246
247 /* Clear any OTG Pin Hold */
248 pxa27x_clear_otgph();
249 return 0;
250 }
251
pxa27x_stop_hc(struct pxa27x_ohci * ohci,struct device * dev)252 static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
253 {
254 struct pxaohci_platform_data *inf;
255 uint32_t uhccoms;
256
257 inf = dev->platform_data;
258
259 if (cpu_is_pxa3xx())
260 pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
261
262 if (inf->exit)
263 inf->exit(dev);
264
265 pxa27x_reset_hc(ohci);
266
267 /* Host Controller Reset */
268 uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
269 __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
270 udelay(10);
271
272 clk_disable_unprepare(ohci->clk);
273 }
274
275
276 /*-------------------------------------------------------------------------*/
277
278 /* configure so an HC device and id are always provided */
279 /* always called with process context; sleeping is OK */
280
281
282 /**
283 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
284 * Context: !in_interrupt()
285 *
286 * Allocates basic resources for this USB host controller, and
287 * then invokes the start() method for the HCD associated with it
288 * through the hotplug entry's driver_data.
289 *
290 */
usb_hcd_pxa27x_probe(const struct hc_driver * driver,struct platform_device * pdev)291 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
292 {
293 int retval, irq;
294 struct usb_hcd *hcd;
295 struct pxaohci_platform_data *inf;
296 struct pxa27x_ohci *ohci;
297 struct resource *r;
298 struct clk *usb_clk;
299
300 inf = pdev->dev.platform_data;
301
302 if (!inf)
303 return -ENODEV;
304
305 irq = platform_get_irq(pdev, 0);
306 if (irq < 0) {
307 pr_err("no resource of IORESOURCE_IRQ");
308 return -ENXIO;
309 }
310
311 usb_clk = clk_get(&pdev->dev, NULL);
312 if (IS_ERR(usb_clk))
313 return PTR_ERR(usb_clk);
314
315 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
316 if (!hcd) {
317 retval = -ENOMEM;
318 goto err0;
319 }
320
321 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
322 if (!r) {
323 pr_err("no resource of IORESOURCE_MEM");
324 retval = -ENXIO;
325 goto err1;
326 }
327
328 hcd->rsrc_start = r->start;
329 hcd->rsrc_len = resource_size(r);
330
331 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
332 pr_debug("request_mem_region failed");
333 retval = -EBUSY;
334 goto err1;
335 }
336
337 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
338 if (!hcd->regs) {
339 pr_debug("ioremap failed");
340 retval = -ENOMEM;
341 goto err2;
342 }
343
344 /* initialize "struct pxa27x_ohci" */
345 ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
346 ohci->dev = &pdev->dev;
347 ohci->clk = usb_clk;
348 ohci->mmio_base = (void __iomem *)hcd->regs;
349
350 if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
351 pr_debug("pxa27x_start_hc failed");
352 goto err3;
353 }
354
355 /* Select Power Management Mode */
356 pxa27x_ohci_select_pmm(ohci, inf->port_mode);
357
358 if (inf->power_budget)
359 hcd->power_budget = inf->power_budget;
360
361 ohci_hcd_init(hcd_to_ohci(hcd));
362
363 retval = usb_add_hcd(hcd, irq, 0);
364 if (retval == 0)
365 return retval;
366
367 pxa27x_stop_hc(ohci, &pdev->dev);
368 err3:
369 iounmap(hcd->regs);
370 err2:
371 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
372 err1:
373 usb_put_hcd(hcd);
374 err0:
375 clk_put(usb_clk);
376 return retval;
377 }
378
379
380 /* may be called without controller electrically present */
381 /* may be called with controller, bus, and devices active */
382
383 /**
384 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
385 * @dev: USB Host Controller being removed
386 * Context: !in_interrupt()
387 *
388 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
389 * the HCD's stop() method. It is always called from a thread
390 * context, normally "rmmod", "apmd", or something similar.
391 *
392 */
usb_hcd_pxa27x_remove(struct usb_hcd * hcd,struct platform_device * pdev)393 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
394 {
395 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
396
397 usb_remove_hcd(hcd);
398 pxa27x_stop_hc(ohci, &pdev->dev);
399 iounmap(hcd->regs);
400 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
401 usb_put_hcd(hcd);
402 clk_put(ohci->clk);
403 }
404
405 /*-------------------------------------------------------------------------*/
406
407 static int __devinit
ohci_pxa27x_start(struct usb_hcd * hcd)408 ohci_pxa27x_start (struct usb_hcd *hcd)
409 {
410 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
411 int ret;
412
413 ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
414
415 /* The value of NDP in roothub_a is incorrect on this hardware */
416 ohci->num_ports = 3;
417
418 if ((ret = ohci_init(ohci)) < 0)
419 return ret;
420
421 if ((ret = ohci_run (ohci)) < 0) {
422 err ("can't start %s", hcd->self.bus_name);
423 ohci_stop (hcd);
424 return ret;
425 }
426
427 return 0;
428 }
429
430 /*-------------------------------------------------------------------------*/
431
432 static const struct hc_driver ohci_pxa27x_hc_driver = {
433 .description = hcd_name,
434 .product_desc = "PXA27x OHCI",
435 .hcd_priv_size = sizeof(struct pxa27x_ohci),
436
437 /*
438 * generic hardware linkage
439 */
440 .irq = ohci_irq,
441 .flags = HCD_USB11 | HCD_MEMORY,
442
443 /*
444 * basic lifecycle operations
445 */
446 .start = ohci_pxa27x_start,
447 .stop = ohci_stop,
448 .shutdown = ohci_shutdown,
449
450 /*
451 * managing i/o requests and associated device resources
452 */
453 .urb_enqueue = ohci_urb_enqueue,
454 .urb_dequeue = ohci_urb_dequeue,
455 .endpoint_disable = ohci_endpoint_disable,
456
457 /*
458 * scheduling support
459 */
460 .get_frame_number = ohci_get_frame,
461
462 /*
463 * root hub support
464 */
465 .hub_status_data = ohci_hub_status_data,
466 .hub_control = ohci_hub_control,
467 #ifdef CONFIG_PM
468 .bus_suspend = ohci_bus_suspend,
469 .bus_resume = ohci_bus_resume,
470 #endif
471 .start_port_reset = ohci_start_port_reset,
472 };
473
474 /*-------------------------------------------------------------------------*/
475
ohci_hcd_pxa27x_drv_probe(struct platform_device * pdev)476 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
477 {
478 pr_debug ("In ohci_hcd_pxa27x_drv_probe");
479
480 if (usb_disabled())
481 return -ENODEV;
482
483 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
484 }
485
ohci_hcd_pxa27x_drv_remove(struct platform_device * pdev)486 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
487 {
488 struct usb_hcd *hcd = platform_get_drvdata(pdev);
489
490 usb_hcd_pxa27x_remove(hcd, pdev);
491 platform_set_drvdata(pdev, NULL);
492 return 0;
493 }
494
495 #ifdef CONFIG_PM
ohci_hcd_pxa27x_drv_suspend(struct device * dev)496 static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
497 {
498 struct usb_hcd *hcd = dev_get_drvdata(dev);
499 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
500
501 if (time_before(jiffies, ohci->ohci.next_statechange))
502 msleep(5);
503 ohci->ohci.next_statechange = jiffies;
504
505 pxa27x_stop_hc(ohci, dev);
506 return 0;
507 }
508
ohci_hcd_pxa27x_drv_resume(struct device * dev)509 static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
510 {
511 struct usb_hcd *hcd = dev_get_drvdata(dev);
512 struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
513 struct pxaohci_platform_data *inf = dev->platform_data;
514 int status;
515
516 if (time_before(jiffies, ohci->ohci.next_statechange))
517 msleep(5);
518 ohci->ohci.next_statechange = jiffies;
519
520 if ((status = pxa27x_start_hc(ohci, dev)) < 0)
521 return status;
522
523 /* Select Power Management Mode */
524 pxa27x_ohci_select_pmm(ohci, inf->port_mode);
525
526 ohci_finish_controller_resume(hcd);
527 return 0;
528 }
529
530 static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
531 .suspend = ohci_hcd_pxa27x_drv_suspend,
532 .resume = ohci_hcd_pxa27x_drv_resume,
533 };
534 #endif
535
536 /* work with hotplug and coldplug */
537 MODULE_ALIAS("platform:pxa27x-ohci");
538
539 static struct platform_driver ohci_hcd_pxa27x_driver = {
540 .probe = ohci_hcd_pxa27x_drv_probe,
541 .remove = ohci_hcd_pxa27x_drv_remove,
542 .shutdown = usb_hcd_platform_shutdown,
543 .driver = {
544 .name = "pxa27x-ohci",
545 .owner = THIS_MODULE,
546 #ifdef CONFIG_PM
547 .pm = &ohci_hcd_pxa27x_pm_ops,
548 #endif
549 },
550 };
551
552