1 /*
2 * MFD driver for twl6040
3 *
4 * Authors: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
5 * Misael Lopez Cruz <misael.lopez@ti.com>
6 *
7 * Copyright: (C) 2011 Texas Instruments, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25 #ifndef __TWL6040_CODEC_H__
26 #define __TWL6040_CODEC_H__
27
28 #include <linux/interrupt.h>
29 #include <linux/mfd/core.h>
30
31 #define TWL6040_REG_ASICID 0x01
32 #define TWL6040_REG_ASICREV 0x02
33 #define TWL6040_REG_INTID 0x03
34 #define TWL6040_REG_INTMR 0x04
35 #define TWL6040_REG_NCPCTL 0x05
36 #define TWL6040_REG_LDOCTL 0x06
37 #define TWL6040_REG_HPPLLCTL 0x07
38 #define TWL6040_REG_LPPLLCTL 0x08
39 #define TWL6040_REG_LPPLLDIV 0x09
40 #define TWL6040_REG_AMICBCTL 0x0A
41 #define TWL6040_REG_DMICBCTL 0x0B
42 #define TWL6040_REG_MICLCTL 0x0C
43 #define TWL6040_REG_MICRCTL 0x0D
44 #define TWL6040_REG_MICGAIN 0x0E
45 #define TWL6040_REG_LINEGAIN 0x0F
46 #define TWL6040_REG_HSLCTL 0x10
47 #define TWL6040_REG_HSRCTL 0x11
48 #define TWL6040_REG_HSGAIN 0x12
49 #define TWL6040_REG_EARCTL 0x13
50 #define TWL6040_REG_HFLCTL 0x14
51 #define TWL6040_REG_HFLGAIN 0x15
52 #define TWL6040_REG_HFRCTL 0x16
53 #define TWL6040_REG_HFRGAIN 0x17
54 #define TWL6040_REG_VIBCTLL 0x18
55 #define TWL6040_REG_VIBDATL 0x19
56 #define TWL6040_REG_VIBCTLR 0x1A
57 #define TWL6040_REG_VIBDATR 0x1B
58 #define TWL6040_REG_HKCTL1 0x1C
59 #define TWL6040_REG_HKCTL2 0x1D
60 #define TWL6040_REG_GPOCTL 0x1E
61 #define TWL6040_REG_ALB 0x1F
62 #define TWL6040_REG_DLB 0x20
63 #define TWL6040_REG_TRIM1 0x28
64 #define TWL6040_REG_TRIM2 0x29
65 #define TWL6040_REG_TRIM3 0x2A
66 #define TWL6040_REG_HSOTRIM 0x2B
67 #define TWL6040_REG_HFOTRIM 0x2C
68 #define TWL6040_REG_ACCCTL 0x2D
69 #define TWL6040_REG_STATUS 0x2E
70
71 /* INTID (0x03) fields */
72
73 #define TWL6040_THINT 0x01
74 #define TWL6040_PLUGINT 0x02
75 #define TWL6040_UNPLUGINT 0x04
76 #define TWL6040_HOOKINT 0x08
77 #define TWL6040_HFINT 0x10
78 #define TWL6040_VIBINT 0x20
79 #define TWL6040_READYINT 0x40
80
81 /* INTMR (0x04) fields */
82
83 #define TWL6040_THMSK 0x01
84 #define TWL6040_PLUGMSK 0x02
85 #define TWL6040_HOOKMSK 0x08
86 #define TWL6040_HFMSK 0x10
87 #define TWL6040_VIBMSK 0x20
88 #define TWL6040_READYMSK 0x40
89 #define TWL6040_ALLINT_MSK 0x7B
90
91 /* NCPCTL (0x05) fields */
92
93 #define TWL6040_NCPENA 0x01
94 #define TWL6040_NCPOPEN 0x40
95
96 /* LDOCTL (0x06) fields */
97
98 #define TWL6040_LSLDOENA 0x01
99 #define TWL6040_HSLDOENA 0x04
100 #define TWL6040_REFENA 0x40
101 #define TWL6040_OSCENA 0x80
102
103 /* HPPLLCTL (0x07) fields */
104
105 #define TWL6040_HPLLENA 0x01
106 #define TWL6040_HPLLRST 0x02
107 #define TWL6040_HPLLBP 0x04
108 #define TWL6040_HPLLSQRENA 0x08
109 #define TWL6040_MCLK_12000KHZ (0 << 5)
110 #define TWL6040_MCLK_19200KHZ (1 << 5)
111 #define TWL6040_MCLK_26000KHZ (2 << 5)
112 #define TWL6040_MCLK_38400KHZ (3 << 5)
113 #define TWL6040_MCLK_MSK 0x60
114
115 /* LPPLLCTL (0x08) fields */
116
117 #define TWL6040_LPLLENA 0x01
118 #define TWL6040_LPLLRST 0x02
119 #define TWL6040_LPLLSEL 0x04
120 #define TWL6040_LPLLFIN 0x08
121 #define TWL6040_HPLLSEL 0x10
122
123 /* HSLCTL/R (0x10/0x11) fields */
124
125 #define TWL6040_HSDACENA (1 << 0)
126 #define TWL6040_HSDACMODE (1 << 1)
127 #define TWL6040_HSDRVMODE (1 << 3)
128
129 /* VIBCTLL/R (0x18/0x1A) fields */
130
131 #define TWL6040_VIBENA (1 << 0)
132 #define TWL6040_VIBSEL (1 << 1)
133 #define TWL6040_VIBCTRL (1 << 2)
134 #define TWL6040_VIBCTRL_P (1 << 3)
135 #define TWL6040_VIBCTRL_N (1 << 4)
136
137 /* VIBDATL/R (0x19/0x1B) fields */
138
139 #define TWL6040_VIBDAT_MAX 0x64
140
141 /* GPOCTL (0x1E) fields */
142
143 #define TWL6040_GPO1 0x01
144 #define TWL6040_GPO2 0x02
145 #define TWL6040_GPO3 0x03
146
147 /* ACCCTL (0x2D) fields */
148
149 #define TWL6040_I2CSEL 0x01
150 #define TWL6040_RESETSPLIT 0x04
151 #define TWL6040_INTCLRMODE 0x08
152
153 /* STATUS (0x2E) fields */
154
155 #define TWL6040_PLUGCOMP 0x02
156 #define TWL6040_VIBLOCDET 0x10
157 #define TWL6040_VIBROCDET 0x20
158 #define TWL6040_TSHUTDET 0x40
159
160 #define TWL6040_CELLS 2
161
162 #define TWL6040_REV_ES1_0 0x00
163 #define TWL6040_REV_ES1_1 0x01
164 #define TWL6040_REV_ES1_2 0x02
165
166 #define TWL6040_IRQ_TH 0
167 #define TWL6040_IRQ_PLUG 1
168 #define TWL6040_IRQ_HOOK 2
169 #define TWL6040_IRQ_HF 3
170 #define TWL6040_IRQ_VIB 4
171 #define TWL6040_IRQ_READY 5
172
173 /* PLL selection */
174 #define TWL6040_SYSCLK_SEL_LPPLL 0
175 #define TWL6040_SYSCLK_SEL_HPPLL 1
176
177 struct twl6040_codec_data {
178 u16 hs_left_step;
179 u16 hs_right_step;
180 u16 hf_left_step;
181 u16 hf_right_step;
182 };
183
184 struct twl6040_vibra_data {
185 unsigned int vibldrv_res; /* left driver resistance */
186 unsigned int vibrdrv_res; /* right driver resistance */
187 unsigned int viblmotor_res; /* left motor resistance */
188 unsigned int vibrmotor_res; /* right motor resistance */
189 int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */
190 int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */
191 };
192
193 struct twl6040_platform_data {
194 int audpwron_gpio; /* audio power-on gpio */
195 unsigned int irq_base;
196
197 struct twl6040_codec_data *codec;
198 struct twl6040_vibra_data *vibra;
199 };
200
201 struct regmap;
202
203 struct twl6040 {
204 struct device *dev;
205 struct regmap *regmap;
206 struct mutex mutex;
207 struct mutex io_mutex;
208 struct mutex irq_mutex;
209 struct mfd_cell cells[TWL6040_CELLS];
210 struct completion ready;
211
212 int audpwron;
213 int power_count;
214 int rev;
215 u8 vibra_ctrl_cache[2];
216
217 /* PLL configuration */
218 int pll;
219 unsigned int sysclk;
220 unsigned int mclk;
221
222 unsigned int irq;
223 unsigned int irq_base;
224 u8 irq_masks_cur;
225 u8 irq_masks_cache;
226 };
227
228 int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
229 int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
230 u8 val);
231 int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
232 u8 mask);
233 int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
234 u8 mask);
235 int twl6040_power(struct twl6040 *twl6040, int on);
236 int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
237 unsigned int freq_in, unsigned int freq_out);
238 int twl6040_get_pll(struct twl6040 *twl6040);
239 unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
240 int twl6040_irq_init(struct twl6040 *twl6040);
241 void twl6040_irq_exit(struct twl6040 *twl6040);
242 /* Get the combined status of the vibra control register */
243 int twl6040_get_vibralr_status(struct twl6040 *twl6040);
244
twl6040_get_revid(struct twl6040 * twl6040)245 static inline int twl6040_get_revid(struct twl6040 *twl6040)
246 {
247 return twl6040->rev;
248 }
249
250
251 #endif /* End of __TWL6040_CODEC_H__ */
252