1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #define CP_PACKET2 0x80000000 31 #define PACKET2_PAD_SHIFT 0 32 #define PACKET2_PAD_MASK (0x3fffffff << 0) 33 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 35 36 #define R6XX_MAX_SH_GPRS 256 37 #define R6XX_MAX_TEMP_GPRS 16 38 #define R6XX_MAX_SH_THREADS 256 39 #define R6XX_MAX_SH_STACK_ENTRIES 4096 40 #define R6XX_MAX_BACKENDS 8 41 #define R6XX_MAX_BACKENDS_MASK 0xff 42 #define R6XX_MAX_SIMDS 8 43 #define R6XX_MAX_SIMDS_MASK 0xff 44 #define R6XX_MAX_PIPES 8 45 #define R6XX_MAX_PIPES_MASK 0xff 46 47 /* PTE flags */ 48 #define PTE_VALID (1 << 0) 49 #define PTE_SYSTEM (1 << 1) 50 #define PTE_SNOOPED (1 << 2) 51 #define PTE_READABLE (1 << 5) 52 #define PTE_WRITEABLE (1 << 6) 53 54 /* tiling bits */ 55 #define ARRAY_LINEAR_GENERAL 0x00000000 56 #define ARRAY_LINEAR_ALIGNED 0x00000001 57 #define ARRAY_1D_TILED_THIN1 0x00000002 58 #define ARRAY_2D_TILED_THIN1 0x00000004 59 60 /* Registers */ 61 #define ARB_POP 0x2418 62 #define ENABLE_TC128 (1 << 30) 63 #define ARB_GDEC_RD_CNTL 0x246C 64 65 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 66 #define CC_RB_BACKEND_DISABLE 0x98F4 67 #define BACKEND_DISABLE(x) ((x) << 16) 68 69 #define CB_COLOR0_BASE 0x28040 70 #define CB_COLOR1_BASE 0x28044 71 #define CB_COLOR2_BASE 0x28048 72 #define CB_COLOR3_BASE 0x2804C 73 #define CB_COLOR4_BASE 0x28050 74 #define CB_COLOR5_BASE 0x28054 75 #define CB_COLOR6_BASE 0x28058 76 #define CB_COLOR7_BASE 0x2805C 77 #define CB_COLOR7_FRAG 0x280FC 78 79 #define CB_COLOR0_SIZE 0x28060 80 #define CB_COLOR0_VIEW 0x28080 81 #define R_028080_CB_COLOR0_VIEW 0x028080 82 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 83 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 84 #define C_028080_SLICE_START 0xFFFFF800 85 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 86 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 87 #define C_028080_SLICE_MAX 0xFF001FFF 88 #define R_028084_CB_COLOR1_VIEW 0x028084 89 #define R_028088_CB_COLOR2_VIEW 0x028088 90 #define R_02808C_CB_COLOR3_VIEW 0x02808C 91 #define R_028090_CB_COLOR4_VIEW 0x028090 92 #define R_028094_CB_COLOR5_VIEW 0x028094 93 #define R_028098_CB_COLOR6_VIEW 0x028098 94 #define R_02809C_CB_COLOR7_VIEW 0x02809C 95 #define CB_COLOR0_INFO 0x280a0 96 # define CB_FORMAT(x) ((x) << 2) 97 # define CB_ARRAY_MODE(x) ((x) << 8) 98 # define CB_SOURCE_FORMAT(x) ((x) << 27) 99 # define CB_SF_EXPORT_FULL 0 100 # define CB_SF_EXPORT_NORM 1 101 #define CB_COLOR0_TILE 0x280c0 102 #define CB_COLOR0_FRAG 0x280e0 103 #define CB_COLOR0_MASK 0x28100 104 105 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 106 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 107 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 108 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 109 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 110 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 111 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 112 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 113 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 114 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 115 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 116 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 117 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 118 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 119 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 120 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 121 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 122 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 123 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 124 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 125 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 126 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 127 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 128 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 129 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 130 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 131 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 132 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 133 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 134 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 135 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 136 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 137 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 138 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 139 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 140 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 141 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 142 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 143 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 144 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 145 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 146 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 147 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 148 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 149 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 150 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 151 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 152 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 153 154 #define CONFIG_MEMSIZE 0x5428 155 #define CONFIG_CNTL 0x5424 156 #define CP_STAT 0x8680 157 #define CP_COHER_BASE 0x85F8 158 #define CP_DEBUG 0xC1FC 159 #define R_0086D8_CP_ME_CNTL 0x86D8 160 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 161 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 162 #define CP_ME_RAM_DATA 0xC160 163 #define CP_ME_RAM_RADDR 0xC158 164 #define CP_ME_RAM_WADDR 0xC15C 165 #define CP_MEQ_THRESHOLDS 0x8764 166 #define MEQ_END(x) ((x) << 16) 167 #define ROQ_END(x) ((x) << 24) 168 #define CP_PERFMON_CNTL 0x87FC 169 #define CP_PFP_UCODE_ADDR 0xC150 170 #define CP_PFP_UCODE_DATA 0xC154 171 #define CP_QUEUE_THRESHOLDS 0x8760 172 #define ROQ_IB1_START(x) ((x) << 0) 173 #define ROQ_IB2_START(x) ((x) << 8) 174 #define CP_RB_BASE 0xC100 175 #define CP_RB_CNTL 0xC104 176 #define RB_BUFSZ(x) ((x) << 0) 177 #define RB_BLKSZ(x) ((x) << 8) 178 #define RB_NO_UPDATE (1 << 27) 179 #define RB_RPTR_WR_ENA (1 << 31) 180 #define BUF_SWAP_32BIT (2 << 16) 181 #define CP_RB_RPTR 0x8700 182 #define CP_RB_RPTR_ADDR 0xC10C 183 #define RB_RPTR_SWAP(x) ((x) << 0) 184 #define CP_RB_RPTR_ADDR_HI 0xC110 185 #define CP_RB_RPTR_WR 0xC108 186 #define CP_RB_WPTR 0xC114 187 #define CP_RB_WPTR_ADDR 0xC118 188 #define CP_RB_WPTR_ADDR_HI 0xC11C 189 #define CP_RB_WPTR_DELAY 0x8704 190 #define CP_ROQ_IB1_STAT 0x8784 191 #define CP_ROQ_IB2_STAT 0x8788 192 #define CP_SEM_WAIT_TIMER 0x85BC 193 194 #define DB_DEBUG 0x9830 195 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 196 #define DB_DEPTH_BASE 0x2800C 197 #define DB_HTILE_DATA_BASE 0x28014 198 #define DB_HTILE_SURFACE 0x28D24 199 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 200 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 201 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE 202 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 203 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 204 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 205 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 206 #define DB_WATERMARKS 0x9838 207 #define DEPTH_FREE(x) ((x) << 0) 208 #define DEPTH_FLUSH(x) ((x) << 5) 209 #define DEPTH_PENDING_FREE(x) ((x) << 15) 210 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 211 212 #define DCP_TILING_CONFIG 0x6CA0 213 #define PIPE_TILING(x) ((x) << 1) 214 #define BANK_TILING(x) ((x) << 4) 215 #define GROUP_SIZE(x) ((x) << 6) 216 #define ROW_TILING(x) ((x) << 8) 217 #define BANK_SWAPS(x) ((x) << 11) 218 #define SAMPLE_SPLIT(x) ((x) << 14) 219 #define BACKEND_MAP(x) ((x) << 16) 220 221 #define GB_TILING_CONFIG 0x98F0 222 223 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 224 #define INACTIVE_QD_PIPES(x) ((x) << 8) 225 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 226 #define INACTIVE_SIMDS(x) ((x) << 16) 227 #define INACTIVE_SIMDS_MASK 0x00FF0000 228 229 #define SQ_CONFIG 0x8c00 230 # define VC_ENABLE (1 << 0) 231 # define EXPORT_SRC_C (1 << 1) 232 # define DX9_CONSTS (1 << 2) 233 # define ALU_INST_PREFER_VECTOR (1 << 3) 234 # define DX10_CLAMP (1 << 4) 235 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 236 # define PS_PRIO(x) ((x) << 24) 237 # define VS_PRIO(x) ((x) << 26) 238 # define GS_PRIO(x) ((x) << 28) 239 # define ES_PRIO(x) ((x) << 30) 240 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 241 # define NUM_PS_GPRS(x) ((x) << 0) 242 # define NUM_VS_GPRS(x) ((x) << 16) 243 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 244 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 245 # define NUM_GS_GPRS(x) ((x) << 0) 246 # define NUM_ES_GPRS(x) ((x) << 16) 247 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 248 # define NUM_PS_THREADS(x) ((x) << 0) 249 # define NUM_VS_THREADS(x) ((x) << 8) 250 # define NUM_GS_THREADS(x) ((x) << 16) 251 # define NUM_ES_THREADS(x) ((x) << 24) 252 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 253 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 254 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 255 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 256 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 257 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 258 #define SQ_ESGS_RING_BASE 0x8c40 259 #define SQ_GSVS_RING_BASE 0x8c48 260 #define SQ_ESTMP_RING_BASE 0x8c50 261 #define SQ_GSTMP_RING_BASE 0x8c58 262 #define SQ_VSTMP_RING_BASE 0x8c60 263 #define SQ_PSTMP_RING_BASE 0x8c68 264 #define SQ_FBUF_RING_BASE 0x8c70 265 #define SQ_REDUC_RING_BASE 0x8c78 266 267 #define GRBM_CNTL 0x8000 268 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 269 #define GRBM_STATUS 0x8010 270 #define CMDFIFO_AVAIL_MASK 0x0000001F 271 #define GUI_ACTIVE (1<<31) 272 #define GRBM_STATUS2 0x8014 273 #define GRBM_SOFT_RESET 0x8020 274 #define SOFT_RESET_CP (1<<0) 275 276 #define CG_THERMAL_STATUS 0x7F4 277 #define ASIC_T(x) ((x) << 0) 278 #define ASIC_T_MASK 0x1FF 279 #define ASIC_T_SHIFT 0 280 281 #define HDP_HOST_PATH_CNTL 0x2C00 282 #define HDP_NONSURFACE_BASE 0x2C04 283 #define HDP_NONSURFACE_INFO 0x2C08 284 #define HDP_NONSURFACE_SIZE 0x2C0C 285 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 286 #define HDP_TILING_CONFIG 0x2F3C 287 #define HDP_DEBUG1 0x2F34 288 289 #define MC_VM_AGP_TOP 0x2184 290 #define MC_VM_AGP_BOT 0x2188 291 #define MC_VM_AGP_BASE 0x218C 292 #define MC_VM_FB_LOCATION 0x2180 293 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 294 #define ENABLE_L1_TLB (1 << 0) 295 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 296 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 297 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 298 #define SYSTEM_ACCESS_MODE_SHIFT 6 299 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 300 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 301 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 302 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 303 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 304 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 305 #define ENABLE_SEMAPHORE_MODE (1 << 10) 306 #define ENABLE_WAIT_L2_QUERY (1 << 11) 307 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 308 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 309 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 310 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 311 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 312 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 313 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 314 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 315 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 316 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 317 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 318 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 319 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 320 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 321 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 322 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 323 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 324 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 325 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 326 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 327 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 328 #define LOGICAL_PAGE_NUMBER_SHIFT 0 329 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 330 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 331 332 #define PA_CL_ENHANCE 0x8A14 333 #define CLIP_VTX_REORDER_ENA (1 << 0) 334 #define NUM_CLIP_SEQ(x) ((x) << 1) 335 #define PA_SC_AA_CONFIG 0x28C04 336 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 337 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 338 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 339 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 340 #define S0_X(x) ((x) << 0) 341 #define S0_Y(x) ((x) << 4) 342 #define S1_X(x) ((x) << 8) 343 #define S1_Y(x) ((x) << 12) 344 #define S2_X(x) ((x) << 16) 345 #define S2_Y(x) ((x) << 20) 346 #define S3_X(x) ((x) << 24) 347 #define S3_Y(x) ((x) << 28) 348 #define S4_X(x) ((x) << 0) 349 #define S4_Y(x) ((x) << 4) 350 #define S5_X(x) ((x) << 8) 351 #define S5_Y(x) ((x) << 12) 352 #define S6_X(x) ((x) << 16) 353 #define S6_Y(x) ((x) << 20) 354 #define S7_X(x) ((x) << 24) 355 #define S7_Y(x) ((x) << 28) 356 #define PA_SC_CLIPRECT_RULE 0x2820c 357 #define PA_SC_ENHANCE 0x8BF0 358 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 359 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 360 #define PA_SC_LINE_STIPPLE 0x28A0C 361 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 362 #define PA_SC_MODE_CNTL 0x28A4C 363 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 364 365 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 366 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 367 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 368 369 #define PCIE_PORT_INDEX 0x0038 370 #define PCIE_PORT_DATA 0x003C 371 372 #define CHMAP 0x2004 373 #define NOOFCHAN_SHIFT 12 374 #define NOOFCHAN_MASK 0x00003000 375 376 #define RAMCFG 0x2408 377 #define NOOFBANK_SHIFT 0 378 #define NOOFBANK_MASK 0x00000001 379 #define NOOFRANK_SHIFT 1 380 #define NOOFRANK_MASK 0x00000002 381 #define NOOFROWS_SHIFT 2 382 #define NOOFROWS_MASK 0x0000001C 383 #define NOOFCOLS_SHIFT 5 384 #define NOOFCOLS_MASK 0x00000060 385 #define CHANSIZE_SHIFT 7 386 #define CHANSIZE_MASK 0x00000080 387 #define BURSTLENGTH_SHIFT 8 388 #define BURSTLENGTH_MASK 0x00000100 389 #define CHANSIZE_OVERRIDE (1 << 10) 390 391 #define SCRATCH_REG0 0x8500 392 #define SCRATCH_REG1 0x8504 393 #define SCRATCH_REG2 0x8508 394 #define SCRATCH_REG3 0x850C 395 #define SCRATCH_REG4 0x8510 396 #define SCRATCH_REG5 0x8514 397 #define SCRATCH_REG6 0x8518 398 #define SCRATCH_REG7 0x851C 399 #define SCRATCH_UMSK 0x8540 400 #define SCRATCH_ADDR 0x8544 401 402 #define SPI_CONFIG_CNTL 0x9100 403 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 404 #define DISABLE_INTERP_1 (1 << 5) 405 #define SPI_CONFIG_CNTL_1 0x913C 406 #define VTX_DONE_DELAY(x) ((x) << 0) 407 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 408 #define SPI_INPUT_Z 0x286D8 409 #define SPI_PS_IN_CONTROL_0 0x286CC 410 #define NUM_INTERP(x) ((x)<<0) 411 #define POSITION_ENA (1<<8) 412 #define POSITION_CENTROID (1<<9) 413 #define POSITION_ADDR(x) ((x)<<10) 414 #define PARAM_GEN(x) ((x)<<15) 415 #define PARAM_GEN_ADDR(x) ((x)<<19) 416 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 417 #define PERSP_GRADIENT_ENA (1<<28) 418 #define LINEAR_GRADIENT_ENA (1<<29) 419 #define POSITION_SAMPLE (1<<30) 420 #define BARYC_AT_SAMPLE_ENA (1<<31) 421 #define SPI_PS_IN_CONTROL_1 0x286D0 422 #define GEN_INDEX_PIX (1<<0) 423 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 424 #define FRONT_FACE_ENA (1<<8) 425 #define FRONT_FACE_CHAN(x) ((x)<<9) 426 #define FRONT_FACE_ALL_BITS (1<<11) 427 #define FRONT_FACE_ADDR(x) ((x)<<12) 428 #define FOG_ADDR(x) ((x)<<17) 429 #define FIXED_PT_POSITION_ENA (1<<24) 430 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 431 432 #define SQ_MS_FIFO_SIZES 0x8CF0 433 #define CACHE_FIFO_SIZE(x) ((x) << 0) 434 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 435 #define DONE_FIFO_HIWATER(x) ((x) << 16) 436 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 437 #define SQ_PGM_START_ES 0x28880 438 #define SQ_PGM_START_FS 0x28894 439 #define SQ_PGM_START_GS 0x2886C 440 #define SQ_PGM_START_PS 0x28840 441 #define SQ_PGM_RESOURCES_PS 0x28850 442 #define SQ_PGM_EXPORTS_PS 0x28854 443 #define SQ_PGM_CF_OFFSET_PS 0x288cc 444 #define SQ_PGM_START_VS 0x28858 445 #define SQ_PGM_RESOURCES_VS 0x28868 446 #define SQ_PGM_CF_OFFSET_VS 0x288d0 447 448 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 449 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 450 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 451 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 452 # define SQ_VTXC_STRIDE(x) ((x) << 8) 453 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 454 # define SQ_ENDIAN_NONE 0 455 # define SQ_ENDIAN_8IN16 1 456 # define SQ_ENDIAN_8IN32 2 457 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c 458 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 459 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 460 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 461 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 462 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 463 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 464 #define SQ_TEX_VTX_VALID_BUFFER 0x3 465 466 467 #define SX_MISC 0x28350 468 #define SX_MEMORY_EXPORT_BASE 0x9010 469 #define SX_DEBUG_1 0x9054 470 #define SMX_EVENT_RELEASE (1 << 0) 471 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 472 473 #define TA_CNTL_AUX 0x9508 474 #define DISABLE_CUBE_WRAP (1 << 0) 475 #define DISABLE_CUBE_ANISO (1 << 1) 476 #define SYNC_GRADIENT (1 << 24) 477 #define SYNC_WALKER (1 << 25) 478 #define SYNC_ALIGNER (1 << 26) 479 #define BILINEAR_PRECISION_6_BIT (0 << 31) 480 #define BILINEAR_PRECISION_8_BIT (1 << 31) 481 482 #define TC_CNTL 0x9608 483 #define TC_L2_SIZE(x) ((x)<<5) 484 #define L2_DISABLE_LATE_HIT (1<<9) 485 486 #define VC_ENHANCE 0x9714 487 488 #define VGT_CACHE_INVALIDATION 0x88C4 489 #define CACHE_INVALIDATION(x) ((x)<<0) 490 #define VC_ONLY 0 491 #define TC_ONLY 1 492 #define VC_AND_TC 2 493 #define VGT_DMA_BASE 0x287E8 494 #define VGT_DMA_BASE_HI 0x287E4 495 #define VGT_ES_PER_GS 0x88CC 496 #define VGT_GS_PER_ES 0x88C8 497 #define VGT_GS_PER_VS 0x88E8 498 #define VGT_GS_VERTEX_REUSE 0x88D4 499 #define VGT_PRIMITIVE_TYPE 0x8958 500 #define VGT_NUM_INSTANCES 0x8974 501 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 502 #define DEALLOC_DIST_MASK 0x0000007F 503 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 504 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 505 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 506 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 507 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 508 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 509 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 510 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 511 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 512 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 513 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 514 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 515 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 516 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 517 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 518 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 519 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 520 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 521 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 522 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 523 524 #define VGT_STRMOUT_EN 0x28AB0 525 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 526 #define VTX_REUSE_DEPTH_MASK 0x000000FF 527 #define VGT_EVENT_INITIATOR 0x28a90 528 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 529 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 530 531 #define VM_CONTEXT0_CNTL 0x1410 532 #define ENABLE_CONTEXT (1 << 0) 533 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 534 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 535 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 536 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 537 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 538 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 539 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 540 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 541 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 542 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 543 #define RESPONSE_TYPE_MASK 0x000000F0 544 #define RESPONSE_TYPE_SHIFT 4 545 #define VM_L2_CNTL 0x1400 546 #define ENABLE_L2_CACHE (1 << 0) 547 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 548 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 549 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 550 #define VM_L2_CNTL2 0x1404 551 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 552 #define INVALIDATE_L2_CACHE (1 << 1) 553 #define VM_L2_CNTL3 0x1408 554 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 555 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 556 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 557 #define VM_L2_STATUS 0x140C 558 #define L2_BUSY (1 << 0) 559 560 #define WAIT_UNTIL 0x8040 561 #define WAIT_2D_IDLE_bit (1 << 14) 562 #define WAIT_3D_IDLE_bit (1 << 15) 563 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 564 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 565 566 #define IH_RB_CNTL 0x3e00 567 # define IH_RB_ENABLE (1 << 0) 568 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 569 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 570 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 571 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 572 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 573 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 574 #define IH_RB_BASE 0x3e04 575 #define IH_RB_RPTR 0x3e08 576 #define IH_RB_WPTR 0x3e0c 577 # define RB_OVERFLOW (1 << 0) 578 # define WPTR_OFFSET_MASK 0x3fffc 579 #define IH_RB_WPTR_ADDR_HI 0x3e10 580 #define IH_RB_WPTR_ADDR_LO 0x3e14 581 #define IH_CNTL 0x3e18 582 # define ENABLE_INTR (1 << 0) 583 # define IH_MC_SWAP(x) ((x) << 1) 584 # define IH_MC_SWAP_NONE 0 585 # define IH_MC_SWAP_16BIT 1 586 # define IH_MC_SWAP_32BIT 2 587 # define IH_MC_SWAP_64BIT 3 588 # define RPTR_REARM (1 << 4) 589 # define MC_WRREQ_CREDIT(x) ((x) << 15) 590 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 591 592 #define RLC_CNTL 0x3f00 593 # define RLC_ENABLE (1 << 0) 594 #define RLC_HB_BASE 0x3f10 595 #define RLC_HB_CNTL 0x3f0c 596 #define RLC_HB_RPTR 0x3f20 597 #define RLC_HB_WPTR 0x3f1c 598 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 599 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 600 #define RLC_MC_CNTL 0x3f44 601 #define RLC_UCODE_CNTL 0x3f48 602 #define RLC_UCODE_ADDR 0x3f2c 603 #define RLC_UCODE_DATA 0x3f30 604 605 /* new for TN */ 606 #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 607 #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 608 609 #define SRBM_SOFT_RESET 0xe60 610 # define SOFT_RESET_RLC (1 << 13) 611 612 #define CP_INT_CNTL 0xc124 613 # define CNTX_BUSY_INT_ENABLE (1 << 19) 614 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 615 # define SCRATCH_INT_ENABLE (1 << 25) 616 # define TIME_STAMP_INT_ENABLE (1 << 26) 617 # define IB2_INT_ENABLE (1 << 29) 618 # define IB1_INT_ENABLE (1 << 30) 619 # define RB_INT_ENABLE (1 << 31) 620 #define CP_INT_STATUS 0xc128 621 # define SCRATCH_INT_STAT (1 << 25) 622 # define TIME_STAMP_INT_STAT (1 << 26) 623 # define IB2_INT_STAT (1 << 29) 624 # define IB1_INT_STAT (1 << 30) 625 # define RB_INT_STAT (1 << 31) 626 627 #define GRBM_INT_CNTL 0x8060 628 # define RDERR_INT_ENABLE (1 << 0) 629 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 630 # define GUI_IDLE_INT_ENABLE (1 << 19) 631 632 #define INTERRUPT_CNTL 0x5468 633 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 634 # define IH_DUMMY_RD_EN (1 << 1) 635 # define IH_REQ_NONSNOOP_EN (1 << 3) 636 # define GEN_IH_INT_EN (1 << 8) 637 #define INTERRUPT_CNTL2 0x546c 638 639 #define D1MODE_VBLANK_STATUS 0x6534 640 #define D2MODE_VBLANK_STATUS 0x6d34 641 # define DxMODE_VBLANK_OCCURRED (1 << 0) 642 # define DxMODE_VBLANK_ACK (1 << 4) 643 # define DxMODE_VBLANK_STAT (1 << 12) 644 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 645 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 646 #define D1MODE_VLINE_STATUS 0x653c 647 #define D2MODE_VLINE_STATUS 0x6d3c 648 # define DxMODE_VLINE_OCCURRED (1 << 0) 649 # define DxMODE_VLINE_ACK (1 << 4) 650 # define DxMODE_VLINE_STAT (1 << 12) 651 # define DxMODE_VLINE_INTERRUPT (1 << 16) 652 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 653 #define DxMODE_INT_MASK 0x6540 654 # define D1MODE_VBLANK_INT_MASK (1 << 0) 655 # define D1MODE_VLINE_INT_MASK (1 << 4) 656 # define D2MODE_VBLANK_INT_MASK (1 << 8) 657 # define D2MODE_VLINE_INT_MASK (1 << 12) 658 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 659 # define DC_HPD1_INTERRUPT (1 << 18) 660 # define DC_HPD2_INTERRUPT (1 << 19) 661 #define DISP_INTERRUPT_STATUS 0x7edc 662 # define LB_D1_VLINE_INTERRUPT (1 << 2) 663 # define LB_D2_VLINE_INTERRUPT (1 << 3) 664 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 665 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 666 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 667 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 668 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 669 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 670 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 671 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 672 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 673 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 674 # define DC_HPD4_INTERRUPT (1 << 14) 675 # define DC_HPD4_RX_INTERRUPT (1 << 15) 676 # define DC_HPD3_INTERRUPT (1 << 28) 677 # define DC_HPD1_RX_INTERRUPT (1 << 29) 678 # define DC_HPD2_RX_INTERRUPT (1 << 30) 679 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 680 # define DC_HPD3_RX_INTERRUPT (1 << 0) 681 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 682 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 683 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 684 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 685 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 686 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 687 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 688 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 689 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 690 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 691 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 692 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 693 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 694 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 695 /* DCE 3.2 */ 696 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 697 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 698 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 699 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 700 # define DC_HPD5_INTERRUPT (1 << 19) 701 # define DC_HPD5_RX_INTERRUPT (1 << 20) 702 # define DC_HPD6_INTERRUPT (1 << 21) 703 # define DC_HPD6_RX_INTERRUPT (1 << 22) 704 705 #define DACA_AUTO_DETECT_CONTROL 0x7828 706 #define DACB_AUTO_DETECT_CONTROL 0x7a28 707 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 708 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 709 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 710 # define DACx_AUTODETECT_MODE_NONE 0 711 # define DACx_AUTODETECT_MODE_CONNECT 1 712 # define DACx_AUTODETECT_MODE_DISCONNECT 2 713 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 714 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 715 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 716 717 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 718 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 719 #define DACA_AUTODETECT_INT_CONTROL 0x7838 720 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 721 # define DACx_AUTODETECT_ACK (1 << 0) 722 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 723 724 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 725 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 726 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 727 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 728 729 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 730 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 731 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 732 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 733 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 734 735 /* DCE 3.0 */ 736 #define DC_HPD1_INT_STATUS 0x7d00 737 #define DC_HPD2_INT_STATUS 0x7d0c 738 #define DC_HPD3_INT_STATUS 0x7d18 739 #define DC_HPD4_INT_STATUS 0x7d24 740 /* DCE 3.2 */ 741 #define DC_HPD5_INT_STATUS 0x7dc0 742 #define DC_HPD6_INT_STATUS 0x7df4 743 # define DC_HPDx_INT_STATUS (1 << 0) 744 # define DC_HPDx_SENSE (1 << 1) 745 # define DC_HPDx_RX_INT_STATUS (1 << 8) 746 747 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 748 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 749 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 750 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 751 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 752 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 753 /* DCE 3.0 */ 754 #define DC_HPD1_INT_CONTROL 0x7d04 755 #define DC_HPD2_INT_CONTROL 0x7d10 756 #define DC_HPD3_INT_CONTROL 0x7d1c 757 #define DC_HPD4_INT_CONTROL 0x7d28 758 /* DCE 3.2 */ 759 #define DC_HPD5_INT_CONTROL 0x7dc4 760 #define DC_HPD6_INT_CONTROL 0x7df8 761 # define DC_HPDx_INT_ACK (1 << 0) 762 # define DC_HPDx_INT_POLARITY (1 << 8) 763 # define DC_HPDx_INT_EN (1 << 16) 764 # define DC_HPDx_RX_INT_ACK (1 << 20) 765 # define DC_HPDx_RX_INT_EN (1 << 24) 766 767 /* DCE 3.0 */ 768 #define DC_HPD1_CONTROL 0x7d08 769 #define DC_HPD2_CONTROL 0x7d14 770 #define DC_HPD3_CONTROL 0x7d20 771 #define DC_HPD4_CONTROL 0x7d2c 772 /* DCE 3.2 */ 773 #define DC_HPD5_CONTROL 0x7dc8 774 #define DC_HPD6_CONTROL 0x7dfc 775 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 776 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 777 /* DCE 3.2 */ 778 # define DC_HPDx_EN (1 << 28) 779 780 #define D1GRPH_INTERRUPT_STATUS 0x6158 781 #define D2GRPH_INTERRUPT_STATUS 0x6958 782 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 783 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 784 #define D1GRPH_INTERRUPT_CONTROL 0x615c 785 #define D2GRPH_INTERRUPT_CONTROL 0x695c 786 # define DxGRPH_PFLIP_INT_MASK (1 << 0) 787 # define DxGRPH_PFLIP_INT_TYPE (1 << 8) 788 789 /* PCIE link stuff */ 790 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 791 # define LC_POINT_7_PLUS_EN (1 << 6) 792 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 793 # define LC_LINK_WIDTH_SHIFT 0 794 # define LC_LINK_WIDTH_MASK 0x7 795 # define LC_LINK_WIDTH_X0 0 796 # define LC_LINK_WIDTH_X1 1 797 # define LC_LINK_WIDTH_X2 2 798 # define LC_LINK_WIDTH_X4 3 799 # define LC_LINK_WIDTH_X8 4 800 # define LC_LINK_WIDTH_X16 6 801 # define LC_LINK_WIDTH_RD_SHIFT 4 802 # define LC_LINK_WIDTH_RD_MASK 0x70 803 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 804 # define LC_RECONFIG_NOW (1 << 8) 805 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 806 # define LC_RENEGOTIATE_EN (1 << 10) 807 # define LC_SHORT_RECONFIG_EN (1 << 11) 808 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 809 # define LC_UPCONFIGURE_DIS (1 << 13) 810 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 811 # define LC_GEN2_EN_STRAP (1 << 0) 812 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 813 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 814 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 815 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 816 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 817 # define LC_CURRENT_DATA_RATE (1 << 11) 818 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 819 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 820 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 821 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 822 #define MM_CFGREGS_CNTL 0x544c 823 # define MM_WR_TO_CFG_EN (1 << 3) 824 #define LINK_CNTL2 0x88 /* F0 */ 825 # define TARGET_LINK_SPEED_MASK (0xf << 0) 826 # define SELECTABLE_DEEMPHASIS (1 << 6) 827 828 /* 829 * PM4 830 */ 831 #define PACKET_TYPE0 0 832 #define PACKET_TYPE1 1 833 #define PACKET_TYPE2 2 834 #define PACKET_TYPE3 3 835 836 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 837 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 838 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 839 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 840 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 841 (((reg) >> 2) & 0xFFFF) | \ 842 ((n) & 0x3FFF) << 16) 843 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 844 (((op) & 0xFF) << 8) | \ 845 ((n) & 0x3FFF) << 16) 846 847 /* Packet 3 types */ 848 #define PACKET3_NOP 0x10 849 #define PACKET3_INDIRECT_BUFFER_END 0x17 850 #define PACKET3_SET_PREDICATION 0x20 851 #define PACKET3_REG_RMW 0x21 852 #define PACKET3_COND_EXEC 0x22 853 #define PACKET3_PRED_EXEC 0x23 854 #define PACKET3_START_3D_CMDBUF 0x24 855 #define PACKET3_DRAW_INDEX_2 0x27 856 #define PACKET3_CONTEXT_CONTROL 0x28 857 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 858 #define PACKET3_INDEX_TYPE 0x2A 859 #define PACKET3_DRAW_INDEX 0x2B 860 #define PACKET3_DRAW_INDEX_AUTO 0x2D 861 #define PACKET3_DRAW_INDEX_IMMD 0x2E 862 #define PACKET3_NUM_INSTANCES 0x2F 863 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 864 #define PACKET3_INDIRECT_BUFFER_MP 0x38 865 #define PACKET3_MEM_SEMAPHORE 0x39 866 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 867 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 868 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 869 #define PACKET3_MPEG_INDEX 0x3A 870 #define PACKET3_COPY_DW 0x3B 871 #define PACKET3_WAIT_REG_MEM 0x3C 872 #define PACKET3_MEM_WRITE 0x3D 873 #define PACKET3_INDIRECT_BUFFER 0x32 874 #define PACKET3_SURFACE_SYNC 0x43 875 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 876 # define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ 877 # define PACKET3_TC_ACTION_ENA (1 << 23) 878 # define PACKET3_VC_ACTION_ENA (1 << 24) 879 # define PACKET3_CB_ACTION_ENA (1 << 25) 880 # define PACKET3_DB_ACTION_ENA (1 << 26) 881 # define PACKET3_SH_ACTION_ENA (1 << 27) 882 # define PACKET3_SMX_ACTION_ENA (1 << 28) 883 #define PACKET3_ME_INITIALIZE 0x44 884 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 885 #define PACKET3_COND_WRITE 0x45 886 #define PACKET3_EVENT_WRITE 0x46 887 #define EVENT_TYPE(x) ((x) << 0) 888 #define EVENT_INDEX(x) ((x) << 8) 889 /* 0 - any non-TS event 890 * 1 - ZPASS_DONE 891 * 2 - SAMPLE_PIPELINESTAT 892 * 3 - SAMPLE_STREAMOUTSTAT* 893 * 4 - *S_PARTIAL_FLUSH 894 * 5 - TS events 895 */ 896 #define PACKET3_EVENT_WRITE_EOP 0x47 897 #define DATA_SEL(x) ((x) << 29) 898 /* 0 - discard 899 * 1 - send low 32bit data 900 * 2 - send 64bit data 901 * 3 - send 64bit counter value 902 */ 903 #define INT_SEL(x) ((x) << 24) 904 /* 0 - none 905 * 1 - interrupt only (DATA_SEL = 0) 906 * 2 - interrupt when data write is confirmed 907 */ 908 #define PACKET3_ONE_REG_WRITE 0x57 909 #define PACKET3_SET_CONFIG_REG 0x68 910 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 911 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 912 #define PACKET3_SET_CONTEXT_REG 0x69 913 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 914 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 915 #define PACKET3_SET_ALU_CONST 0x6A 916 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 917 #define PACKET3_SET_ALU_CONST_END 0x00032000 918 #define PACKET3_SET_BOOL_CONST 0x6B 919 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 920 #define PACKET3_SET_BOOL_CONST_END 0x00040000 921 #define PACKET3_SET_LOOP_CONST 0x6C 922 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 923 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 924 #define PACKET3_SET_RESOURCE 0x6D 925 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 926 #define PACKET3_SET_RESOURCE_END 0x0003c000 927 #define PACKET3_SET_SAMPLER 0x6E 928 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 929 #define PACKET3_SET_SAMPLER_END 0x0003cff0 930 #define PACKET3_SET_CTL_CONST 0x6F 931 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 932 #define PACKET3_SET_CTL_CONST_END 0x0003e200 933 #define PACKET3_SURFACE_BASE_UPDATE 0x73 934 935 936 #define R_008020_GRBM_SOFT_RESET 0x8020 937 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 938 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 939 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 940 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 941 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 942 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 943 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 944 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 945 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 946 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 947 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 948 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 949 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 950 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 951 #define R_008010_GRBM_STATUS 0x8010 952 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 953 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 954 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 955 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 956 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 957 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 958 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 959 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 960 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 961 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 962 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 963 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 964 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 965 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 966 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 967 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 968 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 969 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 970 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 971 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 972 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 973 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 974 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 975 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 976 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 977 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 978 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 979 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 980 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 981 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 982 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 983 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 984 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 985 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 986 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 987 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 988 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 989 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 990 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 991 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 992 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 993 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 994 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 995 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 996 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 997 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 998 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 999 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1000 #define R_008014_GRBM_STATUS2 0x8014 1001 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1002 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1003 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1004 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1005 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1006 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1007 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1008 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1009 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1010 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1011 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1012 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1013 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1014 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1015 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1016 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1017 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1018 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1019 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1020 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1021 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1022 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1023 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1024 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1025 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1026 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1027 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1028 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1029 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1030 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1031 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1032 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1033 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1034 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1035 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1036 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1037 #define R_000E50_SRBM_STATUS 0x0E50 1038 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1039 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1040 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1041 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1042 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1043 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1044 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1045 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1046 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1047 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1048 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1049 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1050 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1051 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1052 #define R_000E60_SRBM_SOFT_RESET 0x0E60 1053 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1054 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1055 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1056 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1057 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1058 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1059 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1060 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1061 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1062 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1063 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1064 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1065 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1066 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1067 1068 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1069 1070 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 1071 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1072 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1073 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1074 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1075 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1076 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1077 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1078 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1079 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1080 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1081 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1082 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1083 #define C_0280E0_BASE_256B 0x00000000 1084 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1085 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1086 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1087 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1088 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1089 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1090 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1091 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 1092 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1093 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1094 #define C_0280C0_BASE_256B 0x00000000 1095 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 1096 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 1097 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 1098 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 1099 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 1100 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 1101 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 1102 #define R_0280A0_CB_COLOR0_INFO 0x0280A0 1103 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1104 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1105 #define C_0280A0_ENDIAN 0xFFFFFFFC 1106 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1107 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1108 #define C_0280A0_FORMAT 0xFFFFFF03 1109 #define V_0280A0_COLOR_INVALID 0x00000000 1110 #define V_0280A0_COLOR_8 0x00000001 1111 #define V_0280A0_COLOR_4_4 0x00000002 1112 #define V_0280A0_COLOR_3_3_2 0x00000003 1113 #define V_0280A0_COLOR_16 0x00000005 1114 #define V_0280A0_COLOR_16_FLOAT 0x00000006 1115 #define V_0280A0_COLOR_8_8 0x00000007 1116 #define V_0280A0_COLOR_5_6_5 0x00000008 1117 #define V_0280A0_COLOR_6_5_5 0x00000009 1118 #define V_0280A0_COLOR_1_5_5_5 0x0000000A 1119 #define V_0280A0_COLOR_4_4_4_4 0x0000000B 1120 #define V_0280A0_COLOR_5_5_5_1 0x0000000C 1121 #define V_0280A0_COLOR_32 0x0000000D 1122 #define V_0280A0_COLOR_32_FLOAT 0x0000000E 1123 #define V_0280A0_COLOR_16_16 0x0000000F 1124 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1125 #define V_0280A0_COLOR_8_24 0x00000011 1126 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1127 #define V_0280A0_COLOR_24_8 0x00000013 1128 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1129 #define V_0280A0_COLOR_10_11_11 0x00000015 1130 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1131 #define V_0280A0_COLOR_11_11_10 0x00000017 1132 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1133 #define V_0280A0_COLOR_2_10_10_10 0x00000019 1134 #define V_0280A0_COLOR_8_8_8_8 0x0000001A 1135 #define V_0280A0_COLOR_10_10_10_2 0x0000001B 1136 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1137 #define V_0280A0_COLOR_32_32 0x0000001D 1138 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1139 #define V_0280A0_COLOR_16_16_16_16 0x0000001F 1140 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1141 #define V_0280A0_COLOR_32_32_32_32 0x00000022 1142 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1143 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1144 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1145 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1146 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1147 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1148 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1149 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1150 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1151 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1152 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1153 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1154 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1155 #define C_0280A0_READ_SIZE 0xFFFF7FFF 1156 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1157 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1158 #define C_0280A0_COMP_SWAP 0xFFFCFFFF 1159 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1160 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1161 #define C_0280A0_TILE_MODE 0xFFF3FFFF 1162 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1163 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1164 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1165 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1166 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1167 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1168 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1169 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1170 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1171 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1172 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1173 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1174 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1175 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1176 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1177 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1178 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1179 #define C_0280A0_ROUND_MODE 0xFDFFFFFF 1180 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1181 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1182 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1183 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1184 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1185 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1186 #define R_0280A4_CB_COLOR1_INFO 0x0280A4 1187 #define R_0280A8_CB_COLOR2_INFO 0x0280A8 1188 #define R_0280AC_CB_COLOR3_INFO 0x0280AC 1189 #define R_0280B0_CB_COLOR4_INFO 0x0280B0 1190 #define R_0280B4_CB_COLOR5_INFO 0x0280B4 1191 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 1192 #define R_0280BC_CB_COLOR7_INFO 0x0280BC 1193 #define R_028060_CB_COLOR0_SIZE 0x028060 1194 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1195 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1196 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1197 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1198 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1199 #define C_028060_SLICE_TILE_MAX 0xC00003FF 1200 #define R_028064_CB_COLOR1_SIZE 0x028064 1201 #define R_028068_CB_COLOR2_SIZE 0x028068 1202 #define R_02806C_CB_COLOR3_SIZE 0x02806C 1203 #define R_028070_CB_COLOR4_SIZE 0x028070 1204 #define R_028074_CB_COLOR5_SIZE 0x028074 1205 #define R_028078_CB_COLOR6_SIZE 0x028078 1206 #define R_02807C_CB_COLOR7_SIZE 0x02807C 1207 #define R_028238_CB_TARGET_MASK 0x028238 1208 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1209 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1210 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1211 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1212 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1213 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1214 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1215 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1216 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1217 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1218 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1219 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1220 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1221 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1222 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1223 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1224 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1225 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1226 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1227 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1228 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1229 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1230 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1231 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1232 #define R_02823C_CB_SHADER_MASK 0x02823C 1233 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1234 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1235 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1236 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1237 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1238 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1239 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1240 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1241 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1242 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1243 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1244 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1245 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1246 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1247 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1248 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1249 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1250 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1251 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1252 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1253 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1254 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1255 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1256 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1257 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1258 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1259 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1260 #define C_028AB0_STREAMOUT 0xFFFFFFFE 1261 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1262 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1263 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1264 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1265 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1266 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1267 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1268 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1269 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1270 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1271 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1272 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1273 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1274 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1275 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1276 #define C_028B20_SIZE 0x00000000 1277 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1278 #define S_038000_DIM(x) (((x) & 0x7) << 0) 1279 #define G_038000_DIM(x) (((x) >> 0) & 0x7) 1280 #define C_038000_DIM 0xFFFFFFF8 1281 #define V_038000_SQ_TEX_DIM_1D 0x00000000 1282 #define V_038000_SQ_TEX_DIM_2D 0x00000001 1283 #define V_038000_SQ_TEX_DIM_3D 0x00000002 1284 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1285 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1286 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1287 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1288 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1289 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1290 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1291 #define C_038000_TILE_MODE 0xFFFFFF87 1292 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1293 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1294 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1295 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1296 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1297 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1298 #define C_038000_TILE_TYPE 0xFFFFFF7F 1299 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1300 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1301 #define C_038000_PITCH 0xFFF800FF 1302 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1303 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1304 #define C_038000_TEX_WIDTH 0x0007FFFF 1305 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1306 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1307 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1308 #define C_038004_TEX_HEIGHT 0xFFFFE000 1309 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1310 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1311 #define C_038004_TEX_DEPTH 0xFC001FFF 1312 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1313 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1314 #define C_038004_DATA_FORMAT 0x03FFFFFF 1315 #define V_038004_COLOR_INVALID 0x00000000 1316 #define V_038004_COLOR_8 0x00000001 1317 #define V_038004_COLOR_4_4 0x00000002 1318 #define V_038004_COLOR_3_3_2 0x00000003 1319 #define V_038004_COLOR_16 0x00000005 1320 #define V_038004_COLOR_16_FLOAT 0x00000006 1321 #define V_038004_COLOR_8_8 0x00000007 1322 #define V_038004_COLOR_5_6_5 0x00000008 1323 #define V_038004_COLOR_6_5_5 0x00000009 1324 #define V_038004_COLOR_1_5_5_5 0x0000000A 1325 #define V_038004_COLOR_4_4_4_4 0x0000000B 1326 #define V_038004_COLOR_5_5_5_1 0x0000000C 1327 #define V_038004_COLOR_32 0x0000000D 1328 #define V_038004_COLOR_32_FLOAT 0x0000000E 1329 #define V_038004_COLOR_16_16 0x0000000F 1330 #define V_038004_COLOR_16_16_FLOAT 0x00000010 1331 #define V_038004_COLOR_8_24 0x00000011 1332 #define V_038004_COLOR_8_24_FLOAT 0x00000012 1333 #define V_038004_COLOR_24_8 0x00000013 1334 #define V_038004_COLOR_24_8_FLOAT 0x00000014 1335 #define V_038004_COLOR_10_11_11 0x00000015 1336 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1337 #define V_038004_COLOR_11_11_10 0x00000017 1338 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1339 #define V_038004_COLOR_2_10_10_10 0x00000019 1340 #define V_038004_COLOR_8_8_8_8 0x0000001A 1341 #define V_038004_COLOR_10_10_10_2 0x0000001B 1342 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1343 #define V_038004_COLOR_32_32 0x0000001D 1344 #define V_038004_COLOR_32_32_FLOAT 0x0000001E 1345 #define V_038004_COLOR_16_16_16_16 0x0000001F 1346 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1347 #define V_038004_COLOR_32_32_32_32 0x00000022 1348 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1349 #define V_038004_FMT_1 0x00000025 1350 #define V_038004_FMT_GB_GR 0x00000027 1351 #define V_038004_FMT_BG_RG 0x00000028 1352 #define V_038004_FMT_32_AS_8 0x00000029 1353 #define V_038004_FMT_32_AS_8_8 0x0000002A 1354 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1355 #define V_038004_FMT_8_8_8 0x0000002C 1356 #define V_038004_FMT_16_16_16 0x0000002D 1357 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1358 #define V_038004_FMT_32_32_32 0x0000002F 1359 #define V_038004_FMT_32_32_32_FLOAT 0x00000030 1360 #define V_038004_FMT_BC1 0x00000031 1361 #define V_038004_FMT_BC2 0x00000032 1362 #define V_038004_FMT_BC3 0x00000033 1363 #define V_038004_FMT_BC4 0x00000034 1364 #define V_038004_FMT_BC5 0x00000035 1365 #define V_038004_FMT_BC6 0x00000036 1366 #define V_038004_FMT_BC7 0x00000037 1367 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 1368 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1369 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1370 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1371 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1372 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1373 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1374 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1375 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1376 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1377 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1378 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1379 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1380 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1381 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1382 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1383 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1384 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1385 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1386 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1387 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1388 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1389 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1390 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1391 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1392 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1393 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1394 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1395 #define C_038010_REQUEST_SIZE 0xFFFF3FFF 1396 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1397 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1398 #define C_038010_DST_SEL_X 0xFFF8FFFF 1399 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1400 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1401 #define C_038010_DST_SEL_Y 0xFFC7FFFF 1402 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1403 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1404 #define C_038010_DST_SEL_Z 0xFE3FFFFF 1405 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1406 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1407 #define C_038010_DST_SEL_W 0xF1FFFFFF 1408 # define SQ_SEL_X 0 1409 # define SQ_SEL_Y 1 1410 # define SQ_SEL_Z 2 1411 # define SQ_SEL_W 3 1412 # define SQ_SEL_0 4 1413 # define SQ_SEL_1 5 1414 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1415 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1416 #define C_038010_BASE_LEVEL 0x0FFFFFFF 1417 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1418 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1419 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1420 #define C_038014_LAST_LEVEL 0xFFFFFFF0 1421 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1422 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1423 #define C_038014_BASE_ARRAY 0xFFFE000F 1424 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1425 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1426 #define C_038014_LAST_ARRAY 0xC001FFFF 1427 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1428 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1429 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1430 #define C_0288A8_ITEMSIZE 0xFFFF8000 1431 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1432 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1433 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1434 #define C_008C44_MEM_SIZE 0x00000000 1435 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1436 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1437 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1438 #define C_0288B0_ITEMSIZE 0xFFFF8000 1439 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1440 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1441 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1442 #define C_008C54_MEM_SIZE 0x00000000 1443 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1444 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1445 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1446 #define C_0288C0_ITEMSIZE 0xFFFF8000 1447 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1448 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1449 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1450 #define C_008C74_MEM_SIZE 0x00000000 1451 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1452 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1453 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1454 #define C_0288B4_ITEMSIZE 0xFFFF8000 1455 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1456 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1457 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1458 #define C_008C5C_MEM_SIZE 0x00000000 1459 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1460 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1461 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1462 #define C_0288AC_ITEMSIZE 0xFFFF8000 1463 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1464 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1465 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1466 #define C_008C4C_MEM_SIZE 0x00000000 1467 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1468 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1469 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1470 #define C_0288BC_ITEMSIZE 0xFFFF8000 1471 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1472 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1473 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1474 #define C_008C6C_MEM_SIZE 0x00000000 1475 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1476 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1477 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1478 #define C_0288C4_ITEMSIZE 0xFFFF8000 1479 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1480 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1481 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1482 #define C_008C7C_MEM_SIZE 0x00000000 1483 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1484 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1485 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1486 #define C_0288B8_ITEMSIZE 0xFFFF8000 1487 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1488 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1489 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1490 #define C_008C64_MEM_SIZE 0x00000000 1491 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1492 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1493 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1494 #define C_0288C8_ITEMSIZE 0xFFFF8000 1495 #define R_028010_DB_DEPTH_INFO 0x028010 1496 #define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1497 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1498 #define C_028010_FORMAT 0xFFFFFFF8 1499 #define V_028010_DEPTH_INVALID 0x00000000 1500 #define V_028010_DEPTH_16 0x00000001 1501 #define V_028010_DEPTH_X8_24 0x00000002 1502 #define V_028010_DEPTH_8_24 0x00000003 1503 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1504 #define V_028010_DEPTH_8_24_FLOAT 0x00000005 1505 #define V_028010_DEPTH_32_FLOAT 0x00000006 1506 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1507 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1508 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1509 #define C_028010_READ_SIZE 0xFFFFFFF7 1510 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1511 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1512 #define C_028010_ARRAY_MODE 0xFFF87FFF 1513 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1514 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1515 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1516 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1517 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1518 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1519 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1520 #define C_028010_TILE_COMPACT 0xFBFFFFFF 1521 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1522 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1523 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1524 #define R_028000_DB_DEPTH_SIZE 0x028000 1525 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1526 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1527 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1528 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1529 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1530 #define C_028000_SLICE_TILE_MAX 0xC00003FF 1531 #define R_028004_DB_DEPTH_VIEW 0x028004 1532 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1533 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1534 #define C_028004_SLICE_START 0xFFFFF800 1535 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1536 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1537 #define C_028004_SLICE_MAX 0xFF001FFF 1538 #define R_028800_DB_DEPTH_CONTROL 0x028800 1539 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1540 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1541 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1542 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1543 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1544 #define C_028800_Z_ENABLE 0xFFFFFFFD 1545 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1546 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1547 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1548 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1549 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1550 #define C_028800_ZFUNC 0xFFFFFF8F 1551 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1552 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1553 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1554 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1555 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1556 #define C_028800_STENCILFUNC 0xFFFFF8FF 1557 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1558 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1559 #define C_028800_STENCILFAIL 0xFFFFC7FF 1560 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1561 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1562 #define C_028800_STENCILZPASS 0xFFFE3FFF 1563 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1564 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1565 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1566 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1567 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1568 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1569 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1570 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1571 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1572 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1573 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1574 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1575 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1576 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1577 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1578 1579 #endif 1580