1 #ifndef LINUX_SSB_PCICORE_H_
2 #define LINUX_SSB_PCICORE_H_
3
4 #include <linux/types.h>
5
6 struct pci_dev;
7
8
9 #ifdef CONFIG_SSB_DRIVER_PCICORE
10
11 /* PCI core registers. */
12 #define SSB_PCICORE_CTL 0x0000 /* PCI Control */
13 #define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
14 #define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
15 #define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
16 #define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
17 #define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
18 #define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
19 #define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
20 #define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
21 #define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
22 #define SSB_PCICORE_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
23 #define SSB_PCICORE_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
24 #define SSB_PCICORE_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
25 #define SSB_PCICORE_ISTAT 0x0020 /* Interrupt status */
26 #define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */
27 #define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */
28 #define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
29 #define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
30 #define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */
31 #define SSB_PCICORE_IMASK 0x0024 /* Interrupt mask */
32 #define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */
33 #define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */
34 #define SSB_PCICORE_IMASK_SERR 0x00000004 /* PCI SERR# */
35 #define SSB_PCICORE_IMASK_PERR 0x00000008 /* PCI PERR# */
36 #define SSB_PCICORE_IMASK_PME 0x00000010 /* PCI PME# */
37 #define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */
38 #define SSB_PCICORE_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
39 #define SSB_PCICORE_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
40 #define SSB_PCICORE_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
41 #define SSB_PCICORE_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
42 #define SSB_PCICORE_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
43 #define SSB_PCICORE_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
44 #define SSB_PCICORE_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
45 #define SSB_PCICORE_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
46 #define SSB_PCICORE_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
47 #define SSB_PCICORE_BCAST_ADDR_MASK 0x000000FF
48 #define SSB_PCICORE_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
49 #define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */
50 #define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */
51 #define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */
52 #define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */
53 #define SSB_PCICORE_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
54 #define SSB_PCICORE_SBTOPCI0_MASK 0xFC000000
55 #define SSB_PCICORE_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
56 #define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
57 #define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
58 #define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
59 #define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
60 #define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
61 #define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
62 #define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
63 #define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
64
65 /* SBtoPCIx */
66 #define SSB_PCICORE_SBTOPCI_MEM 0x00000000
67 #define SSB_PCICORE_SBTOPCI_IO 0x00000001
68 #define SSB_PCICORE_SBTOPCI_CFG0 0x00000002
69 #define SSB_PCICORE_SBTOPCI_CFG1 0x00000003
70 #define SSB_PCICORE_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
71 #define SSB_PCICORE_SBTOPCI_BURST 0x00000008 /* Burst enable */
72 #define SSB_PCICORE_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
73 #define SSB_PCICORE_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
74 #define SSB_PCICORE_SBTOPCI_RC_READ 0x00000000 /* Memory read */
75 #define SSB_PCICORE_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
76 #define SSB_PCICORE_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
77
78
79 /* PCIcore specific boardflags */
80 #define SSB_PCICORE_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
81
82
83 struct ssb_pcicore {
84 struct ssb_device *dev;
85 u8 setup_done:1;
86 u8 hostmode:1;
87 u8 cardbusmode:1;
88 };
89
90 extern void ssb_pcicore_init(struct ssb_pcicore *pc);
91
92 /* Enable IRQ routing for a specific device */
93 extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
94 struct ssb_device *dev);
95
96 int ssb_pcicore_plat_dev_init(struct pci_dev *d);
97 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
98
99
100 #else /* CONFIG_SSB_DRIVER_PCICORE */
101
102
103 struct ssb_pcicore {
104 };
105
106 static inline
ssb_pcicore_init(struct ssb_pcicore * pc)107 void ssb_pcicore_init(struct ssb_pcicore *pc)
108 {
109 }
110
111 static inline
ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore * pc,struct ssb_device * dev)112 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
113 struct ssb_device *dev)
114 {
115 return 0;
116 }
117
118 static inline
ssb_pcicore_plat_dev_init(struct pci_dev * d)119 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
120 {
121 return -ENODEV;
122 }
123 static inline
ssb_pcicore_pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)124 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
125 {
126 return -ENODEV;
127 }
128
129 #endif /* CONFIG_SSB_DRIVER_PCICORE */
130 #endif /* LINUX_SSB_PCICORE_H_ */
131