1 /*
2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
3  *
4  *   This program is free software; you can redistribute it and/or
5  *   modify it under the terms of the GNU General Public License
6  *   as published by the Free Software Foundation, version 2.
7  *
8  *   This program is distributed in the hope that it will be useful, but
9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11  *   NON INFRINGEMENT.  See the GNU General Public License for
12  *   more details.
13  */
14 
15 /**
16  * @file
17  *
18  * Some low-level simulator definitions.
19  */
20 
21 #ifndef __ARCH_SIM_DEF_H__
22 #define __ARCH_SIM_DEF_H__
23 
24 
25 /**
26  * Internal: the low bits of the SIM_CONTROL_* SPR values specify
27  * the operation to perform, and the remaining bits are
28  * an operation-specific parameter (often unused).
29  */
30 #define _SIM_CONTROL_OPERATOR_BITS 8
31 
32 
33 /*
34  * Values which can be written to SPR_SIM_CONTROL.
35  */
36 
37 /** If written to SPR_SIM_CONTROL, stops profiling. */
38 #define SIM_CONTROL_PROFILER_DISABLE 0
39 
40 /** If written to SPR_SIM_CONTROL, starts profiling. */
41 #define SIM_CONTROL_PROFILER_ENABLE 1
42 
43 /** If written to SPR_SIM_CONTROL, clears profiling counters. */
44 #define SIM_CONTROL_PROFILER_CLEAR 2
45 
46 /** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
47 #define SIM_CONTROL_CHECKPOINT 3
48 
49 /**
50  * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
51  * sets the tracing mask to the given mask. See "sim_set_tracing()".
52  */
53 #define SIM_CONTROL_SET_TRACING 4
54 
55 /**
56  * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
57  * dumps the requested items of machine state to the log.
58  */
59 #define SIM_CONTROL_DUMP 5
60 
61 /** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
62 #define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
63 
64 /** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
65 #define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
66 
67 /** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
68 #define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
69 
70 /** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
71 #define SIM_CONTROL_ENABLE_FUNCTIONAL 9
72 
73 /** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
74 #define SIM_CONTROL_DISABLE_FUNCTIONAL 10
75 
76 /**
77  * If written to SPR_SIM_CONTROL, enables chip-level functional mode.
78  * All tiles must perform this write for functional mode to be enabled.
79  * Ignored in naked boot mode unless --functional is specified.
80  * WARNING: Only the hypervisor startup code should use this!
81  */
82 #define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
83 
84 /**
85  * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
86  * writes a string directly to the simulator output.  Written to once for
87  * each character in the string, plus a final NUL.  Instead of NUL,
88  * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
89  */
90 /* ISSUE: Document the meaning of "newline", and the handling of NUL. */
91 #define SIM_CONTROL_PUTC 12
92 
93 /**
94  * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
95  * this core.  This is intended to be used before a loop that will
96  * invalidate the cache by loading new data and evicting all current data.
97  * Generally speaking, this API should only be used by system code.
98  */
99 #define SIM_CONTROL_GRINDER_CLEAR 13
100 
101 /** If written to SPR_SIM_CONTROL, shuts down the simulator. */
102 #define SIM_CONTROL_SHUTDOWN 14
103 
104 /**
105  * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
106  * indicates that a fork syscall just created the given process.
107  */
108 #define SIM_CONTROL_OS_FORK 15
109 
110 /**
111  * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
112  * indicates that an exit syscall was just executed by the given process.
113  */
114 #define SIM_CONTROL_OS_EXIT 16
115 
116 /**
117  * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
118  * indicates that the OS just switched to the given process.
119  */
120 #define SIM_CONTROL_OS_SWITCH 17
121 
122 /**
123  * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
124  * indicates that an exec syscall was just executed. Written to once for
125  * each character in the executable name, plus a final NUL.
126  */
127 #define SIM_CONTROL_OS_EXEC 18
128 
129 /**
130  * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
131  * indicates that an interpreter (PT_INTERP) was loaded.  Written to once
132  * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
133  * hex load address starting with "0x", and "PATH" is the executable name.
134  */
135 #define SIM_CONTROL_OS_INTERP 19
136 
137 /**
138  * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
139  * indicates that a dll was loaded.  Written to once for each character
140  * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
141  * address starting with "0x", and "PATH" is the executable name.
142  */
143 #define SIM_CONTROL_DLOPEN 20
144 
145 /**
146  * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
147  * indicates that a dll was unloaded.  Written to once for each character
148  * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
149  * address starting with "0x".
150  */
151 #define SIM_CONTROL_DLCLOSE 21
152 
153 /**
154  * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
155  * indicates whether to allow data reads to remotely-cached
156  * dirty cache lines to be cached locally without grinder warnings or
157  * assertions (used by Linux kernel fast memcpy).
158  */
159 #define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
160 
161 /** If written to SPR_SIM_CONTROL, enables memory tracing. */
162 #define SIM_CONTROL_ENABLE_MEM_LOGGING 23
163 
164 /** If written to SPR_SIM_CONTROL, disables memory tracing. */
165 #define SIM_CONTROL_DISABLE_MEM_LOGGING 24
166 
167 /**
168  * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
169  * the gbe or xgbe shims. Must specify the shim id, the type, the units, and
170  * the rate, as defined in SIM_SHAPING_SPR_ARG.
171  */
172 #define SIM_CONTROL_SHAPING 25
173 
174 /**
175  * If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
176  * requests that a simulator command be executed.  Written to once for each
177  * character in the command, plus a final NUL.
178  */
179 #define SIM_CONTROL_COMMAND 26
180 
181 /**
182  * If written to SPR_SIM_CONTROL, indicates that the simulated system
183  * is panicking, to allow debugging via --debug-on-panic.
184  */
185 #define SIM_CONTROL_PANIC 27
186 
187 /**
188  * If written to SPR_SIM_CONTROL, triggers a simulator syscall.
189  * See "sim_syscall()" for more info.
190  */
191 #define SIM_CONTROL_SYSCALL 32
192 
193 /**
194  * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
195  * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
196  * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
197  */
198 #define SIM_CONTROL_OS_FORK_PARENT 33
199 
200 /**
201  * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
202  * (shifted by 8), clears the pending magic data section.  The cleared
203  * pending magic data section and any subsequently appended magic bytes
204  * will only take effect when the classifier blast programmer is run.
205  */
206 #define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
207 
208 /**
209  * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
210  * (shifted by 8) and a byte of data (shifted by 16), appends that byte
211  * to the shim's pending magic data section.  The pending magic data
212  * section takes effect when the classifier blast programmer is run.
213  */
214 #define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
215 
216 /**
217  * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
218  * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
219  * mask of links (shifted by 32), enable or disable the corresponding
220  * mPIPE links.
221  */
222 #define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
223 
224 
225 /*
226  * Syscall numbers for use with "sim_syscall()".
227  */
228 
229 /** Syscall number for sim_add_watchpoint(). */
230 #define SIM_SYSCALL_ADD_WATCHPOINT 2
231 
232 /** Syscall number for sim_remove_watchpoint(). */
233 #define SIM_SYSCALL_REMOVE_WATCHPOINT 3
234 
235 /** Syscall number for sim_query_watchpoint(). */
236 #define SIM_SYSCALL_QUERY_WATCHPOINT 4
237 
238 /**
239  * Syscall number that asserts that the cache lines whose 64-bit PA
240  * is passed as the second argument to sim_syscall(), and over a
241  * range passed as the third argument, are no longer in cache.
242  * The simulator raises an error if this is not the case.
243  */
244 #define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
245 
246 /** Syscall number for sim_query_cpu_speed(). */
247 #define SIM_SYSCALL_QUERY_CPU_SPEED 6
248 
249 
250 /*
251  * Bit masks which can be shifted by 8, combined with
252  * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
253  */
254 
255 /**
256  * @addtogroup arch_sim
257  * @{
258  */
259 
260 /** Enable --trace-cycle when passed to simulator_set_tracing(). */
261 #define SIM_TRACE_CYCLES          0x01
262 
263 /** Enable --trace-router when passed to simulator_set_tracing(). */
264 #define SIM_TRACE_ROUTER          0x02
265 
266 /** Enable --trace-register-writes when passed to simulator_set_tracing(). */
267 #define SIM_TRACE_REGISTER_WRITES 0x04
268 
269 /** Enable --trace-disasm when passed to simulator_set_tracing(). */
270 #define SIM_TRACE_DISASM          0x08
271 
272 /** Enable --trace-stall-info when passed to simulator_set_tracing(). */
273 #define SIM_TRACE_STALL_INFO      0x10
274 
275 /** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
276 #define SIM_TRACE_MEMORY_CONTROLLER 0x20
277 
278 /** Enable --trace-l2 when passed to simulator_set_tracing(). */
279 #define SIM_TRACE_L2_CACHE 0x40
280 
281 /** Enable --trace-lines when passed to simulator_set_tracing(). */
282 #define SIM_TRACE_LINES 0x80
283 
284 /** Turn off all tracing when passed to simulator_set_tracing(). */
285 #define SIM_TRACE_NONE 0
286 
287 /** Turn on all tracing when passed to simulator_set_tracing(). */
288 #define SIM_TRACE_ALL (-1)
289 
290 /** @} */
291 
292 /** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
293 #define SIM_TRACE_SPR_ARG(mask) \
294   (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
295 
296 
297 /*
298  * Bit masks which can be shifted by 8, combined with
299  * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
300  */
301 
302 /**
303  * @addtogroup arch_sim
304  * @{
305  */
306 
307 /** Dump the general-purpose registers. */
308 #define SIM_DUMP_REGS          0x001
309 
310 /** Dump the SPRs. */
311 #define SIM_DUMP_SPRS          0x002
312 
313 /** Dump the ITLB. */
314 #define SIM_DUMP_ITLB          0x004
315 
316 /** Dump the DTLB. */
317 #define SIM_DUMP_DTLB          0x008
318 
319 /** Dump the L1 I-cache. */
320 #define SIM_DUMP_L1I           0x010
321 
322 /** Dump the L1 D-cache. */
323 #define SIM_DUMP_L1D           0x020
324 
325 /** Dump the L2 cache. */
326 #define SIM_DUMP_L2            0x040
327 
328 /** Dump the switch registers. */
329 #define SIM_DUMP_SNREGS        0x080
330 
331 /** Dump the switch ITLB. */
332 #define SIM_DUMP_SNITLB        0x100
333 
334 /** Dump the switch L1 I-cache. */
335 #define SIM_DUMP_SNL1I         0x200
336 
337 /** Dump the current backtrace. */
338 #define SIM_DUMP_BACKTRACE     0x400
339 
340 /** Only dump valid lines in caches. */
341 #define SIM_DUMP_VALID_LINES   0x800
342 
343 /** Dump everything that is dumpable. */
344 #define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
345 
346 /** @} */
347 
348 /** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
349 #define SIM_DUMP_SPR_ARG(mask) \
350   (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
351 
352 
353 /*
354  * Bit masks which can be shifted by 8, combined with
355  * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
356  */
357 
358 /**
359  * @addtogroup arch_sim
360  * @{
361  */
362 
363 /** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
364 #define SIM_CHIP_MEMCTL        0x001
365 
366 /** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
367 #define SIM_CHIP_XAUI          0x002
368 
369 /** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
370 #define SIM_CHIP_PCIE          0x004
371 
372 /** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
373 #define SIM_CHIP_MPIPE         0x008
374 
375 /** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
376 #define SIM_CHIP_TRIO          0x010
377 
378 /** Reference all chip devices. */
379 #define SIM_CHIP_ALL (-1)
380 
381 /** @} */
382 
383 /** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
384 #define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
385   (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
386 
387 /** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
388 #define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
389   (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
390 
391 /** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
392 #define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
393   (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
394 
395 
396 
397 /* Shim bitrate controls. */
398 
399 /** The number of bits used to store the shim id. */
400 #define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
401 
402 /**
403  * @addtogroup arch_sim
404  * @{
405  */
406 
407 /** Change the gbe 0 bitrate. */
408 #define SIM_CONTROL_SHAPING_GBE_0 0x0
409 
410 /** Change the gbe 1 bitrate. */
411 #define SIM_CONTROL_SHAPING_GBE_1 0x1
412 
413 /** Change the gbe 2 bitrate. */
414 #define SIM_CONTROL_SHAPING_GBE_2 0x2
415 
416 /** Change the gbe 3 bitrate. */
417 #define SIM_CONTROL_SHAPING_GBE_3 0x3
418 
419 /** Change the xgbe 0 bitrate. */
420 #define SIM_CONTROL_SHAPING_XGBE_0 0x4
421 
422 /** Change the xgbe 1 bitrate. */
423 #define SIM_CONTROL_SHAPING_XGBE_1 0x5
424 
425 /** The type of shaping to do. */
426 #define SIM_CONTROL_SHAPING_TYPE_BITS 2
427 
428 /** Control the multiplier. */
429 #define SIM_CONTROL_SHAPING_MULTIPLIER 0
430 
431 /** Control the PPS. */
432 #define SIM_CONTROL_SHAPING_PPS 1
433 
434 /** Control the BPS. */
435 #define SIM_CONTROL_SHAPING_BPS 2
436 
437 /** The number of bits for the units for the shaping parameter. */
438 #define SIM_CONTROL_SHAPING_UNITS_BITS 2
439 
440 /** Provide a number in single units. */
441 #define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
442 
443 /** Provide a number in kilo units. */
444 #define SIM_CONTROL_SHAPING_UNITS_KILO 1
445 
446 /** Provide a number in mega units. */
447 #define SIM_CONTROL_SHAPING_UNITS_MEGA 2
448 
449 /** Provide a number in giga units. */
450 #define SIM_CONTROL_SHAPING_UNITS_GIGA 3
451 
452 /** @} */
453 
454 /** How many bits are available for the rate. */
455 #define SIM_CONTROL_SHAPING_RATE_BITS \
456   (32 - (_SIM_CONTROL_OPERATOR_BITS + \
457          SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
458          SIM_CONTROL_SHAPING_TYPE_BITS + \
459          SIM_CONTROL_SHAPING_UNITS_BITS))
460 
461 /** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
462 #define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
463   (SIM_CONTROL_SHAPING | \
464    ((shim) | \
465    ((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \
466    ((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
467                 SIM_CONTROL_SHAPING_TYPE_BITS)) | \
468    ((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
469                SIM_CONTROL_SHAPING_TYPE_BITS + \
470                SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
471 
472 
473 /*
474  * Values returned when reading SPR_SIM_CONTROL.
475  * ISSUE: These names should share a longer common prefix.
476  */
477 
478 /**
479  * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
480  * (SIM_TRACE_xxx values).
481  */
482 #define SIM_TRACE_FLAG_MASK 0xFFFF
483 
484 /** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
485 #define SIM_PROFILER_ENABLED_MASK 0x10000
486 
487 
488 /*
489  * Special arguments for "SIM_CONTROL_PUTC".
490  */
491 
492 /**
493  * Flag value for forcing a PUTC string-flush, including
494  * coordinate/cycle prefix and newline.
495  */
496 #define SIM_PUTC_FLUSH_STRING 0x100
497 
498 /**
499  * Flag value for forcing a PUTC binary-data-flush, which skips the
500  * prefix and does not append a newline.
501  */
502 #define SIM_PUTC_FLUSH_BINARY 0x101
503 
504 
505 #endif /* __ARCH_SIM_DEF_H__ */
506