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62 
63 #ifndef	__iwl_prph_h__
64 #define __iwl_prph_h__
65 
66 /*
67  * Registers in this file are internal, not PCI bus memory mapped.
68  * Driver accesses these via HBUS_TARG_PRPH_* registers.
69  */
70 #define PRPH_BASE	(0x00000)
71 #define PRPH_END	(0xFFFFF)
72 
73 /* APMG (power management) constants */
74 #define APMG_BASE			(PRPH_BASE + 0x3000)
75 #define APMG_CLK_CTRL_REG		(APMG_BASE + 0x0000)
76 #define APMG_CLK_EN_REG			(APMG_BASE + 0x0004)
77 #define APMG_CLK_DIS_REG		(APMG_BASE + 0x0008)
78 #define APMG_PS_CTRL_REG		(APMG_BASE + 0x000c)
79 #define APMG_PCIDEV_STT_REG		(APMG_BASE + 0x0010)
80 #define APMG_RFKILL_REG			(APMG_BASE + 0x0014)
81 #define APMG_RTC_INT_STT_REG		(APMG_BASE + 0x001c)
82 #define APMG_RTC_INT_MSK_REG		(APMG_BASE + 0x0020)
83 #define APMG_DIGITAL_SVR_REG		(APMG_BASE + 0x0058)
84 #define APMG_ANALOG_SVR_REG		(APMG_BASE + 0x006C)
85 
86 #define APMS_CLK_VAL_MRB_FUNC_MODE	(0x00000001)
87 #define APMG_CLK_VAL_DMA_CLK_RQT	(0x00000200)
88 #define APMG_CLK_VAL_BSM_CLK_RQT	(0x00000800)
89 
90 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS	(0x00400000)
91 #define APMG_PS_CTRL_VAL_RESET_REQ		(0x04000000)
92 #define APMG_PS_CTRL_MSK_PWR_SRC		(0x03000000)
93 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN		(0x00000000)
94 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX		(0x02000000)
95 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK	(0x000001E0) /* bit 8:5 */
96 #define APMG_SVR_DIGITAL_VOLTAGE_1_32		(0x00000060)
97 
98 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS		(0x00000800)
99 
100 /**
101  * Tx Scheduler
102  *
103  * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
104  * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
105  * host DRAM.  It steers each frame's Tx command (which contains the frame
106  * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
107  * device.  A queue maps to only one (selectable by driver) Tx DMA channel,
108  * but one DMA channel may take input from several queues.
109  *
110  * Tx DMA FIFOs have dedicated purposes.
111  *
112  * For 5000 series and up, they are used differently
113  * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
114  *
115  * 0 -- EDCA BK (background) frames, lowest priority
116  * 1 -- EDCA BE (best effort) frames, normal priority
117  * 2 -- EDCA VI (video) frames, higher priority
118  * 3 -- EDCA VO (voice) and management frames, highest priority
119  * 4 -- unused
120  * 5 -- unused
121  * 6 -- unused
122  * 7 -- Commands
123  *
124  * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
125  * In addition, driver can map the remaining queues to Tx DMA/FIFO
126  * channels 0-3 to support 11n aggregation via EDCA DMA channels.
127  *
128  * The driver sets up each queue to work in one of two modes:
129  *
130  * 1)  Scheduler-Ack, in which the scheduler automatically supports a
131  *     block-ack (BA) window of up to 64 TFDs.  In this mode, each queue
132  *     contains TFDs for a unique combination of Recipient Address (RA)
133  *     and Traffic Identifier (TID), that is, traffic of a given
134  *     Quality-Of-Service (QOS) priority, destined for a single station.
135  *
136  *     In scheduler-ack mode, the scheduler keeps track of the Tx status of
137  *     each frame within the BA window, including whether it's been transmitted,
138  *     and whether it's been acknowledged by the receiving station.  The device
139  *     automatically processes block-acks received from the receiving STA,
140  *     and reschedules un-acked frames to be retransmitted (successful
141  *     Tx completion may end up being out-of-order).
142  *
143  *     The driver must maintain the queue's Byte Count table in host DRAM
144  *     for this mode.
145  *     This mode does not support fragmentation.
146  *
147  * 2)  FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
148  *     The device may automatically retry Tx, but will retry only one frame
149  *     at a time, until receiving ACK from receiving station, or reaching
150  *     retry limit and giving up.
151  *
152  *     The command queue (#4/#9) must use this mode!
153  *     This mode does not require use of the Byte Count table in host DRAM.
154  *
155  * Driver controls scheduler operation via 3 means:
156  * 1)  Scheduler registers
157  * 2)  Shared scheduler data base in internal SRAM
158  * 3)  Shared data in host DRAM
159  *
160  * Initialization:
161  *
162  * When loading, driver should allocate memory for:
163  * 1)  16 TFD circular buffers, each with space for (typically) 256 TFDs.
164  * 2)  16 Byte Count circular buffers in 16 KBytes contiguous memory
165  *     (1024 bytes for each queue).
166  *
167  * After receiving "Alive" response from uCode, driver must initialize
168  * the scheduler (especially for queue #4/#9, the command queue, otherwise
169  * the driver can't issue commands!):
170  */
171 #define SCD_MEM_LOWER_BOUND		(0x0000)
172 
173 /**
174  * Max Tx window size is the max number of contiguous TFDs that the scheduler
175  * can keep track of at one time when creating block-ack chains of frames.
176  * Note that "64" matches the number of ack bits in a block-ack packet.
177  */
178 #define SCD_WIN_SIZE				64
179 #define SCD_FRAME_LIMIT				64
180 
181 #define SCD_TXFIFO_POS_TID			(0)
182 #define SCD_TXFIFO_POS_RA			(4)
183 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK	(0x01FF)
184 
185 /* agn SCD */
186 #define SCD_QUEUE_STTS_REG_POS_TXF	(0)
187 #define SCD_QUEUE_STTS_REG_POS_ACTIVE	(3)
188 #define SCD_QUEUE_STTS_REG_POS_WSL	(4)
189 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
190 #define SCD_QUEUE_STTS_REG_MSK		(0x00FF0000)
191 
192 #define SCD_QUEUE_CTX_REG1_CREDIT_POS		(8)
193 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK		(0x00FFFF00)
194 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS	(24)
195 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK	(0xFF000000)
196 #define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS		(0)
197 #define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK		(0x0000007F)
198 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS	(16)
199 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK	(0x007F0000)
200 
201 /* Context Data */
202 #define SCD_CONTEXT_MEM_LOWER_BOUND	(SCD_MEM_LOWER_BOUND + 0x600)
203 #define SCD_CONTEXT_MEM_UPPER_BOUND	(SCD_MEM_LOWER_BOUND + 0x6A0)
204 
205 /* Tx status */
206 #define SCD_TX_STTS_MEM_LOWER_BOUND	(SCD_MEM_LOWER_BOUND + 0x6A0)
207 #define SCD_TX_STTS_MEM_UPPER_BOUND	(SCD_MEM_LOWER_BOUND + 0x7E0)
208 
209 /* Translation Data */
210 #define SCD_TRANS_TBL_MEM_LOWER_BOUND	(SCD_MEM_LOWER_BOUND + 0x7E0)
211 #define SCD_TRANS_TBL_MEM_UPPER_BOUND	(SCD_MEM_LOWER_BOUND + 0x808)
212 
213 #define SCD_CONTEXT_QUEUE_OFFSET(x)\
214 	(SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
215 
216 #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
217 	((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
218 
219 #define SCD_BASE			(PRPH_BASE + 0xa02c00)
220 
221 #define SCD_SRAM_BASE_ADDR	(SCD_BASE + 0x0)
222 #define SCD_DRAM_BASE_ADDR	(SCD_BASE + 0x8)
223 #define SCD_AIT			(SCD_BASE + 0x0c)
224 #define SCD_TXFACT		(SCD_BASE + 0x10)
225 #define SCD_ACTIVE		(SCD_BASE + 0x14)
226 #define SCD_QUEUECHAIN_SEL	(SCD_BASE + 0xe8)
227 #define SCD_CHAINEXT_EN		(SCD_BASE + 0x244)
228 #define SCD_AGGR_SEL		(SCD_BASE + 0x248)
229 #define SCD_INTERRUPT_MASK	(SCD_BASE + 0x108)
230 
SCD_QUEUE_WRPTR(unsigned int chnl)231 static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
232 {
233 	if (chnl < 20)
234 		return SCD_BASE + 0x18 + chnl * 4;
235 	WARN_ON_ONCE(chnl >= 32);
236 	return SCD_BASE + 0x284 + (chnl - 20) * 4;
237 }
238 
SCD_QUEUE_RDPTR(unsigned int chnl)239 static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
240 {
241 	if (chnl < 20)
242 		return SCD_BASE + 0x68 + chnl * 4;
243 	WARN_ON_ONCE(chnl >= 32);
244 	return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
245 }
246 
SCD_QUEUE_STATUS_BITS(unsigned int chnl)247 static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
248 {
249 	if (chnl < 20)
250 		return SCD_BASE + 0x10c + chnl * 4;
251 	WARN_ON_ONCE(chnl >= 32);
252 	return SCD_BASE + 0x384 + (chnl - 20) * 4;
253 }
254 
255 /*********************** END TX SCHEDULER *************************************/
256 
257 #endif				/* __iwl_prph_h__ */
258