1 /* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h 2 * 3 * Copyright 2008 Openmoko, Inc. 4 * Copyright 2008 Simtec Electronics 5 * http://armlinux.simtec.co.uk/ 6 * Ben Dooks <ben@simtec.co.uk> 7 * 8 * S3C - USB2.0 Highspeed/OtG device block registers 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H 16 #define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__ 17 18 #define S3C_HSOTG_REG(x) (x) 19 20 #define S3C_GOTGCTL S3C_HSOTG_REG(0x000) 21 #define S3C_GOTGCTL_BSESVLD (1 << 19) 22 #define S3C_GOTGCTL_ASESVLD (1 << 18) 23 #define S3C_GOTGCTL_DBNC_SHORT (1 << 17) 24 #define S3C_GOTGCTL_CONID_B (1 << 16) 25 #define S3C_GOTGCTL_DEVHNPEN (1 << 11) 26 #define S3C_GOTGCTL_HSSETHNPEN (1 << 10) 27 #define S3C_GOTGCTL_HNPREQ (1 << 9) 28 #define S3C_GOTGCTL_HSTNEGSCS (1 << 8) 29 #define S3C_GOTGCTL_SESREQ (1 << 1) 30 #define S3C_GOTGCTL_SESREQSCS (1 << 0) 31 32 #define S3C_GOTGINT S3C_HSOTG_REG(0x004) 33 #define S3C_GOTGINT_DbnceDone (1 << 19) 34 #define S3C_GOTGINT_ADevTOUTChg (1 << 18) 35 #define S3C_GOTGINT_HstNegDet (1 << 17) 36 #define S3C_GOTGINT_HstnegSucStsChng (1 << 9) 37 #define S3C_GOTGINT_SesReqSucStsChng (1 << 8) 38 #define S3C_GOTGINT_SesEndDet (1 << 2) 39 40 #define S3C_GAHBCFG S3C_HSOTG_REG(0x008) 41 #define S3C_GAHBCFG_PTxFEmpLvl (1 << 8) 42 #define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7) 43 #define S3C_GAHBCFG_DMAEn (1 << 5) 44 #define S3C_GAHBCFG_HBstLen_MASK (0xf << 1) 45 #define S3C_GAHBCFG_HBstLen_SHIFT (1) 46 #define S3C_GAHBCFG_HBstLen_Single (0x0 << 1) 47 #define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1) 48 #define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1) 49 #define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1) 50 #define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1) 51 #define S3C_GAHBCFG_GlblIntrEn (1 << 0) 52 53 #define S3C_GUSBCFG S3C_HSOTG_REG(0x00C) 54 #define S3C_GUSBCFG_PHYLPClkSel (1 << 15) 55 #define S3C_GUSBCFG_HNPCap (1 << 9) 56 #define S3C_GUSBCFG_SRPCap (1 << 8) 57 #define S3C_GUSBCFG_PHYIf16 (1 << 3) 58 #define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0) 59 #define S3C_GUSBCFG_TOutCal_SHIFT (0) 60 #define S3C_GUSBCFG_TOutCal_LIMIT (0x7) 61 #define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0) 62 63 #define S3C_GRSTCTL S3C_HSOTG_REG(0x010) 64 65 #define S3C_GRSTCTL_AHBIdle (1 << 31) 66 #define S3C_GRSTCTL_DMAReq (1 << 30) 67 #define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6) 68 #define S3C_GRSTCTL_TxFNum_SHIFT (6) 69 #define S3C_GRSTCTL_TxFNum_LIMIT (0x1f) 70 #define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6) 71 #define S3C_GRSTCTL_TxFFlsh (1 << 5) 72 #define S3C_GRSTCTL_RxFFlsh (1 << 4) 73 #define S3C_GRSTCTL_INTknQFlsh (1 << 3) 74 #define S3C_GRSTCTL_FrmCntrRst (1 << 2) 75 #define S3C_GRSTCTL_HSftRst (1 << 1) 76 #define S3C_GRSTCTL_CSftRst (1 << 0) 77 78 #define S3C_GINTSTS S3C_HSOTG_REG(0x014) 79 #define S3C_GINTMSK S3C_HSOTG_REG(0x018) 80 81 #define S3C_GINTSTS_WkUpInt (1 << 31) 82 #define S3C_GINTSTS_SessReqInt (1 << 30) 83 #define S3C_GINTSTS_DisconnInt (1 << 29) 84 #define S3C_GINTSTS_ConIDStsChng (1 << 28) 85 #define S3C_GINTSTS_PTxFEmp (1 << 26) 86 #define S3C_GINTSTS_HChInt (1 << 25) 87 #define S3C_GINTSTS_PrtInt (1 << 24) 88 #define S3C_GINTSTS_FetSusp (1 << 22) 89 #define S3C_GINTSTS_incompIP (1 << 21) 90 #define S3C_GINTSTS_IncomplSOIN (1 << 20) 91 #define S3C_GINTSTS_OEPInt (1 << 19) 92 #define S3C_GINTSTS_IEPInt (1 << 18) 93 #define S3C_GINTSTS_EPMis (1 << 17) 94 #define S3C_GINTSTS_EOPF (1 << 15) 95 #define S3C_GINTSTS_ISOutDrop (1 << 14) 96 #define S3C_GINTSTS_EnumDone (1 << 13) 97 #define S3C_GINTSTS_USBRst (1 << 12) 98 #define S3C_GINTSTS_USBSusp (1 << 11) 99 #define S3C_GINTSTS_ErlySusp (1 << 10) 100 #define S3C_GINTSTS_GOUTNakEff (1 << 7) 101 #define S3C_GINTSTS_GINNakEff (1 << 6) 102 #define S3C_GINTSTS_NPTxFEmp (1 << 5) 103 #define S3C_GINTSTS_RxFLvl (1 << 4) 104 #define S3C_GINTSTS_SOF (1 << 3) 105 #define S3C_GINTSTS_OTGInt (1 << 2) 106 #define S3C_GINTSTS_ModeMis (1 << 1) 107 #define S3C_GINTSTS_CurMod_Host (1 << 0) 108 109 #define S3C_GRXSTSR S3C_HSOTG_REG(0x01C) 110 #define S3C_GRXSTSP S3C_HSOTG_REG(0x020) 111 112 #define S3C_GRXSTS_FN_MASK (0x7f << 25) 113 #define S3C_GRXSTS_FN_SHIFT (25) 114 115 #define S3C_GRXSTS_PktSts_MASK (0xf << 17) 116 #define S3C_GRXSTS_PktSts_SHIFT (17) 117 #define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17) 118 #define S3C_GRXSTS_PktSts_OutRX (0x2 << 17) 119 #define S3C_GRXSTS_PktSts_OutDone (0x3 << 17) 120 #define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17) 121 #define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17) 122 123 #define S3C_GRXSTS_DPID_MASK (0x3 << 15) 124 #define S3C_GRXSTS_DPID_SHIFT (15) 125 #define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4) 126 #define S3C_GRXSTS_ByteCnt_SHIFT (4) 127 #define S3C_GRXSTS_EPNum_MASK (0xf << 0) 128 #define S3C_GRXSTS_EPNum_SHIFT (0) 129 130 #define S3C_GRXFSIZ S3C_HSOTG_REG(0x024) 131 132 #define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028) 133 134 #define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16) 135 #define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16) 136 #define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff) 137 #define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16) 138 #define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0) 139 #define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0) 140 #define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff) 141 #define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0) 142 143 #define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C) 144 145 #define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24) 146 #define S3C_GNPTXSTS_NPtxQTop_SHIFT (24) 147 148 #define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16) 149 #define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16) 150 #define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff) 151 152 #define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0) 153 #define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0) 154 #define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff) 155 156 157 #define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100) 158 159 #define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4)) 160 161 #define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16) 162 #define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16) 163 #define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff) 164 #define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff) 165 #define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16) 166 167 #define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0) 168 #define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0) 169 170 /* Device mode registers */ 171 #define S3C_DCFG S3C_HSOTG_REG(0x800) 172 173 #define S3C_DCFG_EPMisCnt_MASK (0x1f << 18) 174 #define S3C_DCFG_EPMisCnt_SHIFT (18) 175 #define S3C_DCFG_EPMisCnt_LIMIT (0x1f) 176 #define S3C_DCFG_EPMisCnt(_x) ((_x) << 18) 177 178 #define S3C_DCFG_PerFrInt_MASK (0x3 << 11) 179 #define S3C_DCFG_PerFrInt_SHIFT (11) 180 #define S3C_DCFG_PerFrInt_LIMIT (0x3) 181 #define S3C_DCFG_PerFrInt(_x) ((_x) << 11) 182 183 #define S3C_DCFG_DevAddr_MASK (0x7f << 4) 184 #define S3C_DCFG_DevAddr_SHIFT (4) 185 #define S3C_DCFG_DevAddr_LIMIT (0x7f) 186 #define S3C_DCFG_DevAddr(_x) ((_x) << 4) 187 188 #define S3C_DCFG_NZStsOUTHShk (1 << 2) 189 190 #define S3C_DCFG_DevSpd_MASK (0x3 << 0) 191 #define S3C_DCFG_DevSpd_SHIFT (0) 192 #define S3C_DCFG_DevSpd_HS (0x0 << 0) 193 #define S3C_DCFG_DevSpd_FS (0x1 << 0) 194 #define S3C_DCFG_DevSpd_LS (0x2 << 0) 195 #define S3C_DCFG_DevSpd_FS48 (0x3 << 0) 196 197 #define S3C_DCTL S3C_HSOTG_REG(0x804) 198 199 #define S3C_DCTL_PWROnPrgDone (1 << 11) 200 #define S3C_DCTL_CGOUTNak (1 << 10) 201 #define S3C_DCTL_SGOUTNak (1 << 9) 202 #define S3C_DCTL_CGNPInNAK (1 << 8) 203 #define S3C_DCTL_SGNPInNAK (1 << 7) 204 #define S3C_DCTL_TstCtl_MASK (0x7 << 4) 205 #define S3C_DCTL_TstCtl_SHIFT (4) 206 #define S3C_DCTL_GOUTNakSts (1 << 3) 207 #define S3C_DCTL_GNPINNakSts (1 << 2) 208 #define S3C_DCTL_SftDiscon (1 << 1) 209 #define S3C_DCTL_RmtWkUpSig (1 << 0) 210 211 #define S3C_DSTS S3C_HSOTG_REG(0x808) 212 213 #define S3C_DSTS_SOFFN_MASK (0x3fff << 8) 214 #define S3C_DSTS_SOFFN_SHIFT (8) 215 #define S3C_DSTS_SOFFN_LIMIT (0x3fff) 216 #define S3C_DSTS_SOFFN(_x) ((_x) << 8) 217 #define S3C_DSTS_ErraticErr (1 << 3) 218 #define S3C_DSTS_EnumSpd_MASK (0x3 << 1) 219 #define S3C_DSTS_EnumSpd_SHIFT (1) 220 #define S3C_DSTS_EnumSpd_HS (0x0 << 1) 221 #define S3C_DSTS_EnumSpd_FS (0x1 << 1) 222 #define S3C_DSTS_EnumSpd_LS (0x2 << 1) 223 #define S3C_DSTS_EnumSpd_FS48 (0x3 << 1) 224 225 #define S3C_DSTS_SuspSts (1 << 0) 226 227 #define S3C_DIEPMSK S3C_HSOTG_REG(0x810) 228 229 #define S3C_DIEPMSK_TxFIFOEmpty (1 << 7) 230 #define S3C_DIEPMSK_INEPNakEffMsk (1 << 6) 231 #define S3C_DIEPMSK_INTknEPMisMsk (1 << 5) 232 #define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4) 233 #define S3C_DIEPMSK_TimeOUTMsk (1 << 3) 234 #define S3C_DIEPMSK_AHBErrMsk (1 << 2) 235 #define S3C_DIEPMSK_EPDisbldMsk (1 << 1) 236 #define S3C_DIEPMSK_XferComplMsk (1 << 0) 237 238 #define S3C_DOEPMSK S3C_HSOTG_REG(0x814) 239 240 #define S3C_DOEPMSK_Back2BackSetup (1 << 6) 241 #define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4) 242 #define S3C_DOEPMSK_SetupMsk (1 << 3) 243 #define S3C_DOEPMSK_AHBErrMsk (1 << 2) 244 #define S3C_DOEPMSK_EPDisbldMsk (1 << 1) 245 #define S3C_DOEPMSK_XferComplMsk (1 << 0) 246 247 #define S3C_DAINT S3C_HSOTG_REG(0x818) 248 #define S3C_DAINTMSK S3C_HSOTG_REG(0x81C) 249 250 #define S3C_DAINT_OutEP_SHIFT (16) 251 #define S3C_DAINT_OutEP(x) (1 << ((x) + 16)) 252 #define S3C_DAINT_InEP(x) (1 << (x)) 253 254 #define S3C_DTKNQR1 S3C_HSOTG_REG(0x820) 255 #define S3C_DTKNQR2 S3C_HSOTG_REG(0x824) 256 #define S3C_DTKNQR3 S3C_HSOTG_REG(0x830) 257 #define S3C_DTKNQR4 S3C_HSOTG_REG(0x834) 258 259 #define S3C_DVBUSDIS S3C_HSOTG_REG(0x828) 260 #define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C) 261 262 #define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900) 263 #define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00) 264 #define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20)) 265 #define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20)) 266 267 /* EP0 specialness: 268 * bits[29..28] - reserved (no SetD0PID, SetD1PID) 269 * bits[25..22] - should always be zero, this isn't a periodic endpoint 270 * bits[10..0] - MPS setting differenct for EP0 271 */ 272 #define S3C_D0EPCTL_MPS_MASK (0x3 << 0) 273 #define S3C_D0EPCTL_MPS_SHIFT (0) 274 #define S3C_D0EPCTL_MPS_64 (0x0 << 0) 275 #define S3C_D0EPCTL_MPS_32 (0x1 << 0) 276 #define S3C_D0EPCTL_MPS_16 (0x2 << 0) 277 #define S3C_D0EPCTL_MPS_8 (0x3 << 0) 278 279 #define S3C_DxEPCTL_EPEna (1 << 31) 280 #define S3C_DxEPCTL_EPDis (1 << 30) 281 #define S3C_DxEPCTL_SetD1PID (1 << 29) 282 #define S3C_DxEPCTL_SetOddFr (1 << 29) 283 #define S3C_DxEPCTL_SetD0PID (1 << 28) 284 #define S3C_DxEPCTL_SetEvenFr (1 << 28) 285 #define S3C_DxEPCTL_SNAK (1 << 27) 286 #define S3C_DxEPCTL_CNAK (1 << 26) 287 #define S3C_DxEPCTL_TxFNum_MASK (0xf << 22) 288 #define S3C_DxEPCTL_TxFNum_SHIFT (22) 289 #define S3C_DxEPCTL_TxFNum_LIMIT (0xf) 290 #define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22) 291 292 #define S3C_DxEPCTL_Stall (1 << 21) 293 #define S3C_DxEPCTL_Snp (1 << 20) 294 #define S3C_DxEPCTL_EPType_MASK (0x3 << 18) 295 #define S3C_DxEPCTL_EPType_SHIFT (18) 296 #define S3C_DxEPCTL_EPType_Control (0x0 << 18) 297 #define S3C_DxEPCTL_EPType_Iso (0x1 << 18) 298 #define S3C_DxEPCTL_EPType_Bulk (0x2 << 18) 299 #define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18) 300 301 #define S3C_DxEPCTL_NAKsts (1 << 17) 302 #define S3C_DxEPCTL_DPID (1 << 16) 303 #define S3C_DxEPCTL_EOFrNum (1 << 16) 304 #define S3C_DxEPCTL_USBActEp (1 << 15) 305 #define S3C_DxEPCTL_NextEp_MASK (0xf << 11) 306 #define S3C_DxEPCTL_NextEp_SHIFT (11) 307 #define S3C_DxEPCTL_NextEp_LIMIT (0xf) 308 #define S3C_DxEPCTL_NextEp(_x) ((_x) << 11) 309 310 #define S3C_DxEPCTL_MPS_MASK (0x7ff << 0) 311 #define S3C_DxEPCTL_MPS_SHIFT (0) 312 #define S3C_DxEPCTL_MPS_LIMIT (0x7ff) 313 #define S3C_DxEPCTL_MPS(_x) ((_x) << 0) 314 315 #define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20)) 316 #define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20)) 317 318 #define S3C_DxEPINT_INEPNakEff (1 << 6) 319 #define S3C_DxEPINT_Back2BackSetup (1 << 6) 320 #define S3C_DxEPINT_INTknEPMis (1 << 5) 321 #define S3C_DxEPINT_INTknTXFEmp (1 << 4) 322 #define S3C_DxEPINT_OUTTknEPdis (1 << 4) 323 #define S3C_DxEPINT_Timeout (1 << 3) 324 #define S3C_DxEPINT_Setup (1 << 3) 325 #define S3C_DxEPINT_AHBErr (1 << 2) 326 #define S3C_DxEPINT_EPDisbld (1 << 1) 327 #define S3C_DxEPINT_XferCompl (1 << 0) 328 329 #define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910) 330 331 #define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19) 332 #define S3C_DIEPTSIZ0_PktCnt_SHIFT (19) 333 #define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3) 334 #define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19) 335 336 #define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0) 337 #define S3C_DIEPTSIZ0_XferSize_SHIFT (0) 338 #define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f) 339 #define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0) 340 341 342 #define DOEPTSIZ0 S3C_HSOTG_REG(0xB10) 343 #define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29) 344 #define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29) 345 #define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3) 346 #define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29) 347 348 #define S3C_DOEPTSIZ0_PktCnt (1 << 19) 349 #define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0) 350 #define S3C_DOEPTSIZ0_XferSize_SHIFT (0) 351 352 #define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20)) 353 #define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20)) 354 355 #define S3C_DxEPTSIZ_MC_MASK (0x3 << 29) 356 #define S3C_DxEPTSIZ_MC_SHIFT (29) 357 #define S3C_DxEPTSIZ_MC_LIMIT (0x3) 358 #define S3C_DxEPTSIZ_MC(_x) ((_x) << 29) 359 360 #define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19) 361 #define S3C_DxEPTSIZ_PktCnt_SHIFT (19) 362 #define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff) 363 #define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff) 364 #define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19) 365 366 #define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0) 367 #define S3C_DxEPTSIZ_XferSize_SHIFT (0) 368 #define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff) 369 #define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff) 370 #define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0) 371 372 373 #define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20)) 374 #define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20)) 375 #define S3C_DTXFSTS(_a) S3C_HSOTG_REG(0x918 + ((_a) * 0x20)) 376 377 #define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000)) 378 379 #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */ 380