1 /* arch/arm/mach-s3c2410/include/mach/regs-mem.h
2  *
3  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4  *		http://www.simtec.co.uk/products/SWLINUX/
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * S3C2410 Memory Control register definitions
11 */
12 
13 #ifndef __ASM_ARM_MEMREGS_H
14 #define __ASM_ARM_MEMREGS_H
15 
16 #ifndef S3C2410_MEMREG
17 #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18 #endif
19 
20 /* bus width, and wait state control */
21 #define S3C2410_BWSCON			S3C2410_MEMREG(0x0000)
22 
23 /* bank zero config - note, pinstrapped from OM pins! */
24 #define S3C2410_BWSCON_DW0_16		(1<<1)
25 #define S3C2410_BWSCON_DW0_32		(2<<1)
26 
27 /* bank one configs */
28 #define S3C2410_BWSCON_DW1_8		(0<<4)
29 #define S3C2410_BWSCON_DW1_16		(1<<4)
30 #define S3C2410_BWSCON_DW1_32		(2<<4)
31 #define S3C2410_BWSCON_WS1		(1<<6)
32 #define S3C2410_BWSCON_ST1		(1<<7)
33 
34 /* bank 2 configurations */
35 #define S3C2410_BWSCON_DW2_8		(0<<8)
36 #define S3C2410_BWSCON_DW2_16		(1<<8)
37 #define S3C2410_BWSCON_DW2_32		(2<<8)
38 #define S3C2410_BWSCON_WS2		(1<<10)
39 #define S3C2410_BWSCON_ST2		(1<<11)
40 
41 /* bank 3 configurations */
42 #define S3C2410_BWSCON_DW3_8		(0<<12)
43 #define S3C2410_BWSCON_DW3_16		(1<<12)
44 #define S3C2410_BWSCON_DW3_32		(2<<12)
45 #define S3C2410_BWSCON_WS3		(1<<14)
46 #define S3C2410_BWSCON_ST3		(1<<15)
47 
48 /* bank 4 configurations */
49 #define S3C2410_BWSCON_DW4_8		(0<<16)
50 #define S3C2410_BWSCON_DW4_16		(1<<16)
51 #define S3C2410_BWSCON_DW4_32		(2<<16)
52 #define S3C2410_BWSCON_WS4		(1<<18)
53 #define S3C2410_BWSCON_ST4		(1<<19)
54 
55 /* bank 5 configurations */
56 #define S3C2410_BWSCON_DW5_8		(0<<20)
57 #define S3C2410_BWSCON_DW5_16		(1<<20)
58 #define S3C2410_BWSCON_DW5_32		(2<<20)
59 #define S3C2410_BWSCON_WS5		(1<<22)
60 #define S3C2410_BWSCON_ST5		(1<<23)
61 
62 /* bank 6 configurations */
63 #define S3C2410_BWSCON_DW6_8		(0<<24)
64 #define S3C2410_BWSCON_DW6_16		(1<<24)
65 #define S3C2410_BWSCON_DW6_32		(2<<24)
66 #define S3C2410_BWSCON_WS6		(1<<26)
67 #define S3C2410_BWSCON_ST6		(1<<27)
68 
69 /* bank 7 configurations */
70 #define S3C2410_BWSCON_DW7_8		(0<<28)
71 #define S3C2410_BWSCON_DW7_16		(1<<28)
72 #define S3C2410_BWSCON_DW7_32		(2<<28)
73 #define S3C2410_BWSCON_WS7		(1<<30)
74 #define S3C2410_BWSCON_ST7		(1<<31)
75 
76 /* accesor functions for getting BANK(n) configuration. (n != 0) */
77 
78 #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79 
80 #define S3C2410_BWSCON_DW8		(0)
81 #define S3C2410_BWSCON_DW16		(1)
82 #define S3C2410_BWSCON_DW32		(2)
83 #define S3C2410_BWSCON_WS		(1 << 2)
84 #define S3C2410_BWSCON_ST		(1 << 3)
85 
86 /* memory set (rom, ram) */
87 #define S3C2410_BANKCON0		S3C2410_MEMREG(0x0004)
88 #define S3C2410_BANKCON1		S3C2410_MEMREG(0x0008)
89 #define S3C2410_BANKCON2		S3C2410_MEMREG(0x000C)
90 #define S3C2410_BANKCON3		S3C2410_MEMREG(0x0010)
91 #define S3C2410_BANKCON4		S3C2410_MEMREG(0x0014)
92 #define S3C2410_BANKCON5		S3C2410_MEMREG(0x0018)
93 #define S3C2410_BANKCON6		S3C2410_MEMREG(0x001C)
94 #define S3C2410_BANKCON7		S3C2410_MEMREG(0x0020)
95 
96 /* bank configuration registers */
97 
98 #define S3C2410_BANKCON_PMCnorm		(0x00)
99 #define S3C2410_BANKCON_PMC4		(0x01)
100 #define S3C2410_BANKCON_PMC8		(0x02)
101 #define S3C2410_BANKCON_PMC16		(0x03)
102 
103 /* bank configurations for banks 0..7, note banks
104  * 6 and 7 have different configurations depending on
105  * the memory type bits */
106 
107 #define S3C2410_BANKCON_Tacp2		(0x0 << 2)
108 #define S3C2410_BANKCON_Tacp3		(0x1 << 2)
109 #define S3C2410_BANKCON_Tacp4		(0x2 << 2)
110 #define S3C2410_BANKCON_Tacp6		(0x3 << 2)
111 #define S3C2410_BANKCON_Tacp_SHIFT	(2)
112 
113 #define S3C2410_BANKCON_Tcah0		(0x0 << 4)
114 #define S3C2410_BANKCON_Tcah1		(0x1 << 4)
115 #define S3C2410_BANKCON_Tcah2		(0x2 << 4)
116 #define S3C2410_BANKCON_Tcah4		(0x3 << 4)
117 #define S3C2410_BANKCON_Tcah_SHIFT	(4)
118 
119 #define S3C2410_BANKCON_Tcoh0		(0x0 << 6)
120 #define S3C2410_BANKCON_Tcoh1		(0x1 << 6)
121 #define S3C2410_BANKCON_Tcoh2		(0x2 << 6)
122 #define S3C2410_BANKCON_Tcoh4		(0x3 << 6)
123 #define S3C2410_BANKCON_Tcoh_SHIFT	(6)
124 
125 #define S3C2410_BANKCON_Tacc1		(0x0 << 8)
126 #define S3C2410_BANKCON_Tacc2		(0x1 << 8)
127 #define S3C2410_BANKCON_Tacc3		(0x2 << 8)
128 #define S3C2410_BANKCON_Tacc4		(0x3 << 8)
129 #define S3C2410_BANKCON_Tacc6		(0x4 << 8)
130 #define S3C2410_BANKCON_Tacc8		(0x5 << 8)
131 #define S3C2410_BANKCON_Tacc10		(0x6 << 8)
132 #define S3C2410_BANKCON_Tacc14		(0x7 << 8)
133 #define S3C2410_BANKCON_Tacc_SHIFT	(8)
134 
135 #define S3C2410_BANKCON_Tcos0		(0x0 << 11)
136 #define S3C2410_BANKCON_Tcos1		(0x1 << 11)
137 #define S3C2410_BANKCON_Tcos2		(0x2 << 11)
138 #define S3C2410_BANKCON_Tcos4		(0x3 << 11)
139 #define S3C2410_BANKCON_Tcos_SHIFT	(11)
140 
141 #define S3C2410_BANKCON_Tacs0		(0x0 << 13)
142 #define S3C2410_BANKCON_Tacs1		(0x1 << 13)
143 #define S3C2410_BANKCON_Tacs2		(0x2 << 13)
144 #define S3C2410_BANKCON_Tacs4		(0x3 << 13)
145 #define S3C2410_BANKCON_Tacs_SHIFT	(13)
146 
147 #define S3C2410_BANKCON_SRAM		(0x0 << 15)
148 #define S3C2410_BANKCON_SDRAM		(0x3 << 15)
149 
150 /* next bits only for SDRAM in 6,7 */
151 #define S3C2410_BANKCON_Trcd2		(0x00 << 2)
152 #define S3C2410_BANKCON_Trcd3		(0x01 << 2)
153 #define S3C2410_BANKCON_Trcd4		(0x02 << 2)
154 
155 /* control column address select */
156 #define S3C2410_BANKCON_SCANb8		(0x00 << 0)
157 #define S3C2410_BANKCON_SCANb9		(0x01 << 0)
158 #define S3C2410_BANKCON_SCANb10		(0x02 << 0)
159 
160 #define S3C2410_REFRESH			S3C2410_MEMREG(0x0024)
161 #define S3C2410_BANKSIZE		S3C2410_MEMREG(0x0028)
162 #define S3C2410_MRSRB6			S3C2410_MEMREG(0x002C)
163 #define S3C2410_MRSRB7			S3C2410_MEMREG(0x0030)
164 
165 /* refresh control */
166 
167 #define S3C2410_REFRESH_REFEN		(1<<23)
168 #define S3C2410_REFRESH_SELF		(1<<22)
169 #define S3C2410_REFRESH_REFCOUNTER	((1<<11)-1)
170 
171 #define S3C2410_REFRESH_TRP_MASK	(3<<20)
172 #define S3C2410_REFRESH_TRP_2clk	(0<<20)
173 #define S3C2410_REFRESH_TRP_3clk	(1<<20)
174 #define S3C2410_REFRESH_TRP_4clk	(2<<20)
175 
176 #define S3C2410_REFRESH_TSRC_MASK	(3<<18)
177 #define S3C2410_REFRESH_TSRC_4clk	(0<<18)
178 #define S3C2410_REFRESH_TSRC_5clk	(1<<18)
179 #define S3C2410_REFRESH_TSRC_6clk	(2<<18)
180 #define S3C2410_REFRESH_TSRC_7clk	(3<<18)
181 
182 
183 /* mode select register(s) */
184 
185 #define  S3C2410_MRSRB_CL1		(0x00 << 4)
186 #define  S3C2410_MRSRB_CL2		(0x02 << 4)
187 #define  S3C2410_MRSRB_CL3		(0x03 << 4)
188 
189 /* bank size register */
190 #define S3C2410_BANKSIZE_128M		(0x2 << 0)
191 #define S3C2410_BANKSIZE_64M		(0x1 << 0)
192 #define S3C2410_BANKSIZE_32M		(0x0 << 0)
193 #define S3C2410_BANKSIZE_16M		(0x7 << 0)
194 #define S3C2410_BANKSIZE_8M		(0x6 << 0)
195 #define S3C2410_BANKSIZE_4M		(0x5 << 0)
196 #define S3C2410_BANKSIZE_2M		(0x4 << 0)
197 #define S3C2410_BANKSIZE_MASK		(0x7 << 0)
198 #define S3C2410_BANKSIZE_SCLK_EN	(1<<4)
199 #define S3C2410_BANKSIZE_SCKE_EN	(1<<5)
200 #define S3C2410_BANKSIZE_BURST		(1<<7)
201 
202 #endif /* __ASM_ARM_MEMREGS_H */
203