1 /* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the 17 Free Software Foundation, Inc., 18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 /* 22 Module: rt2500pci 23 Abstract: Data structures and registers for the rt2500pci module. 24 Supported chipsets: RT2560. 25 */ 26 27 #ifndef RT2500PCI_H 28 #define RT2500PCI_H 29 30 /* 31 * RF chip defines. 32 */ 33 #define RF2522 0x0000 34 #define RF2523 0x0001 35 #define RF2524 0x0002 36 #define RF2525 0x0003 37 #define RF2525E 0x0004 38 #define RF5222 0x0010 39 40 /* 41 * RT2560 version 42 */ 43 #define RT2560_VERSION_B 2 44 #define RT2560_VERSION_C 3 45 #define RT2560_VERSION_D 4 46 47 /* 48 * Signal information. 49 * Default offset is required for RSSI <-> dBm conversion. 50 */ 51 #define DEFAULT_RSSI_OFFSET 121 52 53 /* 54 * Register layout information. 55 */ 56 #define CSR_REG_BASE 0x0000 57 #define CSR_REG_SIZE 0x0174 58 #define EEPROM_BASE 0x0000 59 #define EEPROM_SIZE 0x0200 60 #define BBP_BASE 0x0000 61 #define BBP_SIZE 0x0040 62 #define RF_BASE 0x0004 63 #define RF_SIZE 0x0010 64 65 /* 66 * Number of TX queues. 67 */ 68 #define NUM_TX_QUEUES 2 69 70 /* 71 * Control/Status Registers(CSR). 72 * Some values are set in TU, whereas 1 TU == 1024 us. 73 */ 74 75 /* 76 * CSR0: ASIC revision number. 77 */ 78 #define CSR0 0x0000 79 #define CSR0_REVISION FIELD32(0x0000ffff) 80 81 /* 82 * CSR1: System control register. 83 * SOFT_RESET: Software reset, 1: reset, 0: normal. 84 * BBP_RESET: Hardware reset, 1: reset, 0, release. 85 * HOST_READY: Host ready after initialization. 86 */ 87 #define CSR1 0x0004 88 #define CSR1_SOFT_RESET FIELD32(0x00000001) 89 #define CSR1_BBP_RESET FIELD32(0x00000002) 90 #define CSR1_HOST_READY FIELD32(0x00000004) 91 92 /* 93 * CSR2: System admin status register (invalid). 94 */ 95 #define CSR2 0x0008 96 97 /* 98 * CSR3: STA MAC address register 0. 99 */ 100 #define CSR3 0x000c 101 #define CSR3_BYTE0 FIELD32(0x000000ff) 102 #define CSR3_BYTE1 FIELD32(0x0000ff00) 103 #define CSR3_BYTE2 FIELD32(0x00ff0000) 104 #define CSR3_BYTE3 FIELD32(0xff000000) 105 106 /* 107 * CSR4: STA MAC address register 1. 108 */ 109 #define CSR4 0x0010 110 #define CSR4_BYTE4 FIELD32(0x000000ff) 111 #define CSR4_BYTE5 FIELD32(0x0000ff00) 112 113 /* 114 * CSR5: BSSID register 0. 115 */ 116 #define CSR5 0x0014 117 #define CSR5_BYTE0 FIELD32(0x000000ff) 118 #define CSR5_BYTE1 FIELD32(0x0000ff00) 119 #define CSR5_BYTE2 FIELD32(0x00ff0000) 120 #define CSR5_BYTE3 FIELD32(0xff000000) 121 122 /* 123 * CSR6: BSSID register 1. 124 */ 125 #define CSR6 0x0018 126 #define CSR6_BYTE4 FIELD32(0x000000ff) 127 #define CSR6_BYTE5 FIELD32(0x0000ff00) 128 129 /* 130 * CSR7: Interrupt source register. 131 * Write 1 to clear. 132 * TBCN_EXPIRE: Beacon timer expired interrupt. 133 * TWAKE_EXPIRE: Wakeup timer expired interrupt. 134 * TATIMW_EXPIRE: Timer of atim window expired interrupt. 135 * TXDONE_TXRING: Tx ring transmit done interrupt. 136 * TXDONE_ATIMRING: Atim ring transmit done interrupt. 137 * TXDONE_PRIORING: Priority ring transmit done interrupt. 138 * RXDONE: Receive done interrupt. 139 * DECRYPTION_DONE: Decryption done interrupt. 140 * ENCRYPTION_DONE: Encryption done interrupt. 141 * UART1_TX_TRESHOLD: UART1 TX reaches threshold. 142 * UART1_RX_TRESHOLD: UART1 RX reaches threshold. 143 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. 144 * UART1_TX_BUFF_ERROR: UART1 TX buffer error. 145 * UART1_RX_BUFF_ERROR: UART1 RX buffer error. 146 * UART2_TX_TRESHOLD: UART2 TX reaches threshold. 147 * UART2_RX_TRESHOLD: UART2 RX reaches threshold. 148 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. 149 * UART2_TX_BUFF_ERROR: UART2 TX buffer error. 150 * UART2_RX_BUFF_ERROR: UART2 RX buffer error. 151 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). 152 153 */ 154 #define CSR7 0x001c 155 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001) 156 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) 157 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) 158 #define CSR7_TXDONE_TXRING FIELD32(0x00000008) 159 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) 160 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020) 161 #define CSR7_RXDONE FIELD32(0x00000040) 162 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080) 163 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100) 164 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200) 165 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400) 166 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800) 167 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000) 168 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000) 169 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000) 170 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000) 171 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000) 172 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000) 173 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000) 174 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000) 175 176 /* 177 * CSR8: Interrupt mask register. 178 * Write 1 to mask interrupt. 179 * TBCN_EXPIRE: Beacon timer expired interrupt. 180 * TWAKE_EXPIRE: Wakeup timer expired interrupt. 181 * TATIMW_EXPIRE: Timer of atim window expired interrupt. 182 * TXDONE_TXRING: Tx ring transmit done interrupt. 183 * TXDONE_ATIMRING: Atim ring transmit done interrupt. 184 * TXDONE_PRIORING: Priority ring transmit done interrupt. 185 * RXDONE: Receive done interrupt. 186 * DECRYPTION_DONE: Decryption done interrupt. 187 * ENCRYPTION_DONE: Encryption done interrupt. 188 * UART1_TX_TRESHOLD: UART1 TX reaches threshold. 189 * UART1_RX_TRESHOLD: UART1 RX reaches threshold. 190 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold. 191 * UART1_TX_BUFF_ERROR: UART1 TX buffer error. 192 * UART1_RX_BUFF_ERROR: UART1 RX buffer error. 193 * UART2_TX_TRESHOLD: UART2 TX reaches threshold. 194 * UART2_RX_TRESHOLD: UART2 RX reaches threshold. 195 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold. 196 * UART2_TX_BUFF_ERROR: UART2 TX buffer error. 197 * UART2_RX_BUFF_ERROR: UART2 RX buffer error. 198 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period). 199 */ 200 #define CSR8 0x0020 201 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001) 202 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) 203 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) 204 #define CSR8_TXDONE_TXRING FIELD32(0x00000008) 205 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) 206 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020) 207 #define CSR8_RXDONE FIELD32(0x00000040) 208 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080) 209 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100) 210 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200) 211 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400) 212 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800) 213 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000) 214 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000) 215 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000) 216 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000) 217 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000) 218 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000) 219 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000) 220 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000) 221 222 /* 223 * CSR9: Maximum frame length register. 224 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. 225 */ 226 #define CSR9 0x0024 227 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) 228 229 /* 230 * SECCSR0: WEP control register. 231 * KICK_DECRYPT: Kick decryption engine, self-clear. 232 * ONE_SHOT: 0: ring mode, 1: One shot only mode. 233 * DESC_ADDRESS: Descriptor physical address of frame. 234 */ 235 #define SECCSR0 0x0028 236 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001) 237 #define SECCSR0_ONE_SHOT FIELD32(0x00000002) 238 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc) 239 240 /* 241 * CSR11: Back-off control register. 242 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). 243 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). 244 * SLOT_TIME: Slot time, default is 20us for 802.11b 245 * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD. 246 * LONG_RETRY: Long retry count. 247 * SHORT_RETRY: Short retry count. 248 */ 249 #define CSR11 0x002c 250 #define CSR11_CWMIN FIELD32(0x0000000f) 251 #define CSR11_CWMAX FIELD32(0x000000f0) 252 #define CSR11_SLOT_TIME FIELD32(0x00001f00) 253 #define CSR11_CW_SELECT FIELD32(0x00002000) 254 #define CSR11_LONG_RETRY FIELD32(0x00ff0000) 255 #define CSR11_SHORT_RETRY FIELD32(0xff000000) 256 257 /* 258 * CSR12: Synchronization configuration register 0. 259 * All units in 1/16 TU. 260 * BEACON_INTERVAL: Beacon interval, default is 100 TU. 261 * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU. 262 */ 263 #define CSR12 0x0030 264 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) 265 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) 266 267 /* 268 * CSR13: Synchronization configuration register 1. 269 * All units in 1/16 TU. 270 * ATIMW_DURATION: Atim window duration. 271 * CFP_PERIOD: Cfp period, default is 0 TU. 272 */ 273 #define CSR13 0x0034 274 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) 275 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000) 276 277 /* 278 * CSR14: Synchronization control register. 279 * TSF_COUNT: Enable tsf auto counting. 280 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. 281 * TBCN: Enable tbcn with reload value. 282 * TCFP: Enable tcfp & cfp / cp switching. 283 * TATIMW: Enable tatimw & atim window switching. 284 * BEACON_GEN: Enable beacon generator. 285 * CFP_COUNT_PRELOAD: Cfp count preload value. 286 * TBCM_PRELOAD: Tbcn preload value in units of 64us. 287 */ 288 #define CSR14 0x0038 289 #define CSR14_TSF_COUNT FIELD32(0x00000001) 290 #define CSR14_TSF_SYNC FIELD32(0x00000006) 291 #define CSR14_TBCN FIELD32(0x00000008) 292 #define CSR14_TCFP FIELD32(0x00000010) 293 #define CSR14_TATIMW FIELD32(0x00000020) 294 #define CSR14_BEACON_GEN FIELD32(0x00000040) 295 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) 296 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) 297 298 /* 299 * CSR15: Synchronization status register. 300 * CFP: ASIC is in contention-free period. 301 * ATIMW: ASIC is in ATIM window. 302 * BEACON_SENT: Beacon is send. 303 */ 304 #define CSR15 0x003c 305 #define CSR15_CFP FIELD32(0x00000001) 306 #define CSR15_ATIMW FIELD32(0x00000002) 307 #define CSR15_BEACON_SENT FIELD32(0x00000004) 308 309 /* 310 * CSR16: TSF timer register 0. 311 */ 312 #define CSR16 0x0040 313 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) 314 315 /* 316 * CSR17: TSF timer register 1. 317 */ 318 #define CSR17 0x0044 319 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) 320 321 /* 322 * CSR18: IFS timer register 0. 323 * SIFS: Sifs, default is 10 us. 324 * PIFS: Pifs, default is 30 us. 325 */ 326 #define CSR18 0x0048 327 #define CSR18_SIFS FIELD32(0x000001ff) 328 #define CSR18_PIFS FIELD32(0x001f0000) 329 330 /* 331 * CSR19: IFS timer register 1. 332 * DIFS: Difs, default is 50 us. 333 * EIFS: Eifs, default is 364 us. 334 */ 335 #define CSR19 0x004c 336 #define CSR19_DIFS FIELD32(0x0000ffff) 337 #define CSR19_EIFS FIELD32(0xffff0000) 338 339 /* 340 * CSR20: Wakeup timer register. 341 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. 342 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. 343 * AUTOWAKE: Enable auto wakeup / sleep mechanism. 344 */ 345 #define CSR20 0x0050 346 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) 347 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) 348 #define CSR20_AUTOWAKE FIELD32(0x01000000) 349 350 /* 351 * CSR21: EEPROM control register. 352 * RELOAD: Write 1 to reload eeprom content. 353 * TYPE_93C46: 1: 93c46, 0:93c66. 354 */ 355 #define CSR21 0x0054 356 #define CSR21_RELOAD FIELD32(0x00000001) 357 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) 358 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) 359 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) 360 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) 361 #define CSR21_TYPE_93C46 FIELD32(0x00000020) 362 363 /* 364 * CSR22: CFP control register. 365 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. 366 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. 367 */ 368 #define CSR22 0x0058 369 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) 370 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) 371 372 /* 373 * Transmit related CSRs. 374 * Some values are set in TU, whereas 1 TU == 1024 us. 375 */ 376 377 /* 378 * TXCSR0: TX Control Register. 379 * KICK_TX: Kick tx ring. 380 * KICK_ATIM: Kick atim ring. 381 * KICK_PRIO: Kick priority ring. 382 * ABORT: Abort all transmit related ring operation. 383 */ 384 #define TXCSR0 0x0060 385 #define TXCSR0_KICK_TX FIELD32(0x00000001) 386 #define TXCSR0_KICK_ATIM FIELD32(0x00000002) 387 #define TXCSR0_KICK_PRIO FIELD32(0x00000004) 388 #define TXCSR0_ABORT FIELD32(0x00000008) 389 390 /* 391 * TXCSR1: TX Configuration Register. 392 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. 393 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. 394 * TSF_OFFSET: Insert tsf offset. 395 * AUTORESPONDER: Enable auto responder which include ack & cts. 396 */ 397 #define TXCSR1 0x0064 398 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) 399 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) 400 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) 401 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000) 402 403 /* 404 * TXCSR2: Tx descriptor configuration register. 405 * TXD_SIZE: Tx descriptor size, default is 48. 406 * NUM_TXD: Number of tx entries in ring. 407 * NUM_ATIM: Number of atim entries in ring. 408 * NUM_PRIO: Number of priority entries in ring. 409 */ 410 #define TXCSR2 0x0068 411 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff) 412 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00) 413 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) 414 #define TXCSR2_NUM_PRIO FIELD32(0xff000000) 415 416 /* 417 * TXCSR3: TX Ring Base address register. 418 */ 419 #define TXCSR3 0x006c 420 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) 421 422 /* 423 * TXCSR4: TX Atim Ring Base address register. 424 */ 425 #define TXCSR4 0x0070 426 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) 427 428 /* 429 * TXCSR5: TX Prio Ring Base address register. 430 */ 431 #define TXCSR5 0x0074 432 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) 433 434 /* 435 * TXCSR6: Beacon Base address register. 436 */ 437 #define TXCSR6 0x0078 438 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) 439 440 /* 441 * TXCSR7: Auto responder control register. 442 * AR_POWERMANAGEMENT: Auto responder power management bit. 443 */ 444 #define TXCSR7 0x007c 445 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) 446 447 /* 448 * TXCSR8: CCK Tx BBP register. 449 */ 450 #define TXCSR8 0x0098 451 #define TXCSR8_BBP_ID0 FIELD32(0x0000007f) 452 #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080) 453 #define TXCSR8_BBP_ID1 FIELD32(0x00007f00) 454 #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000) 455 #define TXCSR8_BBP_ID2 FIELD32(0x007f0000) 456 #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000) 457 #define TXCSR8_BBP_ID3 FIELD32(0x7f000000) 458 #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000) 459 460 /* 461 * TXCSR9: OFDM TX BBP registers 462 * OFDM_SIGNAL: BBP rate field address for OFDM. 463 * OFDM_SERVICE: BBP service field address for OFDM. 464 * OFDM_LENGTH_LOW: BBP length low byte address for OFDM. 465 * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM. 466 */ 467 #define TXCSR9 0x0094 468 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff) 469 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00) 470 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000) 471 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000) 472 473 /* 474 * Receive related CSRs. 475 * Some values are set in TU, whereas 1 TU == 1024 us. 476 */ 477 478 /* 479 * RXCSR0: RX Control Register. 480 * DISABLE_RX: Disable rx engine. 481 * DROP_CRC: Drop crc error. 482 * DROP_PHYSICAL: Drop physical error. 483 * DROP_CONTROL: Drop control frame. 484 * DROP_NOT_TO_ME: Drop not to me unicast frame. 485 * DROP_TODS: Drop frame tods bit is true. 486 * DROP_VERSION_ERROR: Drop version error frame. 487 * PASS_CRC: Pass all packets with crc attached. 488 * PASS_CRC: Pass all packets with crc attached. 489 * PASS_PLCP: Pass all packets with 4 bytes PLCP attached. 490 * DROP_MCAST: Drop multicast frames. 491 * DROP_BCAST: Drop broadcast frames. 492 * ENABLE_QOS: Accept QOS data frame and parse QOS field. 493 */ 494 #define RXCSR0 0x0080 495 #define RXCSR0_DISABLE_RX FIELD32(0x00000001) 496 #define RXCSR0_DROP_CRC FIELD32(0x00000002) 497 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) 498 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008) 499 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) 500 #define RXCSR0_DROP_TODS FIELD32(0x00000020) 501 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) 502 #define RXCSR0_PASS_CRC FIELD32(0x00000080) 503 #define RXCSR0_PASS_PLCP FIELD32(0x00000100) 504 #define RXCSR0_DROP_MCAST FIELD32(0x00000200) 505 #define RXCSR0_DROP_BCAST FIELD32(0x00000400) 506 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800) 507 508 /* 509 * RXCSR1: RX descriptor configuration register. 510 * RXD_SIZE: Rx descriptor size, default is 32b. 511 * NUM_RXD: Number of rx entries in ring. 512 */ 513 #define RXCSR1 0x0084 514 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff) 515 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00) 516 517 /* 518 * RXCSR2: RX Ring base address register. 519 */ 520 #define RXCSR2 0x0088 521 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) 522 523 /* 524 * RXCSR3: BBP ID register for Rx operation. 525 * BBP_ID#: BBP register # id. 526 * BBP_ID#_VALID: BBP register # id is valid or not. 527 */ 528 #define RXCSR3 0x0090 529 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f) 530 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) 531 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00) 532 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) 533 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000) 534 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) 535 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000) 536 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) 537 538 /* 539 * ARCSR1: Auto Responder PLCP config register 1. 540 * AR_BBP_DATA#: Auto responder BBP register # data. 541 * AR_BBP_ID#: Auto responder BBP register # Id. 542 */ 543 #define ARCSR1 0x009c 544 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) 545 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) 546 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) 547 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) 548 549 /* 550 * Miscellaneous Registers. 551 * Some values are set in TU, whereas 1 TU == 1024 us. 552 553 */ 554 555 /* 556 * PCICSR: PCI control register. 557 * BIG_ENDIAN: 1: big endian, 0: little endian. 558 * RX_TRESHOLD: Rx threshold in dw to start pci access 559 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. 560 * TX_TRESHOLD: Tx threshold in dw to start pci access 561 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. 562 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. 563 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. 564 * READ_MULTIPLE: Enable memory read multiple. 565 * WRITE_INVALID: Enable memory write & invalid. 566 */ 567 #define PCICSR 0x008c 568 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001) 569 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006) 570 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018) 571 #define PCICSR_BURST_LENTH FIELD32(0x00000060) 572 #define PCICSR_ENABLE_CLK FIELD32(0x00000080) 573 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100) 574 #define PCICSR_WRITE_INVALID FIELD32(0x00000200) 575 576 /* 577 * CNT0: FCS error count. 578 * FCS_ERROR: FCS error count, cleared when read. 579 */ 580 #define CNT0 0x00a0 581 #define CNT0_FCS_ERROR FIELD32(0x0000ffff) 582 583 /* 584 * Statistic Register. 585 * CNT1: PLCP error count. 586 * CNT2: Long error count. 587 */ 588 #define TIMECSR2 0x00a8 589 #define CNT1 0x00ac 590 #define CNT2 0x00b0 591 #define TIMECSR3 0x00b4 592 593 /* 594 * CNT3: CCA false alarm count. 595 */ 596 #define CNT3 0x00b8 597 #define CNT3_FALSE_CCA FIELD32(0x0000ffff) 598 599 /* 600 * Statistic Register. 601 * CNT4: Rx FIFO overflow count. 602 * CNT5: Tx FIFO underrun count. 603 */ 604 #define CNT4 0x00bc 605 #define CNT5 0x00c0 606 607 /* 608 * Baseband Control Register. 609 */ 610 611 /* 612 * PWRCSR0: Power mode configuration register. 613 */ 614 #define PWRCSR0 0x00c4 615 616 /* 617 * Power state transition time registers. 618 */ 619 #define PSCSR0 0x00c8 620 #define PSCSR1 0x00cc 621 #define PSCSR2 0x00d0 622 #define PSCSR3 0x00d4 623 624 /* 625 * PWRCSR1: Manual power control / status register. 626 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. 627 * SET_STATE: Set state. Write 1 to trigger, self cleared. 628 * BBP_DESIRE_STATE: BBP desired state. 629 * RF_DESIRE_STATE: RF desired state. 630 * BBP_CURR_STATE: BBP current state. 631 * RF_CURR_STATE: RF current state. 632 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. 633 */ 634 #define PWRCSR1 0x00d8 635 #define PWRCSR1_SET_STATE FIELD32(0x00000001) 636 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) 637 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) 638 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) 639 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) 640 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) 641 642 /* 643 * TIMECSR: Timer control register. 644 * US_COUNT: 1 us timer count in units of clock cycles. 645 * US_64_COUNT: 64 us timer count in units of 1 us timer. 646 * BEACON_EXPECT: Beacon expect window. 647 */ 648 #define TIMECSR 0x00dc 649 #define TIMECSR_US_COUNT FIELD32(0x000000ff) 650 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) 651 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) 652 653 /* 654 * MACCSR0: MAC configuration register 0. 655 */ 656 #define MACCSR0 0x00e0 657 658 /* 659 * MACCSR1: MAC configuration register 1. 660 * KICK_RX: Kick one-shot rx in one-shot rx mode. 661 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. 662 * BBPRX_RESET_MODE: Ralink bbp rx reset mode. 663 * AUTO_TXBBP: Auto tx logic access bbp control register. 664 * AUTO_RXBBP: Auto rx logic access bbp control register. 665 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. 666 * INTERSIL_IF: Intersil if calibration pin. 667 */ 668 #define MACCSR1 0x00e4 669 #define MACCSR1_KICK_RX FIELD32(0x00000001) 670 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) 671 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) 672 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) 673 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) 674 #define MACCSR1_LOOPBACK FIELD32(0x00000060) 675 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080) 676 677 /* 678 * RALINKCSR: Ralink Rx auto-reset BBCR. 679 * AR_BBP_DATA#: Auto reset BBP register # data. 680 * AR_BBP_ID#: Auto reset BBP register # id. 681 */ 682 #define RALINKCSR 0x00e8 683 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) 684 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00) 685 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000) 686 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) 687 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000) 688 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000) 689 690 /* 691 * BCNCSR: Beacon interval control register. 692 * CHANGE: Write one to change beacon interval. 693 * DELTATIME: The delta time value. 694 * NUM_BEACON: Number of beacon according to mode. 695 * MODE: Please refer to asic specs. 696 * PLUS: Plus or minus delta time value. 697 */ 698 #define BCNCSR 0x00ec 699 #define BCNCSR_CHANGE FIELD32(0x00000001) 700 #define BCNCSR_DELTATIME FIELD32(0x0000001e) 701 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) 702 #define BCNCSR_MODE FIELD32(0x00006000) 703 #define BCNCSR_PLUS FIELD32(0x00008000) 704 705 /* 706 * BBP / RF / IF Control Register. 707 */ 708 709 /* 710 * BBPCSR: BBP serial control register. 711 * VALUE: Register value to program into BBP. 712 * REGNUM: Selected BBP register. 713 * BUSY: 1: asic is busy execute BBP programming. 714 * WRITE_CONTROL: 1: write BBP, 0: read BBP. 715 */ 716 #define BBPCSR 0x00f0 717 #define BBPCSR_VALUE FIELD32(0x000000ff) 718 #define BBPCSR_REGNUM FIELD32(0x00007f00) 719 #define BBPCSR_BUSY FIELD32(0x00008000) 720 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) 721 722 /* 723 * RFCSR: RF serial control register. 724 * VALUE: Register value + id to program into rf/if. 725 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). 726 * IF_SELECT: Chip to program: 0: rf, 1: if. 727 * PLL_LD: Rf pll_ld status. 728 * BUSY: 1: asic is busy execute rf programming. 729 */ 730 #define RFCSR 0x00f4 731 #define RFCSR_VALUE FIELD32(0x00ffffff) 732 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) 733 #define RFCSR_IF_SELECT FIELD32(0x20000000) 734 #define RFCSR_PLL_LD FIELD32(0x40000000) 735 #define RFCSR_BUSY FIELD32(0x80000000) 736 737 /* 738 * LEDCSR: LED control register. 739 * ON_PERIOD: On period, default 70ms. 740 * OFF_PERIOD: Off period, default 30ms. 741 * LINK: 0: linkoff, 1: linkup. 742 * ACTIVITY: 0: idle, 1: active. 743 * LINK_POLARITY: 0: active low, 1: active high. 744 * ACTIVITY_POLARITY: 0: active low, 1: active high. 745 * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF. 746 */ 747 #define LEDCSR 0x00f8 748 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff) 749 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) 750 #define LEDCSR_LINK FIELD32(0x00010000) 751 #define LEDCSR_ACTIVITY FIELD32(0x00020000) 752 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000) 753 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000) 754 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000) 755 756 /* 757 * SECCSR3: AES control register. 758 */ 759 #define SECCSR3 0x00fc 760 761 /* 762 * ASIC pointer information. 763 * RXPTR: Current RX ring address. 764 * TXPTR: Current Tx ring address. 765 * PRIPTR: Current Priority ring address. 766 * ATIMPTR: Current ATIM ring address. 767 */ 768 #define RXPTR 0x0100 769 #define TXPTR 0x0104 770 #define PRIPTR 0x0108 771 #define ATIMPTR 0x010c 772 773 /* 774 * TXACKCSR0: TX ACK timeout. 775 */ 776 #define TXACKCSR0 0x0110 777 778 /* 779 * ACK timeout count registers. 780 * ACKCNT0: TX ACK timeout count. 781 * ACKCNT1: RX ACK timeout count. 782 */ 783 #define ACKCNT0 0x0114 784 #define ACKCNT1 0x0118 785 786 /* 787 * GPIO and others. 788 */ 789 790 /* 791 * GPIOCSR: GPIO control register. 792 */ 793 #define GPIOCSR 0x0120 794 #define GPIOCSR_BIT0 FIELD32(0x00000001) 795 #define GPIOCSR_BIT1 FIELD32(0x00000002) 796 #define GPIOCSR_BIT2 FIELD32(0x00000004) 797 #define GPIOCSR_BIT3 FIELD32(0x00000008) 798 #define GPIOCSR_BIT4 FIELD32(0x00000010) 799 #define GPIOCSR_BIT5 FIELD32(0x00000020) 800 #define GPIOCSR_BIT6 FIELD32(0x00000040) 801 #define GPIOCSR_BIT7 FIELD32(0x00000080) 802 #define GPIOCSR_DIR0 FIELD32(0x00000100) 803 #define GPIOCSR_DIR1 FIELD32(0x00000200) 804 #define GPIOCSR_DIR2 FIELD32(0x00000400) 805 #define GPIOCSR_DIR3 FIELD32(0x00000800) 806 #define GPIOCSR_DIR4 FIELD32(0x00001000) 807 #define GPIOCSR_DIR5 FIELD32(0x00002000) 808 #define GPIOCSR_DIR6 FIELD32(0x00004000) 809 #define GPIOCSR_DIR7 FIELD32(0x00008000) 810 811 /* 812 * FIFO pointer registers. 813 * FIFOCSR0: TX FIFO pointer. 814 * FIFOCSR1: RX FIFO pointer. 815 */ 816 #define FIFOCSR0 0x0128 817 #define FIFOCSR1 0x012c 818 819 /* 820 * BCNCSR1: Tx BEACON offset time control register. 821 * PRELOAD: Beacon timer offset in units of usec. 822 * BEACON_CWMIN: 2^CwMin. 823 */ 824 #define BCNCSR1 0x0130 825 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff) 826 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000) 827 828 /* 829 * MACCSR2: TX_PE to RX_PE turn-around time control register 830 * DELAY: RX_PE low width, in units of pci clock cycle. 831 */ 832 #define MACCSR2 0x0134 833 #define MACCSR2_DELAY FIELD32(0x000000ff) 834 835 /* 836 * TESTCSR: TEST mode selection register. 837 */ 838 #define TESTCSR 0x0138 839 840 /* 841 * ARCSR2: 1 Mbps ACK/CTS PLCP. 842 */ 843 #define ARCSR2 0x013c 844 #define ARCSR2_SIGNAL FIELD32(0x000000ff) 845 #define ARCSR2_SERVICE FIELD32(0x0000ff00) 846 #define ARCSR2_LENGTH FIELD32(0xffff0000) 847 848 /* 849 * ARCSR3: 2 Mbps ACK/CTS PLCP. 850 */ 851 #define ARCSR3 0x0140 852 #define ARCSR3_SIGNAL FIELD32(0x000000ff) 853 #define ARCSR3_SERVICE FIELD32(0x0000ff00) 854 #define ARCSR3_LENGTH FIELD32(0xffff0000) 855 856 /* 857 * ARCSR4: 5.5 Mbps ACK/CTS PLCP. 858 */ 859 #define ARCSR4 0x0144 860 #define ARCSR4_SIGNAL FIELD32(0x000000ff) 861 #define ARCSR4_SERVICE FIELD32(0x0000ff00) 862 #define ARCSR4_LENGTH FIELD32(0xffff0000) 863 864 /* 865 * ARCSR5: 11 Mbps ACK/CTS PLCP. 866 */ 867 #define ARCSR5 0x0148 868 #define ARCSR5_SIGNAL FIELD32(0x000000ff) 869 #define ARCSR5_SERVICE FIELD32(0x0000ff00) 870 #define ARCSR5_LENGTH FIELD32(0xffff0000) 871 872 /* 873 * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps. 874 */ 875 #define ARTCSR0 0x014c 876 #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff) 877 #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00) 878 #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000) 879 #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000) 880 881 882 /* 883 * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. 884 */ 885 #define ARTCSR1 0x0150 886 #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff) 887 #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00) 888 #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000) 889 #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000) 890 891 /* 892 * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. 893 */ 894 #define ARTCSR2 0x0154 895 #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff) 896 #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00) 897 #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000) 898 #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000) 899 900 /* 901 * SECCSR1: WEP control register. 902 * KICK_ENCRYPT: Kick encryption engine, self-clear. 903 * ONE_SHOT: 0: ring mode, 1: One shot only mode. 904 * DESC_ADDRESS: Descriptor physical address of frame. 905 */ 906 #define SECCSR1 0x0158 907 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001) 908 #define SECCSR1_ONE_SHOT FIELD32(0x00000002) 909 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc) 910 911 /* 912 * BBPCSR1: BBP TX configuration. 913 */ 914 #define BBPCSR1 0x015c 915 #define BBPCSR1_CCK FIELD32(0x00000003) 916 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004) 917 #define BBPCSR1_OFDM FIELD32(0x00030000) 918 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000) 919 920 /* 921 * Dual band configuration registers. 922 * DBANDCSR0: Dual band configuration register 0. 923 * DBANDCSR1: Dual band configuration register 1. 924 */ 925 #define DBANDCSR0 0x0160 926 #define DBANDCSR1 0x0164 927 928 /* 929 * BBPPCSR: BBP Pin control register. 930 */ 931 #define BBPPCSR 0x0168 932 933 /* 934 * MAC special debug mode selection registers. 935 * DBGSEL0: MAC special debug mode selection register 0. 936 * DBGSEL1: MAC special debug mode selection register 1. 937 */ 938 #define DBGSEL0 0x016c 939 #define DBGSEL1 0x0170 940 941 /* 942 * BISTCSR: BBP BIST register. 943 */ 944 #define BISTCSR 0x0174 945 946 /* 947 * Multicast filter registers. 948 * MCAST0: Multicast filter register 0. 949 * MCAST1: Multicast filter register 1. 950 */ 951 #define MCAST0 0x0178 952 #define MCAST1 0x017c 953 954 /* 955 * UART registers. 956 * UARTCSR0: UART1 TX register. 957 * UARTCSR1: UART1 RX register. 958 * UARTCSR3: UART1 frame control register. 959 * UARTCSR4: UART1 buffer control register. 960 * UART2CSR0: UART2 TX register. 961 * UART2CSR1: UART2 RX register. 962 * UART2CSR3: UART2 frame control register. 963 * UART2CSR4: UART2 buffer control register. 964 */ 965 #define UARTCSR0 0x0180 966 #define UARTCSR1 0x0184 967 #define UARTCSR3 0x0188 968 #define UARTCSR4 0x018c 969 #define UART2CSR0 0x0190 970 #define UART2CSR1 0x0194 971 #define UART2CSR3 0x0198 972 #define UART2CSR4 0x019c 973 974 /* 975 * BBP registers. 976 * The wordsize of the BBP is 8 bits. 977 */ 978 979 /* 980 * R2: TX antenna control 981 */ 982 #define BBP_R2_TX_ANTENNA FIELD8(0x03) 983 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04) 984 985 /* 986 * R14: RX antenna control 987 */ 988 #define BBP_R14_RX_ANTENNA FIELD8(0x03) 989 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04) 990 991 /* 992 * BBP_R70 993 */ 994 #define BBP_R70_JAPAN_FILTER FIELD8(0x08) 995 996 /* 997 * RF registers 998 */ 999 1000 /* 1001 * RF 1 1002 */ 1003 #define RF1_TUNER FIELD32(0x00020000) 1004 1005 /* 1006 * RF 3 1007 */ 1008 #define RF3_TUNER FIELD32(0x00000100) 1009 #define RF3_TXPOWER FIELD32(0x00003e00) 1010 1011 /* 1012 * EEPROM content. 1013 * The wordsize of the EEPROM is 16 bits. 1014 */ 1015 1016 /* 1017 * HW MAC address. 1018 */ 1019 #define EEPROM_MAC_ADDR_0 0x0002 1020 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 1021 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 1022 #define EEPROM_MAC_ADDR1 0x0003 1023 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 1024 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 1025 #define EEPROM_MAC_ADDR_2 0x0004 1026 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 1027 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 1028 1029 /* 1030 * EEPROM antenna. 1031 * ANTENNA_NUM: Number of antenna's. 1032 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 1033 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 1034 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. 1035 * DYN_TXAGC: Dynamic TX AGC control. 1036 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. 1037 * RF_TYPE: Rf_type of this adapter. 1038 */ 1039 #define EEPROM_ANTENNA 0x10 1040 #define EEPROM_ANTENNA_NUM FIELD16(0x0003) 1041 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) 1042 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) 1043 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0) 1044 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) 1045 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) 1046 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) 1047 1048 /* 1049 * EEPROM NIC config. 1050 * CARDBUS_ACCEL: 0: enable, 1: disable. 1051 * DYN_BBP_TUNE: 0: enable, 1: disable. 1052 * CCK_TX_POWER: CCK TX power compensation. 1053 */ 1054 #define EEPROM_NIC 0x11 1055 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001) 1056 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002) 1057 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c) 1058 1059 /* 1060 * EEPROM geography. 1061 * GEO: Default geography setting for device. 1062 */ 1063 #define EEPROM_GEOGRAPHY 0x12 1064 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00) 1065 1066 /* 1067 * EEPROM BBP. 1068 */ 1069 #define EEPROM_BBP_START 0x13 1070 #define EEPROM_BBP_SIZE 16 1071 #define EEPROM_BBP_VALUE FIELD16(0x00ff) 1072 #define EEPROM_BBP_REG_ID FIELD16(0xff00) 1073 1074 /* 1075 * EEPROM TXPOWER 1076 */ 1077 #define EEPROM_TXPOWER_START 0x23 1078 #define EEPROM_TXPOWER_SIZE 7 1079 #define EEPROM_TXPOWER_1 FIELD16(0x00ff) 1080 #define EEPROM_TXPOWER_2 FIELD16(0xff00) 1081 1082 /* 1083 * RSSI <-> dBm offset calibration 1084 */ 1085 #define EEPROM_CALIBRATE_OFFSET 0x3e 1086 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff) 1087 1088 /* 1089 * DMA descriptor defines. 1090 */ 1091 #define TXD_DESC_SIZE (11 * sizeof(__le32)) 1092 #define RXD_DESC_SIZE (11 * sizeof(__le32)) 1093 1094 /* 1095 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. 1096 */ 1097 1098 /* 1099 * Word0 1100 */ 1101 #define TXD_W0_OWNER_NIC FIELD32(0x00000001) 1102 #define TXD_W0_VALID FIELD32(0x00000002) 1103 #define TXD_W0_RESULT FIELD32(0x0000001c) 1104 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) 1105 #define TXD_W0_MORE_FRAG FIELD32(0x00000100) 1106 #define TXD_W0_ACK FIELD32(0x00000200) 1107 #define TXD_W0_TIMESTAMP FIELD32(0x00000400) 1108 #define TXD_W0_OFDM FIELD32(0x00000800) 1109 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000) 1110 #define TXD_W0_IFS FIELD32(0x00006000) 1111 #define TXD_W0_RETRY_MODE FIELD32(0x00008000) 1112 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) 1113 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000) 1114 1115 /* 1116 * Word1 1117 */ 1118 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) 1119 1120 /* 1121 * Word2 1122 */ 1123 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f) 1124 #define TXD_W2_AIFS FIELD32(0x000000c0) 1125 #define TXD_W2_CWMIN FIELD32(0x00000f00) 1126 #define TXD_W2_CWMAX FIELD32(0x0000f000) 1127 1128 /* 1129 * Word3: PLCP information 1130 */ 1131 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) 1132 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00) 1133 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000) 1134 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000) 1135 1136 /* 1137 * Word4 1138 */ 1139 #define TXD_W4_IV FIELD32(0xffffffff) 1140 1141 /* 1142 * Word5 1143 */ 1144 #define TXD_W5_EIV FIELD32(0xffffffff) 1145 1146 /* 1147 * Word6-9: Key 1148 */ 1149 #define TXD_W6_KEY FIELD32(0xffffffff) 1150 #define TXD_W7_KEY FIELD32(0xffffffff) 1151 #define TXD_W8_KEY FIELD32(0xffffffff) 1152 #define TXD_W9_KEY FIELD32(0xffffffff) 1153 1154 /* 1155 * Word10 1156 */ 1157 #define TXD_W10_RTS FIELD32(0x00000001) 1158 #define TXD_W10_TX_RATE FIELD32(0x000000fe) 1159 1160 /* 1161 * RX descriptor format for RX Ring. 1162 */ 1163 1164 /* 1165 * Word0 1166 */ 1167 #define RXD_W0_OWNER_NIC FIELD32(0x00000001) 1168 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) 1169 #define RXD_W0_MULTICAST FIELD32(0x00000004) 1170 #define RXD_W0_BROADCAST FIELD32(0x00000008) 1171 #define RXD_W0_MY_BSS FIELD32(0x00000010) 1172 #define RXD_W0_CRC_ERROR FIELD32(0x00000020) 1173 #define RXD_W0_OFDM FIELD32(0x00000040) 1174 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) 1175 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100) 1176 #define RXD_W0_ICV_ERROR FIELD32(0x00000200) 1177 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00) 1178 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) 1179 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000) 1180 1181 /* 1182 * Word1 1183 */ 1184 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) 1185 1186 /* 1187 * Word2 1188 */ 1189 #define RXD_W2_SIGNAL FIELD32(0x000000ff) 1190 #define RXD_W2_RSSI FIELD32(0x0000ff00) 1191 #define RXD_W2_TA FIELD32(0xffff0000) 1192 1193 /* 1194 * Word3 1195 */ 1196 #define RXD_W3_TA FIELD32(0xffffffff) 1197 1198 /* 1199 * Word4 1200 */ 1201 #define RXD_W4_IV FIELD32(0xffffffff) 1202 1203 /* 1204 * Word5 1205 */ 1206 #define RXD_W5_EIV FIELD32(0xffffffff) 1207 1208 /* 1209 * Word6-9: Key 1210 */ 1211 #define RXD_W6_KEY FIELD32(0xffffffff) 1212 #define RXD_W7_KEY FIELD32(0xffffffff) 1213 #define RXD_W8_KEY FIELD32(0xffffffff) 1214 #define RXD_W9_KEY FIELD32(0xffffffff) 1215 1216 /* 1217 * Word10 1218 */ 1219 #define RXD_W10_DROP FIELD32(0x00000001) 1220 1221 /* 1222 * Macros for converting txpower from EEPROM to mac80211 value 1223 * and from mac80211 value to register value. 1224 */ 1225 #define MIN_TXPOWER 0 1226 #define MAX_TXPOWER 31 1227 #define DEFAULT_TXPOWER 24 1228 1229 #define TXPOWER_FROM_DEV(__txpower) \ 1230 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 1231 1232 #define TXPOWER_TO_DEV(__txpower) \ 1233 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER) 1234 1235 #endif /* RT2500PCI_H */ 1236