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Searched refs:RTSX_WRITE_REG (Results 1 – 8 of 8) sorted by relevance

/linux-3.4.99/drivers/staging/rts_pstor/
Drtsx_chip.c135 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, in rtsx_pre_handle_sdio_old()
138 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, FPGA_SD_PULL_CTL_EN); in rtsx_pre_handle_sdio_old()
140 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD); in rtsx_pre_handle_sdio_old()
143 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01); in rtsx_pre_handle_sdio_old()
145 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL); in rtsx_pre_handle_sdio_old()
197 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00); in rtsx_pre_handle_sdio_new()
199 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00); in rtsx_pre_handle_sdio_new()
201 RTSX_WRITE_REG(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, 0); in rtsx_pre_handle_sdio_new()
203 RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp); in rtsx_pre_handle_sdio_new()
215 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0); in rtsx_pre_handle_sdio_new()
[all …]
Dsd.c546 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST, in sd_set_sample_push_timing()
548 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing()
549 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF, in sd_set_sample_push_timing()
551 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing()
553 RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST, in sd_set_sample_push_timing()
555 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in sd_set_sample_push_timing()
556 RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF, in sd_set_sample_push_timing()
558 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in sd_set_sample_push_timing()
559 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT, in sd_set_sample_push_timing()
561 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, in sd_set_sample_push_timing()
[all …]
Dspi.c42 RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF, in spi_init()
44 RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF); in spi_init()
54 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, (u8)(spi->clk_div >> 8)); in spi_set_init_para()
55 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, (u8)(spi->clk_div)); in spi_set_init_para()
65 RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); in spi_set_init_para()
66 RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); in spi_set_init_para()
202 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); in spi_init_eeprom()
203 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); in spi_init_eeprom()
213 RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN); in spi_init_eeprom()
214 RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN); in spi_init_eeprom()
[all …]
Drtsx_card.c789 RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0); in switch_ssc_clock()
886 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); in switch_normal_clock()
888 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in switch_normal_clock()
889 RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, 0); in switch_normal_clock()
891 RTSX_WRITE_REG(chip, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); in switch_normal_clock()
892 RTSX_WRITE_REG(chip, CLK_SEL, 0xFF, sel); in switch_normal_clock()
896 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET); in switch_normal_clock()
897 RTSX_WRITE_REG(chip, SD_VPCLK1_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET); in switch_normal_clock()
900 RTSX_WRITE_REG(chip, CLK_CTL, 0xFF, 0); in switch_normal_clock()
941 RTSX_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en); in enable_card_clock()
[all …]
Dxd.c345 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); in xd_pull_ctl_disable()
346 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55); in xd_pull_ctl_disable()
347 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5); in xd_pull_ctl_disable()
348 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55); in xd_pull_ctl_disable()
349 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55); in xd_pull_ctl_disable()
350 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15); in xd_pull_ctl_disable()
352 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, in xd_pull_ctl_disable()
354 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, in xd_pull_ctl_disable()
356 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, in xd_pull_ctl_disable()
358 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, in xd_pull_ctl_disable()
[all …]
Dms.c399 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55); in ms_pull_ctl_disable()
400 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55); in ms_pull_ctl_disable()
401 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15); in ms_pull_ctl_disable()
403 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, in ms_pull_ctl_disable()
405 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, in ms_pull_ctl_disable()
407 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, in ms_pull_ctl_disable()
409 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, in ms_pull_ctl_disable()
411 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, in ms_pull_ctl_disable()
413 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, in ms_pull_ctl_disable()
417 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55); in ms_pull_ctl_disable()
[all …]
Drtsx_card.h1064 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0x0F, 0x0F); in card_power_off_all()
Drtsx_chip.h973 #define RTSX_WRITE_REG(chip, addr, mask, data) \ macro