Searched refs:RF90_PATH_D (Results 1 – 17 of 17) sorted by relevance
71 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) in rtl8192_phy_CheckIsLegalRFPath()585 …priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x8… in rtl8192_InitBBRFRegDef()591 …priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8… in rtl8192_InitBBRFRegDef()597 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C in rtl8192_InitBBRFRegDef()603 …priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86… in rtl8192_InitBBRFRegDef()609 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; in rtl8192_InitBBRFRegDef()615 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; in rtl8192_InitBBRFRegDef()621 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage in rtl8192_InitBBRFRegDef()627 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 in rtl8192_InitBBRFRegDef()633 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 in rtl8192_InitBBRFRegDef()[all …]
143 case RF90_PATH_D: in phy_RF8256_Config_ParaFile()200 case RF90_PATH_D: in phy_RF8256_Config_ParaFile()219 case RF90_PATH_D: in phy_RF8256_Config_ParaFile()
48 RF90_PATH_D = 3, //Radio Path D enumerator
75 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) in rtl8192_phy_CheckIsLegalRFPath()410 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl8192_InitBBRFRegDef()415 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; in rtl8192_InitBBRFRegDef()420 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; in rtl8192_InitBBRFRegDef()425 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; in rtl8192_InitBBRFRegDef()430 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; in rtl8192_InitBBRFRegDef()435 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; in rtl8192_InitBBRFRegDef()440 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()445 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; in rtl8192_InitBBRFRegDef()450 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; in rtl8192_InitBBRFRegDef()[all …]
123 case RF90_PATH_D: in phy_RF8256_Config_ParaFile()197 case RF90_PATH_D: in phy_RF8256_Config_ParaFile()220 case RF90_PATH_D: in phy_RF8256_Config_ParaFile()
64 RF90_PATH_D = 3, enumerator
610 (enum rf90_radio_path)RF90_PATH_D, n, in proc_get_reg_rf_d()
713 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92s_phy_init_register_definition()719 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92s_phy_init_register_definition()725 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()731 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; in _rtl92s_phy_init_register_definition()740 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = in _rtl92s_phy_init_register_definition()747 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92s_phy_init_register_definition()753 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92s_phy_init_register_definition()759 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; in _rtl92s_phy_init_register_definition()765 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; in _rtl92s_phy_init_register_definition()774 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control = in _rtl92s_phy_init_register_definition()[all …]
451 case RF90_PATH_D: in rtl92s_phy_rf6052_config()483 case RF90_PATH_D: in rtl92s_phy_rf6052_config()495 case RF90_PATH_D: in rtl92s_phy_rf6052_config()
343 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()348 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()364 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()369 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()383 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control = in _rtl92c_phy_init_bb_rf_register_definition()389 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()394 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()402 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance = in _rtl92c_phy_init_bb_rf_register_definition()408 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()416 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance = in _rtl92c_phy_init_bb_rf_register_definition()[all …]
459 case RF90_PATH_D: in _rtl92ce_phy_rf6052_config_parafile()489 case RF90_PATH_D: in _rtl92ce_phy_rf6052_config_parafile()500 case RF90_PATH_D: in _rtl92ce_phy_rf6052_config_parafile()
352 case RF90_PATH_D: in rtl92c_phy_config_rf_with_headerfile()
445 case RF90_PATH_D: in _rtl92c_phy_rf6052_config_parafile()470 case RF90_PATH_D: in _rtl92c_phy_rf6052_config_parafile()480 case RF90_PATH_D: in _rtl92c_phy_rf6052_config_parafile()
339 case RF90_PATH_D: in rtl92cu_phy_config_rf_with_headerfile()
554 case RF90_PATH_D: in rtl92d_phy_rf6052_config()589 case RF90_PATH_D: in rtl92d_phy_rf6052_config()599 case RF90_PATH_D: in rtl92d_phy_rf6052_config()
420 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92d_phy_init_bb_rf_register_definition()429 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92d_phy_init_bb_rf_register_definition()455 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl92d_phy_init_bb_rf_register_definition()465 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92d_phy_init_bb_rf_register_definition()487 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control = in _rtl92d_phy_init_bb_rf_register_definition()494 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92d_phy_init_bb_rf_register_definition()500 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92d_phy_init_bb_rf_register_definition()509 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance = in _rtl92d_phy_init_bb_rf_register_definition()516 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92d_phy_init_bb_rf_register_definition()525 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance = in _rtl92d_phy_init_bb_rf_register_definition()[all …]
112 RF90_PATH_D = 3, enumerator