1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Support functions for the OMAP internal DMA channels.
17 *
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 *
26 */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <mach/hardware.h>
40 #include <plat/dma.h>
41
42 #include <plat/tc.h>
43
44 #undef DEBUG
45
46 #ifndef CONFIG_ARCH_OMAP1
47 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
48 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
49 };
50
51 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
52 #endif
53
54 #define OMAP_DMA_ACTIVE 0x01
55 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
56
57 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
58
59 static struct omap_system_dma_plat_info *p;
60 static struct omap_dma_dev_attr *d;
61
62 static int enable_1510_mode;
63 static u32 errata;
64
65 static struct omap_dma_global_context_registers {
66 u32 dma_irqenable_l0;
67 u32 dma_ocp_sysconfig;
68 u32 dma_gcr;
69 } omap_dma_global_context;
70
71 struct dma_link_info {
72 int *linked_dmach_q;
73 int no_of_lchs_linked;
74
75 int q_count;
76 int q_tail;
77 int q_head;
78
79 int chain_state;
80 int chain_mode;
81
82 };
83
84 static struct dma_link_info *dma_linked_lch;
85
86 #ifndef CONFIG_ARCH_OMAP1
87
88 /* Chain handling macros */
89 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
90 do { \
91 dma_linked_lch[chain_id].q_head = \
92 dma_linked_lch[chain_id].q_tail = \
93 dma_linked_lch[chain_id].q_count = 0; \
94 } while (0)
95 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
96 (dma_linked_lch[chain_id].no_of_lchs_linked == \
97 dma_linked_lch[chain_id].q_count)
98 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
99 do { \
100 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
101 dma_linked_lch[chain_id].q_count) \
102 } while (0)
103 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
104 (0 == dma_linked_lch[chain_id].q_count)
105 #define __OMAP_DMA_CHAIN_INCQ(end) \
106 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
107 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
108 do { \
109 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
110 dma_linked_lch[chain_id].q_count--; \
111 } while (0)
112
113 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
114 do { \
115 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
116 dma_linked_lch[chain_id].q_count++; \
117 } while (0)
118 #endif
119
120 static int dma_lch_count;
121 static int dma_chan_count;
122 static int omap_dma_reserve_channels;
123
124 static spinlock_t dma_chan_lock;
125 static struct omap_dma_lch *dma_chan;
126
127 static inline void disable_lnk(int lch);
128 static void omap_disable_channel_irq(int lch);
129 static inline void omap_enable_channel_irq(int lch);
130
131 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
132 __func__);
133
134 #ifdef CONFIG_ARCH_OMAP15XX
135 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
omap_dma_in_1510_mode(void)136 static int omap_dma_in_1510_mode(void)
137 {
138 return enable_1510_mode;
139 }
140 #else
141 #define omap_dma_in_1510_mode() 0
142 #endif
143
144 #ifdef CONFIG_ARCH_OMAP1
get_gdma_dev(int req)145 static inline int get_gdma_dev(int req)
146 {
147 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
148 int shift = ((req - 1) % 5) * 6;
149
150 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
151 }
152
set_gdma_dev(int req,int dev)153 static inline void set_gdma_dev(int req, int dev)
154 {
155 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
156 int shift = ((req - 1) % 5) * 6;
157 u32 l;
158
159 l = omap_readl(reg);
160 l &= ~(0x3f << shift);
161 l |= (dev - 1) << shift;
162 omap_writel(l, reg);
163 }
164 #else
165 #define set_gdma_dev(req, dev) do {} while (0)
166 #define omap_readl(reg) 0
167 #define omap_writel(val, reg) do {} while (0)
168 #endif
169
omap_set_dma_priority(int lch,int dst_port,int priority)170 void omap_set_dma_priority(int lch, int dst_port, int priority)
171 {
172 unsigned long reg;
173 u32 l;
174
175 if (cpu_class_is_omap1()) {
176 switch (dst_port) {
177 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
178 reg = OMAP_TC_OCPT1_PRIOR;
179 break;
180 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
181 reg = OMAP_TC_OCPT2_PRIOR;
182 break;
183 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
184 reg = OMAP_TC_EMIFF_PRIOR;
185 break;
186 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
187 reg = OMAP_TC_EMIFS_PRIOR;
188 break;
189 default:
190 BUG();
191 return;
192 }
193 l = omap_readl(reg);
194 l &= ~(0xf << 8);
195 l |= (priority & 0xf) << 8;
196 omap_writel(l, reg);
197 }
198
199 if (cpu_class_is_omap2()) {
200 u32 ccr;
201
202 ccr = p->dma_read(CCR, lch);
203 if (priority)
204 ccr |= (1 << 6);
205 else
206 ccr &= ~(1 << 6);
207 p->dma_write(ccr, CCR, lch);
208 }
209 }
210 EXPORT_SYMBOL(omap_set_dma_priority);
211
omap_set_dma_transfer_params(int lch,int data_type,int elem_count,int frame_count,int sync_mode,int dma_trigger,int src_or_dst_synch)212 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
213 int frame_count, int sync_mode,
214 int dma_trigger, int src_or_dst_synch)
215 {
216 u32 l;
217
218 l = p->dma_read(CSDP, lch);
219 l &= ~0x03;
220 l |= data_type;
221 p->dma_write(l, CSDP, lch);
222
223 if (cpu_class_is_omap1()) {
224 u16 ccr;
225
226 ccr = p->dma_read(CCR, lch);
227 ccr &= ~(1 << 5);
228 if (sync_mode == OMAP_DMA_SYNC_FRAME)
229 ccr |= 1 << 5;
230 p->dma_write(ccr, CCR, lch);
231
232 ccr = p->dma_read(CCR2, lch);
233 ccr &= ~(1 << 2);
234 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
235 ccr |= 1 << 2;
236 p->dma_write(ccr, CCR2, lch);
237 }
238
239 if (cpu_class_is_omap2() && dma_trigger) {
240 u32 val;
241
242 val = p->dma_read(CCR, lch);
243
244 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
245 val &= ~((1 << 23) | (3 << 19) | 0x1f);
246 val |= (dma_trigger & ~0x1f) << 14;
247 val |= dma_trigger & 0x1f;
248
249 if (sync_mode & OMAP_DMA_SYNC_FRAME)
250 val |= 1 << 5;
251 else
252 val &= ~(1 << 5);
253
254 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
255 val |= 1 << 18;
256 else
257 val &= ~(1 << 18);
258
259 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
260 val &= ~(1 << 24); /* dest synch */
261 val |= (1 << 23); /* Prefetch */
262 } else if (src_or_dst_synch) {
263 val |= 1 << 24; /* source synch */
264 } else {
265 val &= ~(1 << 24); /* dest synch */
266 }
267 p->dma_write(val, CCR, lch);
268 }
269
270 p->dma_write(elem_count, CEN, lch);
271 p->dma_write(frame_count, CFN, lch);
272 }
273 EXPORT_SYMBOL(omap_set_dma_transfer_params);
274
omap_set_dma_color_mode(int lch,enum omap_dma_color_mode mode,u32 color)275 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
276 {
277 BUG_ON(omap_dma_in_1510_mode());
278
279 if (cpu_class_is_omap1()) {
280 u16 w;
281
282 w = p->dma_read(CCR2, lch);
283 w &= ~0x03;
284
285 switch (mode) {
286 case OMAP_DMA_CONSTANT_FILL:
287 w |= 0x01;
288 break;
289 case OMAP_DMA_TRANSPARENT_COPY:
290 w |= 0x02;
291 break;
292 case OMAP_DMA_COLOR_DIS:
293 break;
294 default:
295 BUG();
296 }
297 p->dma_write(w, CCR2, lch);
298
299 w = p->dma_read(LCH_CTRL, lch);
300 w &= ~0x0f;
301 /* Default is channel type 2D */
302 if (mode) {
303 p->dma_write(color, COLOR, lch);
304 w |= 1; /* Channel type G */
305 }
306 p->dma_write(w, LCH_CTRL, lch);
307 }
308
309 if (cpu_class_is_omap2()) {
310 u32 val;
311
312 val = p->dma_read(CCR, lch);
313 val &= ~((1 << 17) | (1 << 16));
314
315 switch (mode) {
316 case OMAP_DMA_CONSTANT_FILL:
317 val |= 1 << 16;
318 break;
319 case OMAP_DMA_TRANSPARENT_COPY:
320 val |= 1 << 17;
321 break;
322 case OMAP_DMA_COLOR_DIS:
323 break;
324 default:
325 BUG();
326 }
327 p->dma_write(val, CCR, lch);
328
329 color &= 0xffffff;
330 p->dma_write(color, COLOR, lch);
331 }
332 }
333 EXPORT_SYMBOL(omap_set_dma_color_mode);
334
omap_set_dma_write_mode(int lch,enum omap_dma_write_mode mode)335 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
336 {
337 if (cpu_class_is_omap2()) {
338 u32 csdp;
339
340 csdp = p->dma_read(CSDP, lch);
341 csdp &= ~(0x3 << 16);
342 csdp |= (mode << 16);
343 p->dma_write(csdp, CSDP, lch);
344 }
345 }
346 EXPORT_SYMBOL(omap_set_dma_write_mode);
347
omap_set_dma_channel_mode(int lch,enum omap_dma_channel_mode mode)348 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
349 {
350 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
351 u32 l;
352
353 l = p->dma_read(LCH_CTRL, lch);
354 l &= ~0x7;
355 l |= mode;
356 p->dma_write(l, LCH_CTRL, lch);
357 }
358 }
359 EXPORT_SYMBOL(omap_set_dma_channel_mode);
360
361 /* Note that src_port is only for omap1 */
omap_set_dma_src_params(int lch,int src_port,int src_amode,unsigned long src_start,int src_ei,int src_fi)362 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
363 unsigned long src_start,
364 int src_ei, int src_fi)
365 {
366 u32 l;
367
368 if (cpu_class_is_omap1()) {
369 u16 w;
370
371 w = p->dma_read(CSDP, lch);
372 w &= ~(0x1f << 2);
373 w |= src_port << 2;
374 p->dma_write(w, CSDP, lch);
375 }
376
377 l = p->dma_read(CCR, lch);
378 l &= ~(0x03 << 12);
379 l |= src_amode << 12;
380 p->dma_write(l, CCR, lch);
381
382 p->dma_write(src_start, CSSA, lch);
383
384 p->dma_write(src_ei, CSEI, lch);
385 p->dma_write(src_fi, CSFI, lch);
386 }
387 EXPORT_SYMBOL(omap_set_dma_src_params);
388
omap_set_dma_params(int lch,struct omap_dma_channel_params * params)389 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
390 {
391 omap_set_dma_transfer_params(lch, params->data_type,
392 params->elem_count, params->frame_count,
393 params->sync_mode, params->trigger,
394 params->src_or_dst_synch);
395 omap_set_dma_src_params(lch, params->src_port,
396 params->src_amode, params->src_start,
397 params->src_ei, params->src_fi);
398
399 omap_set_dma_dest_params(lch, params->dst_port,
400 params->dst_amode, params->dst_start,
401 params->dst_ei, params->dst_fi);
402 if (params->read_prio || params->write_prio)
403 omap_dma_set_prio_lch(lch, params->read_prio,
404 params->write_prio);
405 }
406 EXPORT_SYMBOL(omap_set_dma_params);
407
omap_set_dma_src_index(int lch,int eidx,int fidx)408 void omap_set_dma_src_index(int lch, int eidx, int fidx)
409 {
410 if (cpu_class_is_omap2())
411 return;
412
413 p->dma_write(eidx, CSEI, lch);
414 p->dma_write(fidx, CSFI, lch);
415 }
416 EXPORT_SYMBOL(omap_set_dma_src_index);
417
omap_set_dma_src_data_pack(int lch,int enable)418 void omap_set_dma_src_data_pack(int lch, int enable)
419 {
420 u32 l;
421
422 l = p->dma_read(CSDP, lch);
423 l &= ~(1 << 6);
424 if (enable)
425 l |= (1 << 6);
426 p->dma_write(l, CSDP, lch);
427 }
428 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
429
omap_set_dma_src_burst_mode(int lch,enum omap_dma_burst_mode burst_mode)430 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
431 {
432 unsigned int burst = 0;
433 u32 l;
434
435 l = p->dma_read(CSDP, lch);
436 l &= ~(0x03 << 7);
437
438 switch (burst_mode) {
439 case OMAP_DMA_DATA_BURST_DIS:
440 break;
441 case OMAP_DMA_DATA_BURST_4:
442 if (cpu_class_is_omap2())
443 burst = 0x1;
444 else
445 burst = 0x2;
446 break;
447 case OMAP_DMA_DATA_BURST_8:
448 if (cpu_class_is_omap2()) {
449 burst = 0x2;
450 break;
451 }
452 /*
453 * not supported by current hardware on OMAP1
454 * w |= (0x03 << 7);
455 * fall through
456 */
457 case OMAP_DMA_DATA_BURST_16:
458 if (cpu_class_is_omap2()) {
459 burst = 0x3;
460 break;
461 }
462 /*
463 * OMAP1 don't support burst 16
464 * fall through
465 */
466 default:
467 BUG();
468 }
469
470 l |= (burst << 7);
471 p->dma_write(l, CSDP, lch);
472 }
473 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
474
475 /* Note that dest_port is only for OMAP1 */
omap_set_dma_dest_params(int lch,int dest_port,int dest_amode,unsigned long dest_start,int dst_ei,int dst_fi)476 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
477 unsigned long dest_start,
478 int dst_ei, int dst_fi)
479 {
480 u32 l;
481
482 if (cpu_class_is_omap1()) {
483 l = p->dma_read(CSDP, lch);
484 l &= ~(0x1f << 9);
485 l |= dest_port << 9;
486 p->dma_write(l, CSDP, lch);
487 }
488
489 l = p->dma_read(CCR, lch);
490 l &= ~(0x03 << 14);
491 l |= dest_amode << 14;
492 p->dma_write(l, CCR, lch);
493
494 p->dma_write(dest_start, CDSA, lch);
495
496 p->dma_write(dst_ei, CDEI, lch);
497 p->dma_write(dst_fi, CDFI, lch);
498 }
499 EXPORT_SYMBOL(omap_set_dma_dest_params);
500
omap_set_dma_dest_index(int lch,int eidx,int fidx)501 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
502 {
503 if (cpu_class_is_omap2())
504 return;
505
506 p->dma_write(eidx, CDEI, lch);
507 p->dma_write(fidx, CDFI, lch);
508 }
509 EXPORT_SYMBOL(omap_set_dma_dest_index);
510
omap_set_dma_dest_data_pack(int lch,int enable)511 void omap_set_dma_dest_data_pack(int lch, int enable)
512 {
513 u32 l;
514
515 l = p->dma_read(CSDP, lch);
516 l &= ~(1 << 13);
517 if (enable)
518 l |= 1 << 13;
519 p->dma_write(l, CSDP, lch);
520 }
521 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
522
omap_set_dma_dest_burst_mode(int lch,enum omap_dma_burst_mode burst_mode)523 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
524 {
525 unsigned int burst = 0;
526 u32 l;
527
528 l = p->dma_read(CSDP, lch);
529 l &= ~(0x03 << 14);
530
531 switch (burst_mode) {
532 case OMAP_DMA_DATA_BURST_DIS:
533 break;
534 case OMAP_DMA_DATA_BURST_4:
535 if (cpu_class_is_omap2())
536 burst = 0x1;
537 else
538 burst = 0x2;
539 break;
540 case OMAP_DMA_DATA_BURST_8:
541 if (cpu_class_is_omap2())
542 burst = 0x2;
543 else
544 burst = 0x3;
545 break;
546 case OMAP_DMA_DATA_BURST_16:
547 if (cpu_class_is_omap2()) {
548 burst = 0x3;
549 break;
550 }
551 /*
552 * OMAP1 don't support burst 16
553 * fall through
554 */
555 default:
556 printk(KERN_ERR "Invalid DMA burst mode\n");
557 BUG();
558 return;
559 }
560 l |= (burst << 14);
561 p->dma_write(l, CSDP, lch);
562 }
563 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
564
omap_enable_channel_irq(int lch)565 static inline void omap_enable_channel_irq(int lch)
566 {
567 u32 status;
568
569 /* Clear CSR */
570 if (cpu_class_is_omap1())
571 status = p->dma_read(CSR, lch);
572 else if (cpu_class_is_omap2())
573 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
574
575 /* Enable some nice interrupts. */
576 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
577 }
578
omap_disable_channel_irq(int lch)579 static void omap_disable_channel_irq(int lch)
580 {
581 if (cpu_class_is_omap2())
582 p->dma_write(0, CICR, lch);
583 }
584
omap_enable_dma_irq(int lch,u16 bits)585 void omap_enable_dma_irq(int lch, u16 bits)
586 {
587 dma_chan[lch].enabled_irqs |= bits;
588 }
589 EXPORT_SYMBOL(omap_enable_dma_irq);
590
omap_disable_dma_irq(int lch,u16 bits)591 void omap_disable_dma_irq(int lch, u16 bits)
592 {
593 dma_chan[lch].enabled_irqs &= ~bits;
594 }
595 EXPORT_SYMBOL(omap_disable_dma_irq);
596
enable_lnk(int lch)597 static inline void enable_lnk(int lch)
598 {
599 u32 l;
600
601 l = p->dma_read(CLNK_CTRL, lch);
602
603 if (cpu_class_is_omap1())
604 l &= ~(1 << 14);
605
606 /* Set the ENABLE_LNK bits */
607 if (dma_chan[lch].next_lch != -1)
608 l = dma_chan[lch].next_lch | (1 << 15);
609
610 #ifndef CONFIG_ARCH_OMAP1
611 if (cpu_class_is_omap2())
612 if (dma_chan[lch].next_linked_ch != -1)
613 l = dma_chan[lch].next_linked_ch | (1 << 15);
614 #endif
615
616 p->dma_write(l, CLNK_CTRL, lch);
617 }
618
disable_lnk(int lch)619 static inline void disable_lnk(int lch)
620 {
621 u32 l;
622
623 l = p->dma_read(CLNK_CTRL, lch);
624
625 /* Disable interrupts */
626 if (cpu_class_is_omap1()) {
627 p->dma_write(0, CICR, lch);
628 /* Set the STOP_LNK bit */
629 l |= 1 << 14;
630 }
631
632 if (cpu_class_is_omap2()) {
633 omap_disable_channel_irq(lch);
634 /* Clear the ENABLE_LNK bit */
635 l &= ~(1 << 15);
636 }
637
638 p->dma_write(l, CLNK_CTRL, lch);
639 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
640 }
641
omap2_enable_irq_lch(int lch)642 static inline void omap2_enable_irq_lch(int lch)
643 {
644 u32 val;
645 unsigned long flags;
646
647 if (!cpu_class_is_omap2())
648 return;
649
650 spin_lock_irqsave(&dma_chan_lock, flags);
651 val = p->dma_read(IRQENABLE_L0, lch);
652 val |= 1 << lch;
653 p->dma_write(val, IRQENABLE_L0, lch);
654 spin_unlock_irqrestore(&dma_chan_lock, flags);
655 }
656
omap2_disable_irq_lch(int lch)657 static inline void omap2_disable_irq_lch(int lch)
658 {
659 u32 val;
660 unsigned long flags;
661
662 if (!cpu_class_is_omap2())
663 return;
664
665 spin_lock_irqsave(&dma_chan_lock, flags);
666 val = p->dma_read(IRQENABLE_L0, lch);
667 val &= ~(1 << lch);
668 p->dma_write(val, IRQENABLE_L0, lch);
669 spin_unlock_irqrestore(&dma_chan_lock, flags);
670 }
671
omap_request_dma(int dev_id,const char * dev_name,void (* callback)(int lch,u16 ch_status,void * data),void * data,int * dma_ch_out)672 int omap_request_dma(int dev_id, const char *dev_name,
673 void (*callback)(int lch, u16 ch_status, void *data),
674 void *data, int *dma_ch_out)
675 {
676 int ch, free_ch = -1;
677 unsigned long flags;
678 struct omap_dma_lch *chan;
679
680 spin_lock_irqsave(&dma_chan_lock, flags);
681 for (ch = 0; ch < dma_chan_count; ch++) {
682 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
683 free_ch = ch;
684 if (dev_id == 0)
685 break;
686 }
687 }
688 if (free_ch == -1) {
689 spin_unlock_irqrestore(&dma_chan_lock, flags);
690 return -EBUSY;
691 }
692 chan = dma_chan + free_ch;
693 chan->dev_id = dev_id;
694
695 if (p->clear_lch_regs)
696 p->clear_lch_regs(free_ch);
697
698 if (cpu_class_is_omap2())
699 omap_clear_dma(free_ch);
700
701 spin_unlock_irqrestore(&dma_chan_lock, flags);
702
703 chan->dev_name = dev_name;
704 chan->callback = callback;
705 chan->data = data;
706 chan->flags = 0;
707
708 #ifndef CONFIG_ARCH_OMAP1
709 if (cpu_class_is_omap2()) {
710 chan->chain_id = -1;
711 chan->next_linked_ch = -1;
712 }
713 #endif
714
715 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
716
717 if (cpu_class_is_omap1())
718 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
719 else if (cpu_class_is_omap2())
720 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
721 OMAP2_DMA_TRANS_ERR_IRQ;
722
723 if (cpu_is_omap16xx()) {
724 /* If the sync device is set, configure it dynamically. */
725 if (dev_id != 0) {
726 set_gdma_dev(free_ch + 1, dev_id);
727 dev_id = free_ch + 1;
728 }
729 /*
730 * Disable the 1510 compatibility mode and set the sync device
731 * id.
732 */
733 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
734 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
735 p->dma_write(dev_id, CCR, free_ch);
736 }
737
738 if (cpu_class_is_omap2()) {
739 omap2_enable_irq_lch(free_ch);
740 omap_enable_channel_irq(free_ch);
741 /* Clear the CSR register and IRQ status register */
742 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
743 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
744 }
745
746 *dma_ch_out = free_ch;
747
748 return 0;
749 }
750 EXPORT_SYMBOL(omap_request_dma);
751
omap_free_dma(int lch)752 void omap_free_dma(int lch)
753 {
754 unsigned long flags;
755
756 if (dma_chan[lch].dev_id == -1) {
757 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
758 lch);
759 return;
760 }
761
762 if (cpu_class_is_omap1()) {
763 /* Disable all DMA interrupts for the channel. */
764 p->dma_write(0, CICR, lch);
765 /* Make sure the DMA transfer is stopped. */
766 p->dma_write(0, CCR, lch);
767 }
768
769 if (cpu_class_is_omap2()) {
770 omap2_disable_irq_lch(lch);
771
772 /* Clear the CSR register and IRQ status register */
773 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
774 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
775
776 /* Disable all DMA interrupts for the channel. */
777 p->dma_write(0, CICR, lch);
778
779 /* Make sure the DMA transfer is stopped. */
780 p->dma_write(0, CCR, lch);
781 omap_clear_dma(lch);
782 }
783
784 spin_lock_irqsave(&dma_chan_lock, flags);
785 dma_chan[lch].dev_id = -1;
786 dma_chan[lch].next_lch = -1;
787 dma_chan[lch].callback = NULL;
788 spin_unlock_irqrestore(&dma_chan_lock, flags);
789 }
790 EXPORT_SYMBOL(omap_free_dma);
791
792 /**
793 * @brief omap_dma_set_global_params : Set global priority settings for dma
794 *
795 * @param arb_rate
796 * @param max_fifo_depth
797 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
798 * DMA_THREAD_RESERVE_ONET
799 * DMA_THREAD_RESERVE_TWOT
800 * DMA_THREAD_RESERVE_THREET
801 */
802 void
omap_dma_set_global_params(int arb_rate,int max_fifo_depth,int tparams)803 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
804 {
805 u32 reg;
806
807 if (!cpu_class_is_omap2()) {
808 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
809 return;
810 }
811
812 if (max_fifo_depth == 0)
813 max_fifo_depth = 1;
814 if (arb_rate == 0)
815 arb_rate = 1;
816
817 reg = 0xff & max_fifo_depth;
818 reg |= (0x3 & tparams) << 12;
819 reg |= (arb_rate & 0xff) << 16;
820
821 p->dma_write(reg, GCR, 0);
822 }
823 EXPORT_SYMBOL(omap_dma_set_global_params);
824
825 /**
826 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
827 *
828 * @param lch
829 * @param read_prio - Read priority
830 * @param write_prio - Write priority
831 * Both of the above can be set with one of the following values :
832 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
833 */
834 int
omap_dma_set_prio_lch(int lch,unsigned char read_prio,unsigned char write_prio)835 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
836 unsigned char write_prio)
837 {
838 u32 l;
839
840 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
841 printk(KERN_ERR "Invalid channel id\n");
842 return -EINVAL;
843 }
844 l = p->dma_read(CCR, lch);
845 l &= ~((1 << 6) | (1 << 26));
846 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
847 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
848 else
849 l |= ((read_prio & 0x1) << 6);
850
851 p->dma_write(l, CCR, lch);
852
853 return 0;
854 }
855 EXPORT_SYMBOL(omap_dma_set_prio_lch);
856
857 /*
858 * Clears any DMA state so the DMA engine is ready to restart with new buffers
859 * through omap_start_dma(). Any buffers in flight are discarded.
860 */
omap_clear_dma(int lch)861 void omap_clear_dma(int lch)
862 {
863 unsigned long flags;
864
865 local_irq_save(flags);
866 p->clear_dma(lch);
867 local_irq_restore(flags);
868 }
869 EXPORT_SYMBOL(omap_clear_dma);
870
omap_start_dma(int lch)871 void omap_start_dma(int lch)
872 {
873 u32 l;
874
875 /*
876 * The CPC/CDAC register needs to be initialized to zero
877 * before starting dma transfer.
878 */
879 if (cpu_is_omap15xx())
880 p->dma_write(0, CPC, lch);
881 else
882 p->dma_write(0, CDAC, lch);
883
884 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
885 int next_lch, cur_lch;
886 char dma_chan_link_map[dma_lch_count];
887
888 dma_chan_link_map[lch] = 1;
889 /* Set the link register of the first channel */
890 enable_lnk(lch);
891
892 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
893 cur_lch = dma_chan[lch].next_lch;
894 do {
895 next_lch = dma_chan[cur_lch].next_lch;
896
897 /* The loop case: we've been here already */
898 if (dma_chan_link_map[cur_lch])
899 break;
900 /* Mark the current channel */
901 dma_chan_link_map[cur_lch] = 1;
902
903 enable_lnk(cur_lch);
904 omap_enable_channel_irq(cur_lch);
905
906 cur_lch = next_lch;
907 } while (next_lch != -1);
908 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
909 p->dma_write(lch, CLNK_CTRL, lch);
910
911 omap_enable_channel_irq(lch);
912
913 l = p->dma_read(CCR, lch);
914
915 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
916 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
917 l |= OMAP_DMA_CCR_EN;
918
919 /*
920 * As dma_write() uses IO accessors which are weakly ordered, there
921 * is no guarantee that data in coherent DMA memory will be visible
922 * to the DMA device. Add a memory barrier here to ensure that any
923 * such data is visible prior to enabling DMA.
924 */
925 mb();
926 p->dma_write(l, CCR, lch);
927
928 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
929 }
930 EXPORT_SYMBOL(omap_start_dma);
931
omap_stop_dma(int lch)932 void omap_stop_dma(int lch)
933 {
934 u32 l;
935
936 /* Disable all interrupts on the channel */
937 if (cpu_class_is_omap1())
938 p->dma_write(0, CICR, lch);
939
940 l = p->dma_read(CCR, lch);
941 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
942 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
943 int i = 0;
944 u32 sys_cf;
945
946 /* Configure No-Standby */
947 l = p->dma_read(OCP_SYSCONFIG, lch);
948 sys_cf = l;
949 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
950 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
951 p->dma_write(l , OCP_SYSCONFIG, 0);
952
953 l = p->dma_read(CCR, lch);
954 l &= ~OMAP_DMA_CCR_EN;
955 p->dma_write(l, CCR, lch);
956
957 /* Wait for sDMA FIFO drain */
958 l = p->dma_read(CCR, lch);
959 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
960 OMAP_DMA_CCR_WR_ACTIVE))) {
961 udelay(5);
962 i++;
963 l = p->dma_read(CCR, lch);
964 }
965 if (i >= 100)
966 printk(KERN_ERR "DMA drain did not complete on "
967 "lch %d\n", lch);
968 /* Restore OCP_SYSCONFIG */
969 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
970 } else {
971 l &= ~OMAP_DMA_CCR_EN;
972 p->dma_write(l, CCR, lch);
973 }
974
975 /*
976 * Ensure that data transferred by DMA is visible to any access
977 * after DMA has been disabled. This is important for coherent
978 * DMA regions.
979 */
980 mb();
981
982 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
983 int next_lch, cur_lch = lch;
984 char dma_chan_link_map[dma_lch_count];
985
986 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
987 do {
988 /* The loop case: we've been here already */
989 if (dma_chan_link_map[cur_lch])
990 break;
991 /* Mark the current channel */
992 dma_chan_link_map[cur_lch] = 1;
993
994 disable_lnk(cur_lch);
995
996 next_lch = dma_chan[cur_lch].next_lch;
997 cur_lch = next_lch;
998 } while (next_lch != -1);
999 }
1000
1001 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1002 }
1003 EXPORT_SYMBOL(omap_stop_dma);
1004
1005 /*
1006 * Allows changing the DMA callback function or data. This may be needed if
1007 * the driver shares a single DMA channel for multiple dma triggers.
1008 */
omap_set_dma_callback(int lch,void (* callback)(int lch,u16 ch_status,void * data),void * data)1009 int omap_set_dma_callback(int lch,
1010 void (*callback)(int lch, u16 ch_status, void *data),
1011 void *data)
1012 {
1013 unsigned long flags;
1014
1015 if (lch < 0)
1016 return -ENODEV;
1017
1018 spin_lock_irqsave(&dma_chan_lock, flags);
1019 if (dma_chan[lch].dev_id == -1) {
1020 printk(KERN_ERR "DMA callback for not set for free channel\n");
1021 spin_unlock_irqrestore(&dma_chan_lock, flags);
1022 return -EINVAL;
1023 }
1024 dma_chan[lch].callback = callback;
1025 dma_chan[lch].data = data;
1026 spin_unlock_irqrestore(&dma_chan_lock, flags);
1027
1028 return 0;
1029 }
1030 EXPORT_SYMBOL(omap_set_dma_callback);
1031
1032 /*
1033 * Returns current physical source address for the given DMA channel.
1034 * If the channel is running the caller must disable interrupts prior calling
1035 * this function and process the returned value before re-enabling interrupt to
1036 * prevent races with the interrupt handler. Note that in continuous mode there
1037 * is a chance for CSSA_L register overflow between the two reads resulting
1038 * in incorrect return value.
1039 */
omap_get_dma_src_pos(int lch)1040 dma_addr_t omap_get_dma_src_pos(int lch)
1041 {
1042 dma_addr_t offset = 0;
1043
1044 if (cpu_is_omap15xx())
1045 offset = p->dma_read(CPC, lch);
1046 else
1047 offset = p->dma_read(CSAC, lch);
1048
1049 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1050 offset = p->dma_read(CSAC, lch);
1051
1052 if (!cpu_is_omap15xx()) {
1053 /*
1054 * CDAC == 0 indicates that the DMA transfer on the channel has
1055 * not been started (no data has been transferred so far).
1056 * Return the programmed source start address in this case.
1057 */
1058 if (likely(p->dma_read(CDAC, lch)))
1059 offset = p->dma_read(CSAC, lch);
1060 else
1061 offset = p->dma_read(CSSA, lch);
1062 }
1063
1064 if (cpu_class_is_omap1())
1065 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1066
1067 return offset;
1068 }
1069 EXPORT_SYMBOL(omap_get_dma_src_pos);
1070
1071 /*
1072 * Returns current physical destination address for the given DMA channel.
1073 * If the channel is running the caller must disable interrupts prior calling
1074 * this function and process the returned value before re-enabling interrupt to
1075 * prevent races with the interrupt handler. Note that in continuous mode there
1076 * is a chance for CDSA_L register overflow between the two reads resulting
1077 * in incorrect return value.
1078 */
omap_get_dma_dst_pos(int lch)1079 dma_addr_t omap_get_dma_dst_pos(int lch)
1080 {
1081 dma_addr_t offset = 0;
1082
1083 if (cpu_is_omap15xx())
1084 offset = p->dma_read(CPC, lch);
1085 else
1086 offset = p->dma_read(CDAC, lch);
1087
1088 /*
1089 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1090 * read before the DMA controller finished disabling the channel.
1091 */
1092 if (!cpu_is_omap15xx() && offset == 0) {
1093 offset = p->dma_read(CDAC, lch);
1094 /*
1095 * CDAC == 0 indicates that the DMA transfer on the channel has
1096 * not been started (no data has been transferred so far).
1097 * Return the programmed destination start address in this case.
1098 */
1099 if (unlikely(!offset))
1100 offset = p->dma_read(CDSA, lch);
1101 }
1102
1103 if (cpu_class_is_omap1())
1104 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1105
1106 return offset;
1107 }
1108 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1109
omap_get_dma_active_status(int lch)1110 int omap_get_dma_active_status(int lch)
1111 {
1112 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1113 }
1114 EXPORT_SYMBOL(omap_get_dma_active_status);
1115
omap_dma_running(void)1116 int omap_dma_running(void)
1117 {
1118 int lch;
1119
1120 if (cpu_class_is_omap1())
1121 if (omap_lcd_dma_running())
1122 return 1;
1123
1124 for (lch = 0; lch < dma_chan_count; lch++)
1125 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1126 return 1;
1127
1128 return 0;
1129 }
1130
1131 /*
1132 * lch_queue DMA will start right after lch_head one is finished.
1133 * For this DMA link to start, you still need to start (see omap_start_dma)
1134 * the first one. That will fire up the entire queue.
1135 */
omap_dma_link_lch(int lch_head,int lch_queue)1136 void omap_dma_link_lch(int lch_head, int lch_queue)
1137 {
1138 if (omap_dma_in_1510_mode()) {
1139 if (lch_head == lch_queue) {
1140 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1141 CCR, lch_head);
1142 return;
1143 }
1144 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1145 BUG();
1146 return;
1147 }
1148
1149 if ((dma_chan[lch_head].dev_id == -1) ||
1150 (dma_chan[lch_queue].dev_id == -1)) {
1151 printk(KERN_ERR "omap_dma: trying to link "
1152 "non requested channels\n");
1153 dump_stack();
1154 }
1155
1156 dma_chan[lch_head].next_lch = lch_queue;
1157 }
1158 EXPORT_SYMBOL(omap_dma_link_lch);
1159
1160 /*
1161 * Once the DMA queue is stopped, we can destroy it.
1162 */
omap_dma_unlink_lch(int lch_head,int lch_queue)1163 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1164 {
1165 if (omap_dma_in_1510_mode()) {
1166 if (lch_head == lch_queue) {
1167 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1168 CCR, lch_head);
1169 return;
1170 }
1171 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1172 BUG();
1173 return;
1174 }
1175
1176 if (dma_chan[lch_head].next_lch != lch_queue ||
1177 dma_chan[lch_head].next_lch == -1) {
1178 printk(KERN_ERR "omap_dma: trying to unlink "
1179 "non linked channels\n");
1180 dump_stack();
1181 }
1182
1183 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1184 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1185 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1186 "before unlinking\n");
1187 dump_stack();
1188 }
1189
1190 dma_chan[lch_head].next_lch = -1;
1191 }
1192 EXPORT_SYMBOL(omap_dma_unlink_lch);
1193
1194 #ifndef CONFIG_ARCH_OMAP1
1195 /* Create chain of DMA channesls */
create_dma_lch_chain(int lch_head,int lch_queue)1196 static void create_dma_lch_chain(int lch_head, int lch_queue)
1197 {
1198 u32 l;
1199
1200 /* Check if this is the first link in chain */
1201 if (dma_chan[lch_head].next_linked_ch == -1) {
1202 dma_chan[lch_head].next_linked_ch = lch_queue;
1203 dma_chan[lch_head].prev_linked_ch = lch_queue;
1204 dma_chan[lch_queue].next_linked_ch = lch_head;
1205 dma_chan[lch_queue].prev_linked_ch = lch_head;
1206 }
1207
1208 /* a link exists, link the new channel in circular chain */
1209 else {
1210 dma_chan[lch_queue].next_linked_ch =
1211 dma_chan[lch_head].next_linked_ch;
1212 dma_chan[lch_queue].prev_linked_ch = lch_head;
1213 dma_chan[lch_head].next_linked_ch = lch_queue;
1214 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1215 lch_queue;
1216 }
1217
1218 l = p->dma_read(CLNK_CTRL, lch_head);
1219 l &= ~(0x1f);
1220 l |= lch_queue;
1221 p->dma_write(l, CLNK_CTRL, lch_head);
1222
1223 l = p->dma_read(CLNK_CTRL, lch_queue);
1224 l &= ~(0x1f);
1225 l |= (dma_chan[lch_queue].next_linked_ch);
1226 p->dma_write(l, CLNK_CTRL, lch_queue);
1227 }
1228
1229 /**
1230 * @brief omap_request_dma_chain : Request a chain of DMA channels
1231 *
1232 * @param dev_id - Device id using the dma channel
1233 * @param dev_name - Device name
1234 * @param callback - Call back function
1235 * @chain_id -
1236 * @no_of_chans - Number of channels requested
1237 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1238 * OMAP_DMA_DYNAMIC_CHAIN
1239 * @params - Channel parameters
1240 *
1241 * @return - Success : 0
1242 * Failure: -EINVAL/-ENOMEM
1243 */
omap_request_dma_chain(int dev_id,const char * dev_name,void (* callback)(int lch,u16 ch_status,void * data),int * chain_id,int no_of_chans,int chain_mode,struct omap_dma_channel_params params)1244 int omap_request_dma_chain(int dev_id, const char *dev_name,
1245 void (*callback) (int lch, u16 ch_status,
1246 void *data),
1247 int *chain_id, int no_of_chans, int chain_mode,
1248 struct omap_dma_channel_params params)
1249 {
1250 int *channels;
1251 int i, err;
1252
1253 /* Is the chain mode valid ? */
1254 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1255 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1256 printk(KERN_ERR "Invalid chain mode requested\n");
1257 return -EINVAL;
1258 }
1259
1260 if (unlikely((no_of_chans < 1
1261 || no_of_chans > dma_lch_count))) {
1262 printk(KERN_ERR "Invalid Number of channels requested\n");
1263 return -EINVAL;
1264 }
1265
1266 /*
1267 * Allocate a queue to maintain the status of the channels
1268 * in the chain
1269 */
1270 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1271 if (channels == NULL) {
1272 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1273 return -ENOMEM;
1274 }
1275
1276 /* request and reserve DMA channels for the chain */
1277 for (i = 0; i < no_of_chans; i++) {
1278 err = omap_request_dma(dev_id, dev_name,
1279 callback, NULL, &channels[i]);
1280 if (err < 0) {
1281 int j;
1282 for (j = 0; j < i; j++)
1283 omap_free_dma(channels[j]);
1284 kfree(channels);
1285 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1286 return err;
1287 }
1288 dma_chan[channels[i]].prev_linked_ch = -1;
1289 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1290
1291 /*
1292 * Allowing client drivers to set common parameters now,
1293 * so that later only relevant (src_start, dest_start
1294 * and element count) can be set
1295 */
1296 omap_set_dma_params(channels[i], ¶ms);
1297 }
1298
1299 *chain_id = channels[0];
1300 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1301 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1302 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1303 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1304
1305 for (i = 0; i < no_of_chans; i++)
1306 dma_chan[channels[i]].chain_id = *chain_id;
1307
1308 /* Reset the Queue pointers */
1309 OMAP_DMA_CHAIN_QINIT(*chain_id);
1310
1311 /* Set up the chain */
1312 if (no_of_chans == 1)
1313 create_dma_lch_chain(channels[0], channels[0]);
1314 else {
1315 for (i = 0; i < (no_of_chans - 1); i++)
1316 create_dma_lch_chain(channels[i], channels[i + 1]);
1317 }
1318
1319 return 0;
1320 }
1321 EXPORT_SYMBOL(omap_request_dma_chain);
1322
1323 /**
1324 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1325 * params after setting it. Dont do this while dma is running!!
1326 *
1327 * @param chain_id - Chained logical channel id.
1328 * @param params
1329 *
1330 * @return - Success : 0
1331 * Failure : -EINVAL
1332 */
omap_modify_dma_chain_params(int chain_id,struct omap_dma_channel_params params)1333 int omap_modify_dma_chain_params(int chain_id,
1334 struct omap_dma_channel_params params)
1335 {
1336 int *channels;
1337 u32 i;
1338
1339 /* Check for input params */
1340 if (unlikely((chain_id < 0
1341 || chain_id >= dma_lch_count))) {
1342 printk(KERN_ERR "Invalid chain id\n");
1343 return -EINVAL;
1344 }
1345
1346 /* Check if the chain exists */
1347 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1348 printk(KERN_ERR "Chain doesn't exists\n");
1349 return -EINVAL;
1350 }
1351 channels = dma_linked_lch[chain_id].linked_dmach_q;
1352
1353 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1354 /*
1355 * Allowing client drivers to set common parameters now,
1356 * so that later only relevant (src_start, dest_start
1357 * and element count) can be set
1358 */
1359 omap_set_dma_params(channels[i], ¶ms);
1360 }
1361
1362 return 0;
1363 }
1364 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1365
1366 /**
1367 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1368 *
1369 * @param chain_id
1370 *
1371 * @return - Success : 0
1372 * Failure : -EINVAL
1373 */
omap_free_dma_chain(int chain_id)1374 int omap_free_dma_chain(int chain_id)
1375 {
1376 int *channels;
1377 u32 i;
1378
1379 /* Check for input params */
1380 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1381 printk(KERN_ERR "Invalid chain id\n");
1382 return -EINVAL;
1383 }
1384
1385 /* Check if the chain exists */
1386 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1387 printk(KERN_ERR "Chain doesn't exists\n");
1388 return -EINVAL;
1389 }
1390
1391 channels = dma_linked_lch[chain_id].linked_dmach_q;
1392 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1393 dma_chan[channels[i]].next_linked_ch = -1;
1394 dma_chan[channels[i]].prev_linked_ch = -1;
1395 dma_chan[channels[i]].chain_id = -1;
1396 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1397 omap_free_dma(channels[i]);
1398 }
1399
1400 kfree(channels);
1401
1402 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1403 dma_linked_lch[chain_id].chain_mode = -1;
1404 dma_linked_lch[chain_id].chain_state = -1;
1405
1406 return (0);
1407 }
1408 EXPORT_SYMBOL(omap_free_dma_chain);
1409
1410 /**
1411 * @brief omap_dma_chain_status - Check if the chain is in
1412 * active / inactive state.
1413 * @param chain_id
1414 *
1415 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1416 * Failure : -EINVAL
1417 */
omap_dma_chain_status(int chain_id)1418 int omap_dma_chain_status(int chain_id)
1419 {
1420 /* Check for input params */
1421 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1422 printk(KERN_ERR "Invalid chain id\n");
1423 return -EINVAL;
1424 }
1425
1426 /* Check if the chain exists */
1427 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1428 printk(KERN_ERR "Chain doesn't exists\n");
1429 return -EINVAL;
1430 }
1431 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1432 dma_linked_lch[chain_id].q_count);
1433
1434 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1435 return OMAP_DMA_CHAIN_INACTIVE;
1436
1437 return OMAP_DMA_CHAIN_ACTIVE;
1438 }
1439 EXPORT_SYMBOL(omap_dma_chain_status);
1440
1441 /**
1442 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1443 * set the params and start the transfer.
1444 *
1445 * @param chain_id
1446 * @param src_start - buffer start address
1447 * @param dest_start - Dest address
1448 * @param elem_count
1449 * @param frame_count
1450 * @param callbk_data - channel callback parameter data.
1451 *
1452 * @return - Success : 0
1453 * Failure: -EINVAL/-EBUSY
1454 */
omap_dma_chain_a_transfer(int chain_id,int src_start,int dest_start,int elem_count,int frame_count,void * callbk_data)1455 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1456 int elem_count, int frame_count, void *callbk_data)
1457 {
1458 int *channels;
1459 u32 l, lch;
1460 int start_dma = 0;
1461
1462 /*
1463 * if buffer size is less than 1 then there is
1464 * no use of starting the chain
1465 */
1466 if (elem_count < 1) {
1467 printk(KERN_ERR "Invalid buffer size\n");
1468 return -EINVAL;
1469 }
1470
1471 /* Check for input params */
1472 if (unlikely((chain_id < 0
1473 || chain_id >= dma_lch_count))) {
1474 printk(KERN_ERR "Invalid chain id\n");
1475 return -EINVAL;
1476 }
1477
1478 /* Check if the chain exists */
1479 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1480 printk(KERN_ERR "Chain doesn't exist\n");
1481 return -EINVAL;
1482 }
1483
1484 /* Check if all the channels in chain are in use */
1485 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1486 return -EBUSY;
1487
1488 /* Frame count may be negative in case of indexed transfers */
1489 channels = dma_linked_lch[chain_id].linked_dmach_q;
1490
1491 /* Get a free channel */
1492 lch = channels[dma_linked_lch[chain_id].q_tail];
1493
1494 /* Store the callback data */
1495 dma_chan[lch].data = callbk_data;
1496
1497 /* Increment the q_tail */
1498 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1499
1500 /* Set the params to the free channel */
1501 if (src_start != 0)
1502 p->dma_write(src_start, CSSA, lch);
1503 if (dest_start != 0)
1504 p->dma_write(dest_start, CDSA, lch);
1505
1506 /* Write the buffer size */
1507 p->dma_write(elem_count, CEN, lch);
1508 p->dma_write(frame_count, CFN, lch);
1509
1510 /*
1511 * If the chain is dynamically linked,
1512 * then we may have to start the chain if its not active
1513 */
1514 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1515
1516 /*
1517 * In Dynamic chain, if the chain is not started,
1518 * queue the channel
1519 */
1520 if (dma_linked_lch[chain_id].chain_state ==
1521 DMA_CHAIN_NOTSTARTED) {
1522 /* Enable the link in previous channel */
1523 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1524 DMA_CH_QUEUED)
1525 enable_lnk(dma_chan[lch].prev_linked_ch);
1526 dma_chan[lch].state = DMA_CH_QUEUED;
1527 }
1528
1529 /*
1530 * Chain is already started, make sure its active,
1531 * if not then start the chain
1532 */
1533 else {
1534 start_dma = 1;
1535
1536 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1537 DMA_CH_STARTED) {
1538 enable_lnk(dma_chan[lch].prev_linked_ch);
1539 dma_chan[lch].state = DMA_CH_QUEUED;
1540 start_dma = 0;
1541 if (0 == ((1 << 7) & p->dma_read(
1542 CCR, dma_chan[lch].prev_linked_ch))) {
1543 disable_lnk(dma_chan[lch].
1544 prev_linked_ch);
1545 pr_debug("\n prev ch is stopped\n");
1546 start_dma = 1;
1547 }
1548 }
1549
1550 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1551 == DMA_CH_QUEUED) {
1552 enable_lnk(dma_chan[lch].prev_linked_ch);
1553 dma_chan[lch].state = DMA_CH_QUEUED;
1554 start_dma = 0;
1555 }
1556 omap_enable_channel_irq(lch);
1557
1558 l = p->dma_read(CCR, lch);
1559
1560 if ((0 == (l & (1 << 24))))
1561 l &= ~(1 << 25);
1562 else
1563 l |= (1 << 25);
1564 if (start_dma == 1) {
1565 if (0 == (l & (1 << 7))) {
1566 l |= (1 << 7);
1567 dma_chan[lch].state = DMA_CH_STARTED;
1568 pr_debug("starting %d\n", lch);
1569 p->dma_write(l, CCR, lch);
1570 } else
1571 start_dma = 0;
1572 } else {
1573 if (0 == (l & (1 << 7)))
1574 p->dma_write(l, CCR, lch);
1575 }
1576 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1577 }
1578 }
1579
1580 return 0;
1581 }
1582 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1583
1584 /**
1585 * @brief omap_start_dma_chain_transfers - Start the chain
1586 *
1587 * @param chain_id
1588 *
1589 * @return - Success : 0
1590 * Failure : -EINVAL/-EBUSY
1591 */
omap_start_dma_chain_transfers(int chain_id)1592 int omap_start_dma_chain_transfers(int chain_id)
1593 {
1594 int *channels;
1595 u32 l, i;
1596
1597 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1598 printk(KERN_ERR "Invalid chain id\n");
1599 return -EINVAL;
1600 }
1601
1602 channels = dma_linked_lch[chain_id].linked_dmach_q;
1603
1604 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1605 printk(KERN_ERR "Chain is already started\n");
1606 return -EBUSY;
1607 }
1608
1609 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1610 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1611 i++) {
1612 enable_lnk(channels[i]);
1613 omap_enable_channel_irq(channels[i]);
1614 }
1615 } else {
1616 omap_enable_channel_irq(channels[0]);
1617 }
1618
1619 l = p->dma_read(CCR, channels[0]);
1620 l |= (1 << 7);
1621 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1622 dma_chan[channels[0]].state = DMA_CH_STARTED;
1623
1624 if ((0 == (l & (1 << 24))))
1625 l &= ~(1 << 25);
1626 else
1627 l |= (1 << 25);
1628 p->dma_write(l, CCR, channels[0]);
1629
1630 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1631
1632 return 0;
1633 }
1634 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1635
1636 /**
1637 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1638 *
1639 * @param chain_id
1640 *
1641 * @return - Success : 0
1642 * Failure : EINVAL
1643 */
omap_stop_dma_chain_transfers(int chain_id)1644 int omap_stop_dma_chain_transfers(int chain_id)
1645 {
1646 int *channels;
1647 u32 l, i;
1648 u32 sys_cf = 0;
1649
1650 /* Check for input params */
1651 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1652 printk(KERN_ERR "Invalid chain id\n");
1653 return -EINVAL;
1654 }
1655
1656 /* Check if the chain exists */
1657 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1658 printk(KERN_ERR "Chain doesn't exists\n");
1659 return -EINVAL;
1660 }
1661 channels = dma_linked_lch[chain_id].linked_dmach_q;
1662
1663 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1664 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1665 l = sys_cf;
1666 /* Middle mode reg set no Standby */
1667 l &= ~((1 << 12)|(1 << 13));
1668 p->dma_write(l, OCP_SYSCONFIG, 0);
1669 }
1670
1671 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1672
1673 /* Stop the Channel transmission */
1674 l = p->dma_read(CCR, channels[i]);
1675 l &= ~(1 << 7);
1676 p->dma_write(l, CCR, channels[i]);
1677
1678 /* Disable the link in all the channels */
1679 disable_lnk(channels[i]);
1680 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1681
1682 }
1683 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1684
1685 /* Reset the Queue pointers */
1686 OMAP_DMA_CHAIN_QINIT(chain_id);
1687
1688 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1689 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1690
1691 return 0;
1692 }
1693 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1694
1695 /* Get the index of the ongoing DMA in chain */
1696 /**
1697 * @brief omap_get_dma_chain_index - Get the element and frame index
1698 * of the ongoing DMA in chain
1699 *
1700 * @param chain_id
1701 * @param ei - Element index
1702 * @param fi - Frame index
1703 *
1704 * @return - Success : 0
1705 * Failure : -EINVAL
1706 */
omap_get_dma_chain_index(int chain_id,int * ei,int * fi)1707 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1708 {
1709 int lch;
1710 int *channels;
1711
1712 /* Check for input params */
1713 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1714 printk(KERN_ERR "Invalid chain id\n");
1715 return -EINVAL;
1716 }
1717
1718 /* Check if the chain exists */
1719 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1720 printk(KERN_ERR "Chain doesn't exists\n");
1721 return -EINVAL;
1722 }
1723 if ((!ei) || (!fi))
1724 return -EINVAL;
1725
1726 channels = dma_linked_lch[chain_id].linked_dmach_q;
1727
1728 /* Get the current channel */
1729 lch = channels[dma_linked_lch[chain_id].q_head];
1730
1731 *ei = p->dma_read(CCEN, lch);
1732 *fi = p->dma_read(CCFN, lch);
1733
1734 return 0;
1735 }
1736 EXPORT_SYMBOL(omap_get_dma_chain_index);
1737
1738 /**
1739 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1740 * ongoing DMA in chain
1741 *
1742 * @param chain_id
1743 *
1744 * @return - Success : Destination position
1745 * Failure : -EINVAL
1746 */
omap_get_dma_chain_dst_pos(int chain_id)1747 int omap_get_dma_chain_dst_pos(int chain_id)
1748 {
1749 int lch;
1750 int *channels;
1751
1752 /* Check for input params */
1753 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1754 printk(KERN_ERR "Invalid chain id\n");
1755 return -EINVAL;
1756 }
1757
1758 /* Check if the chain exists */
1759 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1760 printk(KERN_ERR "Chain doesn't exists\n");
1761 return -EINVAL;
1762 }
1763
1764 channels = dma_linked_lch[chain_id].linked_dmach_q;
1765
1766 /* Get the current channel */
1767 lch = channels[dma_linked_lch[chain_id].q_head];
1768
1769 return p->dma_read(CDAC, lch);
1770 }
1771 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1772
1773 /**
1774 * @brief omap_get_dma_chain_src_pos - Get the source position
1775 * of the ongoing DMA in chain
1776 * @param chain_id
1777 *
1778 * @return - Success : Destination position
1779 * Failure : -EINVAL
1780 */
omap_get_dma_chain_src_pos(int chain_id)1781 int omap_get_dma_chain_src_pos(int chain_id)
1782 {
1783 int lch;
1784 int *channels;
1785
1786 /* Check for input params */
1787 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1788 printk(KERN_ERR "Invalid chain id\n");
1789 return -EINVAL;
1790 }
1791
1792 /* Check if the chain exists */
1793 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1794 printk(KERN_ERR "Chain doesn't exists\n");
1795 return -EINVAL;
1796 }
1797
1798 channels = dma_linked_lch[chain_id].linked_dmach_q;
1799
1800 /* Get the current channel */
1801 lch = channels[dma_linked_lch[chain_id].q_head];
1802
1803 return p->dma_read(CSAC, lch);
1804 }
1805 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1806 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1807
1808 /*----------------------------------------------------------------------------*/
1809
1810 #ifdef CONFIG_ARCH_OMAP1
1811
omap1_dma_handle_ch(int ch)1812 static int omap1_dma_handle_ch(int ch)
1813 {
1814 u32 csr;
1815
1816 if (enable_1510_mode && ch >= 6) {
1817 csr = dma_chan[ch].saved_csr;
1818 dma_chan[ch].saved_csr = 0;
1819 } else
1820 csr = p->dma_read(CSR, ch);
1821 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1822 dma_chan[ch + 6].saved_csr = csr >> 7;
1823 csr &= 0x7f;
1824 }
1825 if ((csr & 0x3f) == 0)
1826 return 0;
1827 if (unlikely(dma_chan[ch].dev_id == -1)) {
1828 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1829 "%d (CSR %04x)\n", ch, csr);
1830 return 0;
1831 }
1832 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1833 printk(KERN_WARNING "DMA timeout with device %d\n",
1834 dma_chan[ch].dev_id);
1835 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1836 printk(KERN_WARNING "DMA synchronization event drop occurred "
1837 "with device %d\n", dma_chan[ch].dev_id);
1838 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1839 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1840 if (likely(dma_chan[ch].callback != NULL))
1841 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1842
1843 return 1;
1844 }
1845
omap1_dma_irq_handler(int irq,void * dev_id)1846 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1847 {
1848 int ch = ((int) dev_id) - 1;
1849 int handled = 0;
1850
1851 for (;;) {
1852 int handled_now = 0;
1853
1854 handled_now += omap1_dma_handle_ch(ch);
1855 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1856 handled_now += omap1_dma_handle_ch(ch + 6);
1857 if (!handled_now)
1858 break;
1859 handled += handled_now;
1860 }
1861
1862 return handled ? IRQ_HANDLED : IRQ_NONE;
1863 }
1864
1865 #else
1866 #define omap1_dma_irq_handler NULL
1867 #endif
1868
1869 #ifdef CONFIG_ARCH_OMAP2PLUS
1870
omap2_dma_handle_ch(int ch)1871 static int omap2_dma_handle_ch(int ch)
1872 {
1873 u32 status = p->dma_read(CSR, ch);
1874
1875 if (!status) {
1876 if (printk_ratelimit())
1877 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1878 ch);
1879 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1880 return 0;
1881 }
1882 if (unlikely(dma_chan[ch].dev_id == -1)) {
1883 if (printk_ratelimit())
1884 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1885 "channel %d\n", status, ch);
1886 return 0;
1887 }
1888 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1889 printk(KERN_INFO
1890 "DMA synchronization event drop occurred with device "
1891 "%d\n", dma_chan[ch].dev_id);
1892 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1893 printk(KERN_INFO "DMA transaction error with device %d\n",
1894 dma_chan[ch].dev_id);
1895 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1896 u32 ccr;
1897
1898 ccr = p->dma_read(CCR, ch);
1899 ccr &= ~OMAP_DMA_CCR_EN;
1900 p->dma_write(ccr, CCR, ch);
1901 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1902 }
1903 }
1904 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1905 printk(KERN_INFO "DMA secure error with device %d\n",
1906 dma_chan[ch].dev_id);
1907 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1908 printk(KERN_INFO "DMA misaligned error with device %d\n",
1909 dma_chan[ch].dev_id);
1910
1911 p->dma_write(status, CSR, ch);
1912 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1913 /* read back the register to flush the write */
1914 p->dma_read(IRQSTATUS_L0, ch);
1915
1916 /* If the ch is not chained then chain_id will be -1 */
1917 if (dma_chan[ch].chain_id != -1) {
1918 int chain_id = dma_chan[ch].chain_id;
1919 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1920 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1921 dma_chan[dma_chan[ch].next_linked_ch].state =
1922 DMA_CH_STARTED;
1923 if (dma_linked_lch[chain_id].chain_mode ==
1924 OMAP_DMA_DYNAMIC_CHAIN)
1925 disable_lnk(ch);
1926
1927 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1928 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1929
1930 status = p->dma_read(CSR, ch);
1931 p->dma_write(status, CSR, ch);
1932 }
1933
1934 if (likely(dma_chan[ch].callback != NULL))
1935 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1936
1937 return 0;
1938 }
1939
1940 /* STATUS register count is from 1-32 while our is 0-31 */
omap2_dma_irq_handler(int irq,void * dev_id)1941 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1942 {
1943 u32 val, enable_reg;
1944 int i;
1945
1946 val = p->dma_read(IRQSTATUS_L0, 0);
1947 if (val == 0) {
1948 if (printk_ratelimit())
1949 printk(KERN_WARNING "Spurious DMA IRQ\n");
1950 return IRQ_HANDLED;
1951 }
1952 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1953 val &= enable_reg; /* Dispatch only relevant interrupts */
1954 for (i = 0; i < dma_lch_count && val != 0; i++) {
1955 if (val & 1)
1956 omap2_dma_handle_ch(i);
1957 val >>= 1;
1958 }
1959
1960 return IRQ_HANDLED;
1961 }
1962
1963 static struct irqaction omap24xx_dma_irq = {
1964 .name = "DMA",
1965 .handler = omap2_dma_irq_handler,
1966 .flags = IRQF_DISABLED
1967 };
1968
1969 #else
1970 static struct irqaction omap24xx_dma_irq;
1971 #endif
1972
1973 /*----------------------------------------------------------------------------*/
1974
omap_dma_global_context_save(void)1975 void omap_dma_global_context_save(void)
1976 {
1977 omap_dma_global_context.dma_irqenable_l0 =
1978 p->dma_read(IRQENABLE_L0, 0);
1979 omap_dma_global_context.dma_ocp_sysconfig =
1980 p->dma_read(OCP_SYSCONFIG, 0);
1981 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1982 }
1983
omap_dma_global_context_restore(void)1984 void omap_dma_global_context_restore(void)
1985 {
1986 int ch;
1987
1988 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1989 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1990 OCP_SYSCONFIG, 0);
1991 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1992 IRQENABLE_L0, 0);
1993
1994 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1995 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1996
1997 for (ch = 0; ch < dma_chan_count; ch++)
1998 if (dma_chan[ch].dev_id != -1)
1999 omap_clear_dma(ch);
2000 }
2001
omap_system_dma_probe(struct platform_device * pdev)2002 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2003 {
2004 int ch, ret = 0;
2005 int dma_irq;
2006 char irq_name[4];
2007 int irq_rel;
2008
2009 p = pdev->dev.platform_data;
2010 if (!p) {
2011 dev_err(&pdev->dev, "%s: System DMA initialized without"
2012 "platform data\n", __func__);
2013 return -EINVAL;
2014 }
2015
2016 d = p->dma_attr;
2017 errata = p->errata;
2018
2019 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2020 && (omap_dma_reserve_channels <= dma_lch_count))
2021 d->lch_count = omap_dma_reserve_channels;
2022
2023 dma_lch_count = d->lch_count;
2024 dma_chan_count = dma_lch_count;
2025 dma_chan = d->chan;
2026 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2027
2028 if (cpu_class_is_omap2()) {
2029 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2030 dma_lch_count, GFP_KERNEL);
2031 if (!dma_linked_lch) {
2032 ret = -ENOMEM;
2033 goto exit_dma_lch_fail;
2034 }
2035 }
2036
2037 spin_lock_init(&dma_chan_lock);
2038 for (ch = 0; ch < dma_chan_count; ch++) {
2039 omap_clear_dma(ch);
2040 if (cpu_class_is_omap2())
2041 omap2_disable_irq_lch(ch);
2042
2043 dma_chan[ch].dev_id = -1;
2044 dma_chan[ch].next_lch = -1;
2045
2046 if (ch >= 6 && enable_1510_mode)
2047 continue;
2048
2049 if (cpu_class_is_omap1()) {
2050 /*
2051 * request_irq() doesn't like dev_id (ie. ch) being
2052 * zero, so we have to kludge around this.
2053 */
2054 sprintf(&irq_name[0], "%d", ch);
2055 dma_irq = platform_get_irq_byname(pdev, irq_name);
2056
2057 if (dma_irq < 0) {
2058 ret = dma_irq;
2059 goto exit_dma_irq_fail;
2060 }
2061
2062 /* INT_DMA_LCD is handled in lcd_dma.c */
2063 if (dma_irq == INT_DMA_LCD)
2064 continue;
2065
2066 ret = request_irq(dma_irq,
2067 omap1_dma_irq_handler, 0, "DMA",
2068 (void *) (ch + 1));
2069 if (ret != 0)
2070 goto exit_dma_irq_fail;
2071 }
2072 }
2073
2074 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2075 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2076 DMA_DEFAULT_FIFO_DEPTH, 0);
2077
2078 if (cpu_class_is_omap2()) {
2079 strcpy(irq_name, "0");
2080 dma_irq = platform_get_irq_byname(pdev, irq_name);
2081 if (dma_irq < 0) {
2082 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2083 goto exit_dma_lch_fail;
2084 }
2085 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2086 if (ret) {
2087 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2088 "for DMA (error %d)\n", dma_irq, ret);
2089 goto exit_dma_lch_fail;
2090 }
2091 }
2092
2093 /* reserve dma channels 0 and 1 in high security devices */
2094 if (cpu_is_omap34xx() &&
2095 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2096 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2097 "HS ROM code\n");
2098 dma_chan[0].dev_id = 0;
2099 dma_chan[1].dev_id = 1;
2100 }
2101 p->show_dma_caps();
2102 return 0;
2103
2104 exit_dma_irq_fail:
2105 dev_err(&pdev->dev, "unable to request IRQ %d"
2106 "for DMA (error %d)\n", dma_irq, ret);
2107 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2108 dma_irq = platform_get_irq(pdev, irq_rel);
2109 free_irq(dma_irq, (void *)(irq_rel + 1));
2110 }
2111
2112 exit_dma_lch_fail:
2113 kfree(p);
2114 kfree(d);
2115 kfree(dma_chan);
2116 return ret;
2117 }
2118
omap_system_dma_remove(struct platform_device * pdev)2119 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2120 {
2121 int dma_irq;
2122
2123 if (cpu_class_is_omap2()) {
2124 char irq_name[4];
2125 strcpy(irq_name, "0");
2126 dma_irq = platform_get_irq_byname(pdev, irq_name);
2127 remove_irq(dma_irq, &omap24xx_dma_irq);
2128 } else {
2129 int irq_rel = 0;
2130 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2131 dma_irq = platform_get_irq(pdev, irq_rel);
2132 free_irq(dma_irq, (void *)(irq_rel + 1));
2133 }
2134 }
2135 kfree(p);
2136 kfree(d);
2137 kfree(dma_chan);
2138 return 0;
2139 }
2140
2141 static struct platform_driver omap_system_dma_driver = {
2142 .probe = omap_system_dma_probe,
2143 .remove = __devexit_p(omap_system_dma_remove),
2144 .driver = {
2145 .name = "omap_dma_system"
2146 },
2147 };
2148
omap_system_dma_init(void)2149 static int __init omap_system_dma_init(void)
2150 {
2151 return platform_driver_register(&omap_system_dma_driver);
2152 }
2153 arch_initcall(omap_system_dma_init);
2154
omap_system_dma_exit(void)2155 static void __exit omap_system_dma_exit(void)
2156 {
2157 platform_driver_unregister(&omap_system_dma_driver);
2158 }
2159
2160 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2161 MODULE_LICENSE("GPL");
2162 MODULE_ALIAS("platform:" DRIVER_NAME);
2163 MODULE_AUTHOR("Texas Instruments Inc");
2164
2165 /*
2166 * Reserve the omap SDMA channels using cmdline bootarg
2167 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2168 */
omap_dma_cmdline_reserve_ch(char * str)2169 static int __init omap_dma_cmdline_reserve_ch(char *str)
2170 {
2171 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2172 omap_dma_reserve_channels = 0;
2173 return 1;
2174 }
2175
2176 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2177
2178
2179