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Searched refs:REG_READ (Results 1 – 25 of 126) sorted by relevance

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/linux-3.4.99/drivers/gpu/drm/gma500/
Dcdv_device.c46 REG_READ(vga_reg); in cdv_disable_vga()
59 if (REG_READ(SDVOB) & SDVO_DETECTED) in cdv_output_init()
61 if (REG_READ(SDVOC) & SDVO_DETECTED) in cdv_output_init()
258 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
259 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); in cdv_save_display_registers()
261 regs->cdv.saveDSPARB = REG_READ(DSPARB); in cdv_save_display_registers()
262 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); in cdv_save_display_registers()
263 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); in cdv_save_display_registers()
264 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); in cdv_save_display_registers()
265 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); in cdv_save_display_registers()
[all …]
Dcdv_intel_display.c139 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
151 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
157 *val = REG_READ(SB_DATA); in cdv_sb_read()
174 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
187 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
208 REG_READ(DPIO_CFG); in cdv_sb_reset()
231 if ((REG_READ(dpll_reg) & DPLL_SYNCLOCK_ENABLE) == 0) { in cdv_dpll_set_clock_cdv()
430 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { in cdv_intel_find_best_PLL()
437 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == in cdv_intel_find_best_PLL()
514 dspcntr = REG_READ(dspcntr_reg); in cdv_intel_pipe_set_base()
[all …]
Dmdfld_intel_display.c76 temp = REG_READ(pipeconf_reg); in mdfldWaitForPipeDisable()
107 temp = REG_READ(pipeconf_reg); in mdfldWaitForPipeEnable()
140 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
158 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_plane_set_alpha()
246 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_pipe_set_base()
269 REG_READ(dsplinoff); in mdfld__intel_pipe_set_base()
271 REG_READ(dspsurf); in mdfld__intel_pipe_set_base()
318 temp = REG_READ(dspcntr_reg); in mdfld_disable_crtc()
323 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in mdfld_disable_crtc()
324 REG_READ(dspbase_reg); in mdfld_disable_crtc()
[all …]
Doaktrail_crtc.c184 temp = REG_READ(dpll_reg); in oaktrail_crtc_dpms()
187 REG_READ(dpll_reg); in oaktrail_crtc_dpms()
191 REG_READ(dpll_reg); in oaktrail_crtc_dpms()
195 REG_READ(dpll_reg); in oaktrail_crtc_dpms()
200 temp = REG_READ(pipeconf_reg); in oaktrail_crtc_dpms()
204 temp = REG_READ(dspcntr_reg); in oaktrail_crtc_dpms()
209 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in oaktrail_crtc_dpms()
226 temp = REG_READ(dspcntr_reg); in oaktrail_crtc_dpms()
231 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in oaktrail_crtc_dpms()
232 REG_READ(dspbase_reg); in oaktrail_crtc_dpms()
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Dpsb_intel_display.c278 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { in psb_intel_find_best_PLL()
285 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == in psb_intel_find_best_PLL()
372 dspcntr = REG_READ(dspcntr_reg); in psb_intel_pipe_set_base()
400 REG_READ(dspbase); in psb_intel_pipe_set_base()
402 REG_READ(dspsurf); in psb_intel_pipe_set_base()
405 REG_READ(dspbase); in psb_intel_pipe_set_base()
445 temp = REG_READ(dpll_reg); in psb_intel_crtc_dpms()
448 REG_READ(dpll_reg); in psb_intel_crtc_dpms()
452 REG_READ(dpll_reg); in psb_intel_crtc_dpms()
456 REG_READ(dpll_reg); in psb_intel_crtc_dpms()
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Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
246 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
275 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
276 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
277 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
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Dintel_gmbus.c106 reserved = REG_READ(gpio->reg) & in get_reserved()
121 return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; in get_clock()
132 return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0; in get_data()
150 REG_READ(gpio->reg); /* Posting */ in set_clock()
168 REG_READ(gpio->reg); in set_data()
276 REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
280 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50)) in gmbus_xfer()
282 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) in gmbus_xfer()
285 val = REG_READ(GMBUS3 + reg_offset); in gmbus_xfer()
305 REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
[all …]
Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
42 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
50 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
52 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
Dcdv_intel_crt.c45 temp = REG_READ(reg); in cdv_intel_crt_dpms()
127 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
163 adpa_orig = REG_READ(ADPA); in cdv_intel_crt_detect_hotplug()
173 hotplug_en = REG_READ(PORT_HOTPLUG_EN); in cdv_intel_crt_detect_hotplug()
187 if (!(REG_READ(PORT_HOTPLUG_EN) & in cdv_intel_crt_detect_hotplug()
194 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != in cdv_intel_crt_detect_hotplug()
Dmdfld_dsi_dpi.c46 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { in mdfld_wait_for_HS_DATA_FIFO()
63 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) in mdfld_wait_for_HS_CTRL_FIFO()
80 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & in mdfld_wait_for_DPI_CTRL_FIFO()
98 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) in mdfld_wait_for_SPL_PKG_SENT()
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
158 REG_READ(dspbase_reg); in dsi_set_pipe_plane_enable_state()
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
583 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
[all …]
Dintel_i2c.c39 val = REG_READ(chan->reg); in get_clock()
49 val = REG_READ(chan->reg); in get_data()
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
/linux-3.4.99/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c90 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
125 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
127 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
129 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
144 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
146 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
148 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
168 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
170 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
Dar9002_mac.c42 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { in ar9002_hw_get_isr()
43 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9002_hw_get_isr()
45 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
49 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & in ar9002_hw_get_isr()
58 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
64 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
87 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
108 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
109 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
111 s0_s = REG_READ(ah, AR_ISR_S0); in ar9002_hw_get_isr()
[all …]
Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
640 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
697 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
701 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
717 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
718 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
719 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
/linux-3.4.99/drivers/net/wireless/ath/
Dhw.c23 #define REG_READ (common->ops->read) macro
145 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
146 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
147 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
148 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()
/linux-3.4.99/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dmarb_bar_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
300 REG_READ( reg_##scope##_##reg, \
312 REG_READ( reg_##scope##_##reg, \
326 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
336 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dstrmux_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-3.4.99/arch/cris/include/arch-v32/arch/hwregs/
Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
278 REG_READ( reg_##scope##_##reg, \
290 REG_READ( reg_##scope##_##reg, \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dirq_nmi_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dstrcop_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-3.4.99/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
278 REG_READ( reg_##scope##_##reg, \
290 REG_READ( reg_##scope##_##reg, \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
Dstrmux_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-3.4.99/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-3.4.99/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \

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