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Searched refs:REG_GET (Results 1 – 6 of 6) sorted by relevance

/linux-3.4.99/drivers/video/omap2/dss/
Dti_hdmi_4xxx_ip.c78 while (val != REG_GET(base_addr, idx, b2, b1)) { in hdmi_wait_for_bit_change()
336 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
408 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
413 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
422 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
429 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
437 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
1208 r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0); in hdmi_config_audio_acr()
Ddispc.c72 #define REG_GET(idx, start, end) \ macro
462 return REG_GET(DISPC_CONTROL2, bit, bit) == 1; in dispc_mgr_go_busy()
464 return REG_GET(DISPC_CONTROL, bit, bit) == 1; in dispc_mgr_go_busy()
479 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; in dispc_mgr_go()
481 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; in dispc_mgr_go()
492 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; in dispc_mgr_go()
494 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; in dispc_mgr_go()
1014 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end); in dispc_read_plane_fifo_sizes()
1043 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1045 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
[all …]
Ddsi.c110 #define REG_GET(dsidev, idx, start, end) \ macro
425 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
432 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
2059 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2608 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2619 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2639 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2666 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2682 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2833 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
[all …]
Ddss.c59 #define REG_GET(idx, start, end) \ macro
654 return REG_GET(DSS_CONTROL, 15, 15); in dss_get_hdmi_venc_clk_source()
Dti_hdmi_4xxx_ip.h190 #define REG_GET(base, idx, start, end) \ macro
/linux-3.4.99/drivers/gpu/drm/radeon/
Dradeon.h1588 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro