1 /******************************************************************************
2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3  *
4  * This program is distributed in the hope that it will be useful, but WITHOUT
5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
7  * more details.
8  *
9  * You should have received a copy of the GNU General Public License along with
10  * this program; if not, write to the Free Software Foundation, Inc.,
11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12  *
13  * The full GNU General Public License is included in this distribution in the
14  * file called LICENSE.
15  *
16  * Contact Information:
17  * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
19 
20 
21 #ifndef R8190P_DEF_H
22 #define R8190P_DEF_H
23 
24 #include <linux/types.h>
25 
26 #define		MAX_SILENT_RESET_RX_SLOT_NUM	10
27 
28 #define RX_MPDU_QUEUE				0
29 #define RX_CMD_QUEUE				1
30 
31 
32 enum rtl819x_loopback {
33 	RTL819X_NO_LOOPBACK = 0,
34 	RTL819X_MAC_LOOPBACK = 1,
35 	RTL819X_DMA_LOOPBACK = 2,
36 	RTL819X_CCK_LOOPBACK = 3,
37 };
38 
39 
40 #define RESET_DELAY_8185			20
41 
42 #define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
43 
44 #define DESC90_RATE1M				0x00
45 #define DESC90_RATE2M				0x01
46 #define DESC90_RATE5_5M				0x02
47 #define DESC90_RATE11M				0x03
48 #define DESC90_RATE6M				0x04
49 #define DESC90_RATE9M				0x05
50 #define DESC90_RATE12M				0x06
51 #define DESC90_RATE18M				0x07
52 #define DESC90_RATE24M				0x08
53 #define DESC90_RATE36M				0x09
54 #define DESC90_RATE48M				0x0a
55 #define DESC90_RATE54M				0x0b
56 #define DESC90_RATEMCS0				0x00
57 #define DESC90_RATEMCS1				0x01
58 #define DESC90_RATEMCS2				0x02
59 #define DESC90_RATEMCS3				0x03
60 #define DESC90_RATEMCS4				0x04
61 #define DESC90_RATEMCS5				0x05
62 #define DESC90_RATEMCS6				0x06
63 #define DESC90_RATEMCS7				0x07
64 #define DESC90_RATEMCS8				0x08
65 #define DESC90_RATEMCS9				0x09
66 #define DESC90_RATEMCS10			0x0a
67 #define DESC90_RATEMCS11			0x0b
68 #define DESC90_RATEMCS12			0x0c
69 #define DESC90_RATEMCS13			0x0d
70 #define DESC90_RATEMCS14			0x0e
71 #define DESC90_RATEMCS15			0x0f
72 #define DESC90_RATEMCS32			0x20
73 
74 #define SHORT_SLOT_TIME				9
75 #define NON_SHORT_SLOT_TIME		20
76 
77 
78 #define	MAX_LINES_HWCONFIG_TXT			1000
79 #define MAX_BYTES_LINE_HWCONFIG_TXT		128
80 
81 #define SW_THREE_WIRE			0
82 #define HW_THREE_WIRE			2
83 
84 #define BT_DEMO_BOARD			0
85 #define BT_QA_BOARD				1
86 #define BT_FPGA					2
87 
88 #define	RX_SMOOTH				20
89 
90 #define QSLT_BK					0x1
91 #define QSLT_BE					0x0
92 #define QSLT_VI					0x4
93 #define QSLT_VO					0x6
94 #define	QSLT_BEACON			0x10
95 #define	QSLT_HIGH				0x11
96 #define	QSLT_MGNT				0x12
97 #define	QSLT_CMD				0x13
98 
99 #define NUM_OF_FIRMWARE_QUEUE				10
100 #define NUM_OF_PAGES_IN_FW					0x100
101 #define NUM_OF_PAGE_IN_FW_QUEUE_BK		0x007
102 #define NUM_OF_PAGE_IN_FW_QUEUE_BE		0x0aa
103 #define NUM_OF_PAGE_IN_FW_QUEUE_VI		0x024
104 #define NUM_OF_PAGE_IN_FW_QUEUE_VO		0x007
105 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA		0
106 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD		0x2
107 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT		0x10
108 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH		0
109 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN		0x4
110 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB		0xd
111 
112 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM	0x026
113 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM	0x048
114 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM	0x048
115 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM	0x026
116 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM	0x00
117 
118 #define APPLIED_RESERVED_QUEUE_IN_FW		0x80000000
119 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT		0x00
120 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT		0x08
121 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT		0x10
122 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT		0x18
123 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT	0x10
124 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT		0x00
125 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT		0x08
126 
127 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE	0
128 #define HAL_PRIME_CHNL_OFFSET_LOWER		1
129 #define HAL_PRIME_CHNL_OFFSET_UPPER		2
130 
131 
132 enum version_8190_loopback {
133 	VERSION_8190_BD = 0x3,
134 	VERSION_8190_BE
135 };
136 
137 #define IC_VersionCut_C	0x2
138 #define IC_VersionCut_D	0x3
139 #define IC_VersionCut_E	0x4
140 
141 enum rf_optype {
142 	RF_OP_By_SW_3wire = 0,
143 	RF_OP_By_FW,
144 	RF_OP_MAX
145 };
146 
147 
148 enum power_save_mode {
149 	POWER_SAVE_MODE_ACTIVE,
150 	POWER_SAVE_MODE_SAVE,
151 };
152 
153 enum interface_select_8190pci {
154 	INTF_SEL1_MINICARD		= 0,
155 	INTF_SEL0_PCIE			= 1,
156 	INTF_SEL2_RSV			= 2,
157 	INTF_SEL3_RSV			= 3,
158 };
159 
160 struct bb_reg_definition {
161 	u32 rfintfs;
162 	u32 rfintfi;
163 	u32 rfintfo;
164 	u32 rfintfe;
165 	u32 rf3wireOffset;
166 	u32 rfLSSI_Select;
167 	u32 rfTxGainStage;
168 	u32 rfHSSIPara1;
169 	u32 rfHSSIPara2;
170 	u32 rfSwitchControl;
171 	u32 rfAGCControl1;
172 	u32 rfAGCControl2;
173 	u32 rfRxIQImbalance;
174 	u32 rfRxAFE;
175 	u32 rfTxIQImbalance;
176 	u32 rfTxAFE;
177 	u32 rfLSSIReadBack;
178 	u32 rfLSSIReadBackPi;
179 };
180 
181 struct tx_fwinfo {
182 	u8			TxRate:7;
183 	u8			CtsEnable:1;
184 	u8			RtsRate:7;
185 	u8			RtsEnable:1;
186 	u8			TxHT:1;
187 	u8			Short:1;
188 	u8			TxBandwidth:1;
189 	u8			TxSubCarrier:2;
190 	u8			STBC:2;
191 	u8			AllowAggregation:1;
192 	u8			RtsHT:1;
193 	u8			RtsShort:1;
194 	u8			RtsBandwidth:1;
195 	u8			RtsSubcarrier:2;
196 	u8			RtsSTBC:2;
197 	u8			EnableCPUDur:1;
198 
199 	u32			RxMF:2;
200 	u32			RxAMD:3;
201 	u32			Reserved1:3;
202 	u32			TxAGCOffset:4;
203 	u32			TxAGCSign:1;
204 	u32			Tx_INFO_RSVD:6;
205 	u32			PacketID:13;
206 };
207 
208 struct tx_fwinfo_8190pci {
209 	u8			TxRate:7;
210 	u8			CtsEnable:1;
211 	u8			RtsRate:7;
212 	u8			RtsEnable:1;
213 	u8			TxHT:1;
214 	u8			Short:1;
215 	u8			TxBandwidth:1;
216 	u8			TxSubCarrier:2;
217 	u8			STBC:2;
218 	u8			AllowAggregation:1;
219 	u8			RtsHT:1;
220 	u8			RtsShort:1;
221 	u8			RtsBandwidth:1;
222 	u8			RtsSubcarrier:2;
223 	u8			RtsSTBC:2;
224 	u8			EnableCPUDur:1;
225 
226 	u32			RxMF:2;
227 	u32			RxAMD:3;
228 	u32			TxPerPktInfoFeedback:1;
229 	u32			Reserved1:2;
230 	u32			TxAGCOffset:4;
231 	u32			TxAGCSign:1;
232 	u32			RAW_TXD:1;
233 	u32			Retry_Limit:4;
234 	u32			Reserved2:1;
235 	u32			PacketID:13;
236 
237 
238 };
239 
240 
241 #define TX_DESC_SIZE			32
242 
243 #define TX_DESC_CMD_SIZE	32
244 
245 
246 #define TX_STATUS_DESC_SIZE	32
247 
248 #define TX_FWINFO_SIZE	8
249 
250 
251 #define RX_DESC_SIZE	16
252 
253 #define RX_STATUS_DESC_SIZE	16
254 
255 #define RX_DRIVER_INFO_SIZE	8
256 
257 struct log_int_8190 {
258 	u32	nIMR_COMDOK;
259 	u32	nIMR_MGNTDOK;
260 	u32	nIMR_HIGH;
261 	u32	nIMR_VODOK;
262 	u32	nIMR_VIDOK;
263 	u32	nIMR_BEDOK;
264 	u32	nIMR_BKDOK;
265 	u32	nIMR_ROK;
266 	u32	nIMR_RCOK;
267 	u32	nIMR_TBDOK;
268 	u32	nIMR_BDOK;
269 	u32	nIMR_RXFOVW;
270 };
271 
272 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
273 	u8			reserved:4;
274 	u8			rxsc:2;
275 	u8			sgi_en:1;
276 	u8			ex_intf_flag:1;
277 };
278 
279 struct phy_sts_ofdm_819xpci {
280 	u8	trsw_gain_X[4];
281 	u8	pwdb_all;
282 	u8	cfosho_X[4];
283 	u8	cfotail_X[4];
284 	u8	rxevm_X[2];
285 	u8	rxsnr_X[4];
286 	u8	pdsnr_X[2];
287 	u8	csi_current_X[2];
288 	u8	csi_target_X[2];
289 	u8	sigevm;
290 	u8	max_ex_pwr;
291 	u8	sgi_en;
292 	u8	rxsc_sgien_exflg;
293 };
294 
295 struct phy_sts_cck_819xpci {
296 	u8	adc_pwdb_X[4];
297 	u8	sq_rpt;
298 	u8	cck_agc_rpt;
299 };
300 
301 
302 #define		PHY_RSSI_SLID_WIN_MAX				100
303 #define		PHY_Beacon_RSSI_SLID_WIN_MAX		10
304 
305 struct tx_desc {
306 	u16	PktSize;
307 	u8	Offset;
308 	u8	Reserved1:3;
309 	u8	CmdInit:1;
310 	u8	LastSeg:1;
311 	u8	FirstSeg:1;
312 	u8	LINIP:1;
313 	u8	OWN:1;
314 
315 	u8	TxFWInfoSize;
316 	u8	RATid:3;
317 	u8	DISFB:1;
318 	u8	USERATE:1;
319 	u8	MOREFRAG:1;
320 	u8	NoEnc:1;
321 	u8	PIFS:1;
322 	u8	QueueSelect:5;
323 	u8	NoACM:1;
324 	u8	Resv:2;
325 	u8	SecCAMID:5;
326 	u8	SecDescAssign:1;
327 	u8	SecType:2;
328 
329 	u16	TxBufferSize;
330 	u8	PktId:7;
331 	u8	Resv1:1;
332 	u8	Reserved2;
333 
334 	u32	TxBuffAddr;
335 
336 	u32	NextDescAddress;
337 
338 	u32	Reserved5;
339 	u32	Reserved6;
340 	u32	Reserved7;
341 };
342 
343 
344 struct tx_desc_cmd {
345 	u16	PktSize;
346 	u8	Reserved1;
347 	u8	CmdType:3;
348 	u8	CmdInit:1;
349 	u8	LastSeg:1;
350 	u8	FirstSeg:1;
351 	u8	LINIP:1;
352 	u8	OWN:1;
353 
354 	u16	ElementReport;
355 	u16	Reserved2;
356 
357 	u16	TxBufferSize;
358 	u16	Reserved3;
359 
360 	u32	TxBuffAddr;
361 	u32	NextDescAddress;
362 	u32	Reserved4;
363 	u32	Reserved5;
364 	u32	Reserved6;
365 };
366 
367 struct rx_desc {
368 	u16			Length:14;
369 	u16			CRC32:1;
370 	u16			ICV:1;
371 	u8			RxDrvInfoSize;
372 	u8			Shift:2;
373 	u8			PHYStatus:1;
374 	u8			SWDec:1;
375 	u8			LastSeg:1;
376 	u8			FirstSeg:1;
377 	u8			EOR:1;
378 	u8			OWN:1;
379 
380 	u32			Reserved2;
381 
382 	u32			Reserved3;
383 
384 	u32	BufferAddress;
385 
386 };
387 
388 
389 struct rx_fwinfo {
390 	u16			Reserved1:12;
391 	u16			PartAggr:1;
392 	u16			FirstAGGR:1;
393 	u16			Reserved2:2;
394 
395 	u8			RxRate:7;
396 	u8			RxHT:1;
397 
398 	u8			BW:1;
399 	u8			SPLCP:1;
400 	u8			Reserved3:2;
401 	u8			PAM:1;
402 	u8			Mcast:1;
403 	u8			Bcast:1;
404 	u8			Reserved4:1;
405 
406 	u32			TSFL;
407 
408 };
409 
410 #endif
411