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Searched refs:PLLX (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-tegra/
Dclock.h44 #define PLLX (1 << 15) macro
Dtegra30_clocks.c612 if (!(c->parent->flags & PLLX)) in tegra30_super_clk_init()
646 if ((c->flags & DIV_2) && (p->flags & PLLX) && in tegra30_super_clk_set_parent()
648 if (c->parent->flags & PLLX) in tegra30_super_clk_set_parent()
660 if (!(p->flags & PLLX)) { in tegra30_super_clk_set_parent()
1089 } else if (c->flags & (PLLX | PLLM)) { in tegra30_pll_clk_set_rate()
1283 if (c->flags & (PLLD | PLLX)) { in tegra30_pll_div_clk_init()
2429 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
2449 .flags = DIV_2 | PLLX,