1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_REGS_H 36 #define __T4_REGS_H 37 38 #define MYPF_BASE 0x1b000 39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) 40 41 #define PF0_BASE 0x1e000 42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) 43 44 #define PF_STRIDE 0x400 45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE) 46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) 47 48 #define MYPORT_BASE 0x1c000 49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr)) 50 51 #define PORT0_BASE 0x20000 52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr)) 53 54 #define PORT_STRIDE 0x2000 55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) 56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) 57 58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) 59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) 60 61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) 63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) 65 66 #define SGE_PF_KDOORBELL 0x0 67 #define QID_MASK 0xffff8000U 68 #define QID_SHIFT 15 69 #define QID(x) ((x) << QID_SHIFT) 70 #define DBPRIO 0x00004000U 71 #define PIDX_MASK 0x00003fffU 72 #define PIDX_SHIFT 0 73 #define PIDX(x) ((x) << PIDX_SHIFT) 74 75 #define SGE_PF_GTS 0x4 76 #define INGRESSQID_MASK 0xffff0000U 77 #define INGRESSQID_SHIFT 16 78 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT) 79 #define TIMERREG_MASK 0x0000e000U 80 #define TIMERREG_SHIFT 13 81 #define TIMERREG(x) ((x) << TIMERREG_SHIFT) 82 #define SEINTARM_MASK 0x00001000U 83 #define SEINTARM_SHIFT 12 84 #define SEINTARM(x) ((x) << SEINTARM_SHIFT) 85 #define CIDXINC_MASK 0x00000fffU 86 #define CIDXINC_SHIFT 0 87 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) 88 89 #define SGE_CONTROL 0x1008 90 #define DCASYSTYPE 0x00080000U 91 #define RXPKTCPLMODE 0x00040000U 92 #define EGRSTATUSPAGESIZE 0x00020000U 93 #define PKTSHIFT_MASK 0x00001c00U 94 #define PKTSHIFT_SHIFT 10 95 #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT) 96 #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT) 97 #define INGPCIEBOUNDARY_MASK 0x00000380U 98 #define INGPCIEBOUNDARY_SHIFT 7 99 #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT) 100 #define INGPADBOUNDARY_MASK 0x00000070U 101 #define INGPADBOUNDARY_SHIFT 4 102 #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT) 103 #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \ 104 >> INGPADBOUNDARY_SHIFT) 105 #define EGRPCIEBOUNDARY_MASK 0x0000000eU 106 #define EGRPCIEBOUNDARY_SHIFT 1 107 #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT) 108 #define GLOBALENABLE 0x00000001U 109 110 #define SGE_HOST_PAGE_SIZE 0x100c 111 #define HOSTPAGESIZEPF0_MASK 0x0000000fU 112 #define HOSTPAGESIZEPF0_SHIFT 0 113 #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT) 114 115 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010 116 #define QUEUESPERPAGEPF0_MASK 0x0000000fU 117 #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK) 118 119 #define SGE_INT_CAUSE1 0x1024 120 #define SGE_INT_CAUSE2 0x1030 121 #define SGE_INT_CAUSE3 0x103c 122 #define ERR_FLM_DBP 0x80000000U 123 #define ERR_FLM_IDMA1 0x40000000U 124 #define ERR_FLM_IDMA0 0x20000000U 125 #define ERR_FLM_HINT 0x10000000U 126 #define ERR_PCIE_ERROR3 0x08000000U 127 #define ERR_PCIE_ERROR2 0x04000000U 128 #define ERR_PCIE_ERROR1 0x02000000U 129 #define ERR_PCIE_ERROR0 0x01000000U 130 #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U 131 #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U 132 #define ERR_INVALID_CIDX_INC 0x00200000U 133 #define ERR_ITP_TIME_PAUSED 0x00100000U 134 #define ERR_CPL_OPCODE_0 0x00080000U 135 #define ERR_DROPPED_DB 0x00040000U 136 #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U 137 #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U 138 #define ERR_BAD_DB_PIDX3 0x00008000U 139 #define ERR_BAD_DB_PIDX2 0x00004000U 140 #define ERR_BAD_DB_PIDX1 0x00002000U 141 #define ERR_BAD_DB_PIDX0 0x00001000U 142 #define ERR_ING_PCIE_CHAN 0x00000800U 143 #define ERR_ING_CTXT_PRIO 0x00000400U 144 #define ERR_EGR_CTXT_PRIO 0x00000200U 145 #define DBFIFO_HP_INT 0x00000100U 146 #define DBFIFO_LP_INT 0x00000080U 147 #define REG_ADDRESS_ERR 0x00000040U 148 #define INGRESS_SIZE_ERR 0x00000020U 149 #define EGRESS_SIZE_ERR 0x00000010U 150 #define ERR_INV_CTXT3 0x00000008U 151 #define ERR_INV_CTXT2 0x00000004U 152 #define ERR_INV_CTXT1 0x00000002U 153 #define ERR_INV_CTXT0 0x00000001U 154 155 #define SGE_INT_ENABLE3 0x1040 156 #define SGE_FL_BUFFER_SIZE0 0x1044 157 #define SGE_FL_BUFFER_SIZE1 0x1048 158 #define SGE_INGRESS_RX_THRESHOLD 0x10a0 159 #define THRESHOLD_0_MASK 0x3f000000U 160 #define THRESHOLD_0_SHIFT 24 161 #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT) 162 #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT) 163 #define THRESHOLD_1_MASK 0x003f0000U 164 #define THRESHOLD_1_SHIFT 16 165 #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT) 166 #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT) 167 #define THRESHOLD_2_MASK 0x00003f00U 168 #define THRESHOLD_2_SHIFT 8 169 #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT) 170 #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT) 171 #define THRESHOLD_3_MASK 0x0000003fU 172 #define THRESHOLD_3_SHIFT 0 173 #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT) 174 #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT) 175 176 #define SGE_TIMER_VALUE_0_AND_1 0x10b8 177 #define TIMERVALUE0_MASK 0xffff0000U 178 #define TIMERVALUE0_SHIFT 16 179 #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT) 180 #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT) 181 #define TIMERVALUE1_MASK 0x0000ffffU 182 #define TIMERVALUE1_SHIFT 0 183 #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT) 184 #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT) 185 186 #define SGE_TIMER_VALUE_2_AND_3 0x10bc 187 #define SGE_TIMER_VALUE_4_AND_5 0x10c0 188 #define SGE_DEBUG_INDEX 0x10cc 189 #define SGE_DEBUG_DATA_HIGH 0x10d0 190 #define SGE_DEBUG_DATA_LOW 0x10d4 191 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 192 193 #define PCIE_PF_CLI 0x44 194 #define PCIE_INT_CAUSE 0x3004 195 #define UNXSPLCPLERR 0x20000000U 196 #define PCIEPINT 0x10000000U 197 #define PCIESINT 0x08000000U 198 #define RPLPERR 0x04000000U 199 #define RXWRPERR 0x02000000U 200 #define RXCPLPERR 0x01000000U 201 #define PIOTAGPERR 0x00800000U 202 #define MATAGPERR 0x00400000U 203 #define INTXCLRPERR 0x00200000U 204 #define FIDPERR 0x00100000U 205 #define CFGSNPPERR 0x00080000U 206 #define HRSPPERR 0x00040000U 207 #define HREQPERR 0x00020000U 208 #define HCNTPERR 0x00010000U 209 #define DRSPPERR 0x00008000U 210 #define DREQPERR 0x00004000U 211 #define DCNTPERR 0x00002000U 212 #define CRSPPERR 0x00001000U 213 #define CREQPERR 0x00000800U 214 #define CCNTPERR 0x00000400U 215 #define TARTAGPERR 0x00000200U 216 #define PIOREQPERR 0x00000100U 217 #define PIOCPLPERR 0x00000080U 218 #define MSIXDIPERR 0x00000040U 219 #define MSIXDATAPERR 0x00000020U 220 #define MSIXADDRHPERR 0x00000010U 221 #define MSIXADDRLPERR 0x00000008U 222 #define MSIDATAPERR 0x00000004U 223 #define MSIADDRHPERR 0x00000002U 224 #define MSIADDRLPERR 0x00000001U 225 226 #define PCIE_NONFAT_ERR 0x3010 227 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068 228 #define PCIEOFST_MASK 0xfffffc00U 229 #define BIR_MASK 0x00000300U 230 #define BIR_SHIFT 8 231 #define BIR(x) ((x) << BIR_SHIFT) 232 #define WINDOW_MASK 0x000000ffU 233 #define WINDOW_SHIFT 0 234 #define WINDOW(x) ((x) << WINDOW_SHIFT) 235 #define PCIE_MEM_ACCESS_OFFSET 0x306c 236 237 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 238 #define RNPP 0x80000000U 239 #define RPCP 0x20000000U 240 #define RCIP 0x08000000U 241 #define RCCP 0x04000000U 242 #define RFTP 0x00800000U 243 #define PTRP 0x00100000U 244 245 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4 246 #define TPCP 0x40000000U 247 #define TNPP 0x20000000U 248 #define TFTP 0x10000000U 249 #define TCAP 0x08000000U 250 #define TCIP 0x04000000U 251 #define RCAP 0x02000000U 252 #define PLUP 0x00800000U 253 #define PLDN 0x00400000U 254 #define OTDD 0x00200000U 255 #define GTRP 0x00100000U 256 #define RDPE 0x00040000U 257 #define TDCE 0x00020000U 258 #define TDUE 0x00010000U 259 260 #define MC_INT_CAUSE 0x7518 261 #define ECC_UE_INT_CAUSE 0x00000004U 262 #define ECC_CE_INT_CAUSE 0x00000002U 263 #define PERR_INT_CAUSE 0x00000001U 264 265 #define MC_ECC_STATUS 0x751c 266 #define ECC_CECNT_MASK 0xffff0000U 267 #define ECC_CECNT_SHIFT 16 268 #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 269 #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT) 270 #define ECC_UECNT_MASK 0x0000ffffU 271 #define ECC_UECNT_SHIFT 0 272 #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT) 273 #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT) 274 275 #define MC_BIST_CMD 0x7600 276 #define START_BIST 0x80000000U 277 #define BIST_CMD_GAP_MASK 0x0000ff00U 278 #define BIST_CMD_GAP_SHIFT 8 279 #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT) 280 #define BIST_OPCODE_MASK 0x00000003U 281 #define BIST_OPCODE_SHIFT 0 282 #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT) 283 284 #define MC_BIST_CMD_ADDR 0x7604 285 #define MC_BIST_CMD_LEN 0x7608 286 #define MC_BIST_DATA_PATTERN 0x760c 287 #define BIST_DATA_TYPE_MASK 0x0000000fU 288 #define BIST_DATA_TYPE_SHIFT 0 289 #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT) 290 291 #define MC_BIST_STATUS_RDATA 0x7688 292 293 #define MA_EXT_MEMORY_BAR 0x77c8 294 #define EXT_MEM_SIZE_MASK 0x00000fffU 295 #define EXT_MEM_SIZE_SHIFT 0 296 #define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT) 297 298 #define MA_TARGET_MEM_ENABLE 0x77d8 299 #define EXT_MEM_ENABLE 0x00000004U 300 #define EDRAM1_ENABLE 0x00000002U 301 #define EDRAM0_ENABLE 0x00000001U 302 303 #define MA_INT_CAUSE 0x77e0 304 #define MEM_PERR_INT_CAUSE 0x00000002U 305 #define MEM_WRAP_INT_CAUSE 0x00000001U 306 307 #define MA_INT_WRAP_STATUS 0x77e4 308 #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U 309 #define MEM_WRAP_ADDRESS_SHIFT 4 310 #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT) 311 #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU 312 #define MEM_WRAP_CLIENT_NUM_SHIFT 0 313 #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT) 314 315 #define MA_PARITY_ERROR_STATUS 0x77f4 316 317 #define EDC_0_BASE_ADDR 0x7900 318 319 #define EDC_BIST_CMD 0x7904 320 #define EDC_BIST_CMD_ADDR 0x7908 321 #define EDC_BIST_CMD_LEN 0x790c 322 #define EDC_BIST_DATA_PATTERN 0x7910 323 #define EDC_BIST_STATUS_RDATA 0x7928 324 #define EDC_INT_CAUSE 0x7978 325 #define ECC_UE_PAR 0x00000020U 326 #define ECC_CE_PAR 0x00000010U 327 #define PERR_PAR_CAUSE 0x00000008U 328 329 #define EDC_ECC_STATUS 0x797c 330 331 #define EDC_1_BASE_ADDR 0x7980 332 333 #define CIM_BOOT_CFG 0x7b00 334 #define BOOTADDR_MASK 0xffffff00U 335 336 #define CIM_PF_MAILBOX_DATA 0x240 337 #define CIM_PF_MAILBOX_CTRL 0x280 338 #define MBMSGVALID 0x00000008U 339 #define MBINTREQ 0x00000004U 340 #define MBOWNER_MASK 0x00000003U 341 #define MBOWNER_SHIFT 0 342 #define MBOWNER(x) ((x) << MBOWNER_SHIFT) 343 #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT) 344 345 #define CIM_PF_HOST_INT_CAUSE 0x28c 346 #define MBMSGRDYINT 0x00080000U 347 348 #define CIM_HOST_INT_CAUSE 0x7b2c 349 #define TIEQOUTPARERRINT 0x00100000U 350 #define TIEQINPARERRINT 0x00080000U 351 #define MBHOSTPARERR 0x00040000U 352 #define MBUPPARERR 0x00020000U 353 #define IBQPARERR 0x0001f800U 354 #define IBQTP0PARERR 0x00010000U 355 #define IBQTP1PARERR 0x00008000U 356 #define IBQULPPARERR 0x00004000U 357 #define IBQSGELOPARERR 0x00002000U 358 #define IBQSGEHIPARERR 0x00001000U 359 #define IBQNCSIPARERR 0x00000800U 360 #define OBQPARERR 0x000007e0U 361 #define OBQULP0PARERR 0x00000400U 362 #define OBQULP1PARERR 0x00000200U 363 #define OBQULP2PARERR 0x00000100U 364 #define OBQULP3PARERR 0x00000080U 365 #define OBQSGEPARERR 0x00000040U 366 #define OBQNCSIPARERR 0x00000020U 367 #define PREFDROPINT 0x00000002U 368 #define UPACCNONZERO 0x00000001U 369 370 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34 371 #define EEPROMWRINT 0x40000000U 372 #define TIMEOUTMAINT 0x20000000U 373 #define TIMEOUTINT 0x10000000U 374 #define RSPOVRLOOKUPINT 0x08000000U 375 #define REQOVRLOOKUPINT 0x04000000U 376 #define BLKWRPLINT 0x02000000U 377 #define BLKRDPLINT 0x01000000U 378 #define SGLWRPLINT 0x00800000U 379 #define SGLRDPLINT 0x00400000U 380 #define BLKWRCTLINT 0x00200000U 381 #define BLKRDCTLINT 0x00100000U 382 #define SGLWRCTLINT 0x00080000U 383 #define SGLRDCTLINT 0x00040000U 384 #define BLKWREEPROMINT 0x00020000U 385 #define BLKRDEEPROMINT 0x00010000U 386 #define SGLWREEPROMINT 0x00008000U 387 #define SGLRDEEPROMINT 0x00004000U 388 #define BLKWRFLASHINT 0x00002000U 389 #define BLKRDFLASHINT 0x00001000U 390 #define SGLWRFLASHINT 0x00000800U 391 #define SGLRDFLASHINT 0x00000400U 392 #define BLKWRBOOTINT 0x00000200U 393 #define BLKRDBOOTINT 0x00000100U 394 #define SGLWRBOOTINT 0x00000080U 395 #define SGLRDBOOTINT 0x00000040U 396 #define ILLWRBEINT 0x00000020U 397 #define ILLRDBEINT 0x00000010U 398 #define ILLRDINT 0x00000008U 399 #define ILLWRINT 0x00000004U 400 #define ILLTRANSINT 0x00000002U 401 #define RSVDSPACEINT 0x00000001U 402 403 #define TP_OUT_CONFIG 0x7d04 404 #define VLANEXTENABLE_MASK 0x0000f000U 405 #define VLANEXTENABLE_SHIFT 12 406 407 #define TP_PARA_REG2 0x7d68 408 #define MAXRXDATA_MASK 0xffff0000U 409 #define MAXRXDATA_SHIFT 16 410 #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 411 412 #define TP_TIMER_RESOLUTION 0x7d90 413 #define TIMERRESOLUTION_MASK 0x00ff0000U 414 #define TIMERRESOLUTION_SHIFT 16 415 #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 416 417 #define TP_SHIFT_CNT 0x7dc0 418 419 #define TP_CCTRL_TABLE 0x7ddc 420 #define TP_MTU_TABLE 0x7de4 421 #define MTUINDEX_MASK 0xff000000U 422 #define MTUINDEX_SHIFT 24 423 #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 424 #define MTUWIDTH_MASK 0x000f0000U 425 #define MTUWIDTH_SHIFT 16 426 #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 427 #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 428 #define MTUVALUE_MASK 0x00003fffU 429 #define MTUVALUE_SHIFT 0 430 #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 431 #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 432 433 #define TP_RSS_LKP_TABLE 0x7dec 434 #define LKPTBLROWVLD 0x80000000U 435 #define LKPTBLQUEUE1_MASK 0x000ffc00U 436 #define LKPTBLQUEUE1_SHIFT 10 437 #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 438 #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 439 #define LKPTBLQUEUE0_MASK 0x000003ffU 440 #define LKPTBLQUEUE0_SHIFT 0 441 #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 442 #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 443 444 #define TP_PIO_ADDR 0x7e40 445 #define TP_PIO_DATA 0x7e44 446 #define TP_MIB_INDEX 0x7e50 447 #define TP_MIB_DATA 0x7e54 448 #define TP_INT_CAUSE 0x7e74 449 #define FLMTXFLSTEMPTY 0x40000000U 450 451 #define TP_INGRESS_CONFIG 0x141 452 #define VNIC 0x00000800U 453 #define CSUM_HAS_PSEUDO_HDR 0x00000400U 454 #define RM_OVLAN 0x00000200U 455 #define LOOKUPEVERYPKT 0x00000100U 456 457 #define TP_MIB_MAC_IN_ERR_0 0x0 458 #define TP_MIB_TCP_OUT_RST 0xc 459 #define TP_MIB_TCP_IN_SEG_HI 0x10 460 #define TP_MIB_TCP_IN_SEG_LO 0x11 461 #define TP_MIB_TCP_OUT_SEG_HI 0x12 462 #define TP_MIB_TCP_OUT_SEG_LO 0x13 463 #define TP_MIB_TCP_RXT_SEG_HI 0x14 464 #define TP_MIB_TCP_RXT_SEG_LO 0x15 465 #define TP_MIB_TNL_CNG_DROP_0 0x18 466 #define TP_MIB_TCP_V6IN_ERR_0 0x28 467 #define TP_MIB_TCP_V6OUT_RST 0x2c 468 #define TP_MIB_OFD_ARP_DROP 0x36 469 #define TP_MIB_TNL_DROP_0 0x44 470 #define TP_MIB_OFD_VLN_DROP_0 0x58 471 472 #define ULP_TX_INT_CAUSE 0x8dcc 473 #define PBL_BOUND_ERR_CH3 0x80000000U 474 #define PBL_BOUND_ERR_CH2 0x40000000U 475 #define PBL_BOUND_ERR_CH1 0x20000000U 476 #define PBL_BOUND_ERR_CH0 0x10000000U 477 478 #define PM_RX_INT_CAUSE 0x8fdc 479 #define ZERO_E_CMD_ERROR 0x00400000U 480 #define PMRX_FRAMING_ERROR 0x003ffff0U 481 #define OCSPI_PAR_ERROR 0x00000008U 482 #define DB_OPTIONS_PAR_ERROR 0x00000004U 483 #define IESPI_PAR_ERROR 0x00000002U 484 #define E_PCMD_PAR_ERROR 0x00000001U 485 486 #define PM_TX_INT_CAUSE 0x8ffc 487 #define PCMD_LEN_OVFL0 0x80000000U 488 #define PCMD_LEN_OVFL1 0x40000000U 489 #define PCMD_LEN_OVFL2 0x20000000U 490 #define ZERO_C_CMD_ERROR 0x10000000U 491 #define PMTX_FRAMING_ERROR 0x0ffffff0U 492 #define OESPI_PAR_ERROR 0x00000008U 493 #define ICSPI_PAR_ERROR 0x00000002U 494 #define C_PCMD_PAR_ERROR 0x00000001U 495 496 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 497 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 498 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408 499 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c 500 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410 501 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414 502 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418 503 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c 504 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420 505 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424 506 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428 507 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c 508 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430 509 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434 510 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438 511 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c 512 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440 513 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444 514 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448 515 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c 516 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450 517 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454 518 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458 519 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c 520 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460 521 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464 522 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468 523 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c 524 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470 525 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474 526 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478 527 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c 528 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480 529 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484 530 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488 531 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c 532 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490 533 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494 534 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498 535 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c 536 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0 537 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4 538 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8 539 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac 540 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0 541 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4 542 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0 543 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4 544 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8 545 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc 546 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0 547 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4 548 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8 549 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc 550 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0 551 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4 552 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8 553 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec 554 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0 555 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4 556 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8 557 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc 558 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500 559 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504 560 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508 561 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c 562 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510 563 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514 564 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518 565 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c 566 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 567 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 568 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 569 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 570 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 571 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 572 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c 573 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550 574 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554 575 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558 576 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c 577 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560 578 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564 579 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568 580 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c 581 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570 582 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574 583 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578 584 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c 585 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580 586 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584 587 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588 588 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c 589 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590 590 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594 591 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598 592 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c 593 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0 594 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4 595 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8 596 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac 597 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0 598 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4 599 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8 600 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc 601 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0 602 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4 603 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8 604 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc 605 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0 606 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4 607 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8 608 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc 609 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0 610 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4 611 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8 612 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec 613 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0 614 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4 615 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8 616 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc 617 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600 618 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604 619 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608 620 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 621 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 622 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 623 #define MPS_CMN_CTL 0x9000 624 #define NUMPORTS_MASK 0x00000003U 625 #define NUMPORTS_SHIFT 0 626 #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 627 628 #define MPS_INT_CAUSE 0x9008 629 #define STATINT 0x00000020U 630 #define TXINT 0x00000010U 631 #define RXINT 0x00000008U 632 #define TRCINT 0x00000004U 633 #define CLSINT 0x00000002U 634 #define PLINT 0x00000001U 635 636 #define MPS_TX_INT_CAUSE 0x9408 637 #define PORTERR 0x00010000U 638 #define FRMERR 0x00008000U 639 #define SECNTERR 0x00004000U 640 #define BUBBLE 0x00002000U 641 #define TXDESCFIFO 0x00001e00U 642 #define TXDATAFIFO 0x000001e0U 643 #define NCSIFIFO 0x00000010U 644 #define TPFIFO 0x0000000fU 645 646 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 647 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 648 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 649 650 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 651 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 652 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 653 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c 654 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650 655 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654 656 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658 657 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c 658 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660 659 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664 660 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668 661 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c 662 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670 663 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674 664 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678 665 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c 666 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680 667 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684 668 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688 669 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c 670 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690 671 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694 672 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698 673 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c 674 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0 675 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4 676 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8 677 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac 678 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0 679 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 680 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 681 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 682 #define MPS_TRC_CFG 0x9800 683 #define TRCFIFOEMPTY 0x00000010U 684 #define TRCIGNOREDROPINPUT 0x00000008U 685 #define TRCKEEPDUPLICATES 0x00000004U 686 #define TRCEN 0x00000002U 687 #define TRCMULTIFILTER 0x00000001U 688 689 #define MPS_TRC_RSS_CONTROL 0x9808 690 #define RSSCONTROL_MASK 0x00ff0000U 691 #define RSSCONTROL_SHIFT 16 692 #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 693 #define QUEUENUMBER_MASK 0x0000ffffU 694 #define QUEUENUMBER_SHIFT 0 695 #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 696 697 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 698 #define TFINVERTMATCH 0x01000000U 699 #define TFPKTTOOLARGE 0x00800000U 700 #define TFEN 0x00400000U 701 #define TFPORT_MASK 0x003c0000U 702 #define TFPORT_SHIFT 18 703 #define TFPORT(x) ((x) << TFPORT_SHIFT) 704 #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 705 #define TFDROP 0x00020000U 706 #define TFSOPEOPERR 0x00010000U 707 #define TFLENGTH_MASK 0x00001f00U 708 #define TFLENGTH_SHIFT 8 709 #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 710 #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 711 #define TFOFFSET_MASK 0x0000001fU 712 #define TFOFFSET_SHIFT 0 713 #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 714 #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 715 716 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 717 #define TFMINPKTSIZE_MASK 0x01ff0000U 718 #define TFMINPKTSIZE_SHIFT 16 719 #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 720 #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 721 #define TFCAPTUREMAX_MASK 0x00003fffU 722 #define TFCAPTUREMAX_SHIFT 0 723 #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 724 #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 725 726 #define MPS_TRC_INT_CAUSE 0x985c 727 #define MISCPERR 0x00000100U 728 #define PKTFIFO 0x000000f0U 729 #define FILTMEM 0x0000000fU 730 731 #define MPS_TRC_FILTER0_MATCH 0x9c00 732 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 733 #define MPS_TRC_FILTER1_MATCH 0x9d00 734 #define MPS_CLS_INT_CAUSE 0xd028 735 #define PLERRENB 0x00000008U 736 #define HASHSRAM 0x00000004U 737 #define MATCHTCAM 0x00000002U 738 #define MATCHSRAM 0x00000001U 739 740 #define MPS_RX_PERR_INT_CAUSE 0x11074 741 742 #define CPL_INTR_CAUSE 0x19054 743 #define CIM_OP_MAP_PERR 0x00000020U 744 #define CIM_OVFL_ERROR 0x00000010U 745 #define TP_FRAMING_ERROR 0x00000008U 746 #define SGE_FRAMING_ERROR 0x00000004U 747 #define CIM_FRAMING_ERROR 0x00000002U 748 #define ZERO_SWITCH_ERROR 0x00000001U 749 750 #define SMB_INT_CAUSE 0x19090 751 #define MSTTXFIFOPARINT 0x00200000U 752 #define MSTRXFIFOPARINT 0x00100000U 753 #define SLVFIFOPARINT 0x00080000U 754 755 #define ULP_RX_INT_CAUSE 0x19158 756 #define ULP_RX_ISCSI_TAGMASK 0x19164 757 #define ULP_RX_ISCSI_PSZ 0x19168 758 #define HPZ3_MASK 0x0f000000U 759 #define HPZ3_SHIFT 24 760 #define HPZ3(x) ((x) << HPZ3_SHIFT) 761 #define HPZ2_MASK 0x000f0000U 762 #define HPZ2_SHIFT 16 763 #define HPZ2(x) ((x) << HPZ2_SHIFT) 764 #define HPZ1_MASK 0x00000f00U 765 #define HPZ1_SHIFT 8 766 #define HPZ1(x) ((x) << HPZ1_SHIFT) 767 #define HPZ0_MASK 0x0000000fU 768 #define HPZ0_SHIFT 0 769 #define HPZ0(x) ((x) << HPZ0_SHIFT) 770 771 #define ULP_RX_TDDP_PSZ 0x19178 772 773 #define SF_DATA 0x193f8 774 #define SF_OP 0x193fc 775 #define BUSY 0x80000000U 776 #define SF_LOCK 0x00000010U 777 #define SF_CONT 0x00000008U 778 #define BYTECNT_MASK 0x00000006U 779 #define BYTECNT_SHIFT 1 780 #define BYTECNT(x) ((x) << BYTECNT_SHIFT) 781 #define OP_WR 0x00000001U 782 783 #define PL_PF_INT_CAUSE 0x3c0 784 #define PFSW 0x00000008U 785 #define PFSGE 0x00000004U 786 #define PFCIM 0x00000002U 787 #define PFMPS 0x00000001U 788 789 #define PL_PF_INT_ENABLE 0x3c4 790 #define PL_PF_CTL 0x3c8 791 #define SWINT 0x00000001U 792 793 #define PL_WHOAMI 0x19400 794 #define SOURCEPF_MASK 0x00000700U 795 #define SOURCEPF_SHIFT 8 796 #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT) 797 #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT) 798 #define ISVF 0x00000080U 799 #define VFID_MASK 0x0000007fU 800 #define VFID_SHIFT 0 801 #define VFID(x) ((x) << VFID_SHIFT) 802 #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT) 803 804 #define PL_INT_CAUSE 0x1940c 805 #define ULP_TX 0x08000000U 806 #define SGE 0x04000000U 807 #define HMA 0x02000000U 808 #define CPL_SWITCH 0x01000000U 809 #define ULP_RX 0x00800000U 810 #define PM_RX 0x00400000U 811 #define PM_TX 0x00200000U 812 #define MA 0x00100000U 813 #define TP 0x00080000U 814 #define LE 0x00040000U 815 #define EDC1 0x00020000U 816 #define EDC0 0x00010000U 817 #define MC 0x00008000U 818 #define PCIE 0x00004000U 819 #define PMU 0x00002000U 820 #define XGMAC_KR1 0x00001000U 821 #define XGMAC_KR0 0x00000800U 822 #define XGMAC1 0x00000400U 823 #define XGMAC0 0x00000200U 824 #define SMB 0x00000100U 825 #define SF 0x00000080U 826 #define PL 0x00000040U 827 #define NCSI 0x00000020U 828 #define MPS 0x00000010U 829 #define MI 0x00000008U 830 #define DBG 0x00000004U 831 #define I2CM 0x00000002U 832 #define CIM 0x00000001U 833 834 #define PL_INT_MAP0 0x19414 835 #define PL_RST 0x19428 836 #define PIORST 0x00000002U 837 #define PIORSTMODE 0x00000001U 838 839 #define PL_PL_INT_CAUSE 0x19430 840 #define FATALPERR 0x00000010U 841 #define PERRVFID 0x00000001U 842 843 #define PL_REV 0x1943c 844 845 #define LE_DB_CONFIG 0x19c04 846 #define HASHEN 0x00100000U 847 848 #define LE_DB_SERVER_INDEX 0x19c18 849 #define LE_DB_ACT_CNT_IPV4 0x19c20 850 #define LE_DB_ACT_CNT_IPV6 0x19c24 851 852 #define LE_DB_INT_CAUSE 0x19c3c 853 #define REQQPARERR 0x00010000U 854 #define UNKNOWNCMD 0x00008000U 855 #define PARITYERR 0x00000040U 856 #define LIPMISS 0x00000020U 857 #define LIP0 0x00000010U 858 859 #define LE_DB_TID_HASHBASE 0x19df8 860 861 #define NCSI_INT_CAUSE 0x1a0d8 862 #define CIM_DM_PRTY_ERR 0x00000100U 863 #define MPS_DM_PRTY_ERR 0x00000080U 864 #define TXFIFO_PRTY_ERR 0x00000002U 865 #define RXFIFO_PRTY_ERR 0x00000001U 866 867 #define XGMAC_PORT_CFG2 0x1018 868 #define PATEN 0x00040000U 869 #define MAGICEN 0x00020000U 870 871 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024 872 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028 873 874 #define XGMAC_PORT_EPIO_DATA0 0x10c0 875 #define XGMAC_PORT_EPIO_DATA1 0x10c4 876 #define XGMAC_PORT_EPIO_DATA2 0x10c8 877 #define XGMAC_PORT_EPIO_DATA3 0x10cc 878 #define XGMAC_PORT_EPIO_OP 0x10d0 879 #define EPIOWR 0x00000100U 880 #define ADDRESS_MASK 0x000000ffU 881 #define ADDRESS_SHIFT 0 882 #define ADDRESS(x) ((x) << ADDRESS_SHIFT) 883 884 #define XGMAC_PORT_INT_CAUSE 0x10dc 885 #endif /* __T4_REGS_H */ 886