1 /*
2  * Copyright (c) 2009, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc.,
15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16  */
17 #ifndef __PSB_INTEL_REG_H__
18 #define __PSB_INTEL_REG_H__
19 
20 /*
21  * GPIO regs
22  */
23 #define GPIOA			0x5010
24 #define GPIOB			0x5014
25 #define GPIOC			0x5018
26 #define GPIOD			0x501c
27 #define GPIOE			0x5020
28 #define GPIOF			0x5024
29 #define GPIOG			0x5028
30 #define GPIOH			0x502c
31 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
32 # define GPIO_CLOCK_DIR_IN		(0 << 1)
33 # define GPIO_CLOCK_DIR_OUT		(1 << 1)
34 # define GPIO_CLOCK_VAL_MASK		(1 << 2)
35 # define GPIO_CLOCK_VAL_OUT		(1 << 3)
36 # define GPIO_CLOCK_VAL_IN		(1 << 4)
37 # define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
38 # define GPIO_DATA_DIR_MASK		(1 << 8)
39 # define GPIO_DATA_DIR_IN		(0 << 9)
40 # define GPIO_DATA_DIR_OUT		(1 << 9)
41 # define GPIO_DATA_VAL_MASK		(1 << 10)
42 # define GPIO_DATA_VAL_OUT		(1 << 11)
43 # define GPIO_DATA_VAL_IN		(1 << 12)
44 # define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
45 
46 #define GMBUS0			0x5100 /* clock/port select */
47 #define   GMBUS_RATE_100KHZ	(0<<8)
48 #define   GMBUS_RATE_50KHZ	(1<<8)
49 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
50 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
51 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
52 #define   GMBUS_PORT_DISABLED	0
53 #define   GMBUS_PORT_SSC	1
54 #define   GMBUS_PORT_VGADDC	2
55 #define   GMBUS_PORT_PANEL	3
56 #define   GMBUS_PORT_DPC	4 /* HDMIC */
57 #define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
58 				  /* 6 reserved */
59 #define   GMBUS_PORT_DPD	7 /* HDMID */
60 #define   GMBUS_NUM_PORTS       8
61 #define GMBUS1			0x5104 /* command/status */
62 #define   GMBUS_SW_CLR_INT	(1<<31)
63 #define   GMBUS_SW_RDY		(1<<30)
64 #define   GMBUS_ENT		(1<<29) /* enable timeout */
65 #define   GMBUS_CYCLE_NONE	(0<<25)
66 #define   GMBUS_CYCLE_WAIT	(1<<25)
67 #define   GMBUS_CYCLE_INDEX	(2<<25)
68 #define   GMBUS_CYCLE_STOP	(4<<25)
69 #define   GMBUS_BYTE_COUNT_SHIFT 16
70 #define   GMBUS_SLAVE_INDEX_SHIFT 8
71 #define   GMBUS_SLAVE_ADDR_SHIFT 1
72 #define   GMBUS_SLAVE_READ	(1<<0)
73 #define   GMBUS_SLAVE_WRITE	(0<<0)
74 #define GMBUS2			0x5108 /* status */
75 #define   GMBUS_INUSE		(1<<15)
76 #define   GMBUS_HW_WAIT_PHASE	(1<<14)
77 #define   GMBUS_STALL_TIMEOUT	(1<<13)
78 #define   GMBUS_INT		(1<<12)
79 #define   GMBUS_HW_RDY		(1<<11)
80 #define   GMBUS_SATOER		(1<<10)
81 #define   GMBUS_ACTIVE		(1<<9)
82 #define GMBUS3			0x510c /* data buffer bytes 3-0 */
83 #define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
84 #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
85 #define   GMBUS_NAK_EN		(1<<3)
86 #define   GMBUS_IDLE_EN		(1<<2)
87 #define   GMBUS_HW_WAIT_EN	(1<<1)
88 #define   GMBUS_HW_RDY_EN	(1<<0)
89 #define GMBUS5			0x5120 /* byte index */
90 #define   GMBUS_2BYTE_INDEX_EN	(1<<31)
91 
92 #define BLC_PWM_CTL		0x61254
93 #define BLC_PWM_CTL2		0x61250
94 #define BLC_PWM_CTL_C		0x62254
95 #define BLC_PWM_CTL2_C		0x62250
96 #define BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
97 /*
98  * This is the most significant 15 bits of the number of backlight cycles in a
99  * complete cycle of the modulated backlight control.
100  *
101  * The actual value is this field multiplied by two.
102  */
103 #define BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
104 #define BLM_LEGACY_MODE			(1 << 16)
105 /*
106  * This is the number of cycles out of the backlight modulation cycle for which
107  * the backlight is on.
108  *
109  * This field must be no greater than the number of cycles in the complete
110  * backlight modulation cycle.
111  */
112 #define BACKLIGHT_DUTY_CYCLE_SHIFT	(0)
113 #define BACKLIGHT_DUTY_CYCLE_MASK	(0xffff)
114 
115 #define I915_GCFGC			0xf0
116 #define I915_LOW_FREQUENCY_ENABLE	(1 << 7)
117 #define I915_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
118 #define I915_DISPLAY_CLOCK_333_MHZ	(4 << 4)
119 #define I915_DISPLAY_CLOCK_MASK		(7 << 4)
120 
121 #define I855_HPLLCC			0xc0
122 #define I855_CLOCK_CONTROL_MASK		(3 << 0)
123 #define I855_CLOCK_133_200		(0 << 0)
124 #define I855_CLOCK_100_200		(1 << 0)
125 #define I855_CLOCK_100_133		(2 << 0)
126 #define I855_CLOCK_166_250		(3 << 0)
127 
128 /* I830 CRTC registers */
129 #define HTOTAL_A		0x60000
130 #define HBLANK_A		0x60004
131 #define HSYNC_A			0x60008
132 #define VTOTAL_A		0x6000c
133 #define VBLANK_A		0x60010
134 #define VSYNC_A			0x60014
135 #define PIPEASRC		0x6001c
136 #define BCLRPAT_A		0x60020
137 #define VSYNCSHIFT_A		0x60028
138 
139 #define HTOTAL_B		0x61000
140 #define HBLANK_B		0x61004
141 #define HSYNC_B			0x61008
142 #define VTOTAL_B		0x6100c
143 #define VBLANK_B		0x61010
144 #define VSYNC_B			0x61014
145 #define PIPEBSRC		0x6101c
146 #define BCLRPAT_B		0x61020
147 #define VSYNCSHIFT_B		0x61028
148 
149 #define HTOTAL_C		0x62000
150 #define HBLANK_C		0x62004
151 #define HSYNC_C			0x62008
152 #define VTOTAL_C		0x6200c
153 #define VBLANK_C		0x62010
154 #define VSYNC_C			0x62014
155 #define PIPECSRC		0x6201c
156 #define BCLRPAT_C		0x62020
157 #define VSYNCSHIFT_C		0x62028
158 
159 #define PP_STATUS		0x61200
160 # define PP_ON				(1 << 31)
161 /*
162  * Indicates that all dependencies of the panel are on:
163  *
164  * - PLL enabled
165  * - pipe enabled
166  * - LVDS/DVOB/DVOC on
167  */
168 #define PP_READY			(1 << 30)
169 #define PP_SEQUENCE_NONE		(0 << 28)
170 #define PP_SEQUENCE_ON			(1 << 28)
171 #define PP_SEQUENCE_OFF			(2 << 28)
172 #define PP_SEQUENCE_MASK		0x30000000
173 #define PP_CONTROL		0x61204
174 #define POWER_TARGET_ON			(1 << 0)
175 
176 #define LVDSPP_ON		0x61208
177 #define LVDSPP_OFF		0x6120c
178 #define PP_CYCLE		0x61210
179 
180 #define PP_ON_DELAYS		0x61208		/* Cedartrail */
181 #define PP_OFF_DELAYS		0x6120c		/* Cedartrail */
182 
183 #define PFIT_CONTROL		0x61230
184 #define PFIT_ENABLE			(1 << 31)
185 #define PFIT_PIPE_MASK			(3 << 29)
186 #define PFIT_PIPE_SHIFT			29
187 #define PFIT_SCALING_MODE_PILLARBOX	(1 << 27)
188 #define PFIT_SCALING_MODE_LETTERBOX	(3 << 26)
189 #define VERT_INTERP_DISABLE		(0 << 10)
190 #define VERT_INTERP_BILINEAR		(1 << 10)
191 #define VERT_INTERP_MASK		(3 << 10)
192 #define VERT_AUTO_SCALE			(1 << 9)
193 #define HORIZ_INTERP_DISABLE		(0 << 6)
194 #define HORIZ_INTERP_BILINEAR		(1 << 6)
195 #define HORIZ_INTERP_MASK		(3 << 6)
196 #define HORIZ_AUTO_SCALE		(1 << 5)
197 #define PANEL_8TO6_DITHER_ENABLE	(1 << 3)
198 
199 #define PFIT_PGM_RATIOS		0x61234
200 #define PFIT_VERT_SCALE_MASK			0xfff00000
201 #define PFIT_HORIZ_SCALE_MASK			0x0000fff0
202 
203 #define PFIT_AUTO_RATIOS	0x61238
204 
205 #define DPLL_A			0x06014
206 #define DPLL_B			0x06018
207 #define DPLL_VCO_ENABLE			(1 << 31)
208 #define DPLL_DVO_HIGH_SPEED		(1 << 30)
209 #define DPLL_SYNCLOCK_ENABLE		(1 << 29)
210 #define DPLL_VGA_MODE_DIS		(1 << 28)
211 #define DPLLB_MODE_DAC_SERIAL		(1 << 26)	/* i915 */
212 #define DPLLB_MODE_LVDS			(2 << 26)	/* i915 */
213 #define DPLL_MODE_MASK			(3 << 26)
214 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10	(0 << 24)	/* i915 */
215 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5	(1 << 24)	/* i915 */
216 #define DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24)	/* i915 */
217 #define DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24)	/* i915 */
218 #define DPLL_P2_CLOCK_DIV_MASK		0x03000000	/* i915 */
219 #define DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000	/* i915 */
220 #define DPLL_LOCK			(1 << 15)	/* CDV */
221 
222 /*
223  *  The i830 generation, in DAC/serial mode, defines p1 as two plus this
224  * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
225  */
226 # define DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
227 /*
228  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
229  * this field (only one bit may be set).
230  */
231 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
232 #define DPLL_FPA01_P1_POST_DIV_SHIFT	16
233 #define PLL_P2_DIVIDE_BY_4		(1 << 23)	/* i830, required
234 							 * in DVO non-gang */
235 # define PLL_P1_DIVIDE_BY_TWO		(1 << 21)	/* i830 */
236 #define PLL_REF_INPUT_DREFCLK		(0 << 13)
237 #define PLL_REF_INPUT_TVCLKINA		(1 << 13)	/* i830 */
238 #define PLL_REF_INPUT_TVCLKINBC		(2 << 13)	/* SDVO
239 								 * TVCLKIN */
240 #define PLLB_REF_INPUT_SPREADSPECTRUMIN	(3 << 13)
241 #define PLL_REF_INPUT_MASK		(3 << 13)
242 #define PLL_LOAD_PULSE_PHASE_SHIFT	9
243 /*
244  * Parallel to Serial Load Pulse phase selection.
245  * Selects the phase for the 10X DPLL clock for the PCIe
246  * digital display port. The range is 4 to 13; 10 or more
247  * is just a flip delay. The default is 6
248  */
249 #define PLL_LOAD_PULSE_PHASE_MASK	(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
250 #define DISPLAY_RATE_SELECT_FPA1	(1 << 8)
251 
252 /*
253  * SDVO multiplier for 945G/GM. Not used on 965.
254  *
255  * DPLL_MD_UDI_MULTIPLIER_MASK
256  */
257 #define SDVO_MULTIPLIER_MASK		0x000000ff
258 #define SDVO_MULTIPLIER_SHIFT_HIRES	4
259 #define SDVO_MULTIPLIER_SHIFT_VGA	0
260 
261 /*
262  * PLL_MD
263  */
264 /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */
265 #define DPLL_A_MD		0x0601c
266 /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */
267 #define DPLL_B_MD		0x06020
268 /*
269  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
270  *
271  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
272  */
273 #define DPLL_MD_UDI_DIVIDER_MASK	0x3f000000
274 #define DPLL_MD_UDI_DIVIDER_SHIFT	24
275 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
276 #define DPLL_MD_VGA_UDI_DIVIDER_MASK	0x003f0000
277 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT	16
278 /*
279  * SDVO/UDI pixel multiplier.
280  *
281  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
282  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
283  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
284  * dummy bytes in the datastream at an increased clock rate, with both sides of
285  * the link knowing how many bytes are fill.
286  *
287  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
288  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
289  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
290  * through an SDVO command.
291  *
292  * This register field has values of multiplication factor minus 1, with
293  * a maximum multiplier of 5 for SDVO.
294  */
295 #define DPLL_MD_UDI_MULTIPLIER_MASK	0x00003f00
296 #define DPLL_MD_UDI_MULTIPLIER_SHIFT	8
297 /*
298  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
299  * This best be set to the default value (3) or the CRT won't work. No,
300  * I don't entirely understand what this does...
301  */
302 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
303 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
304 
305 #define DPLL_TEST		0x606c
306 #define DPLLB_TEST_SDVO_DIV_1		(0 << 22)
307 #define DPLLB_TEST_SDVO_DIV_2		(1 << 22)
308 #define DPLLB_TEST_SDVO_DIV_4		(2 << 22)
309 #define DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
310 #define DPLLB_TEST_N_BYPASS		(1 << 19)
311 #define DPLLB_TEST_M_BYPASS		(1 << 18)
312 #define DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
313 #define DPLLA_TEST_N_BYPASS		(1 << 3)
314 #define DPLLA_TEST_M_BYPASS		(1 << 2)
315 #define DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
316 
317 #define ADPA			0x61100
318 #define ADPA_DAC_ENABLE			(1 << 31)
319 #define ADPA_DAC_DISABLE		0
320 #define ADPA_PIPE_SELECT_MASK		(1 << 30)
321 #define ADPA_PIPE_A_SELECT		0
322 #define ADPA_PIPE_B_SELECT		(1 << 30)
323 #define ADPA_USE_VGA_HVPOLARITY		(1 << 15)
324 #define ADPA_SETS_HVPOLARITY		0
325 #define ADPA_VSYNC_CNTL_DISABLE		(1 << 11)
326 #define ADPA_VSYNC_CNTL_ENABLE		0
327 #define ADPA_HSYNC_CNTL_DISABLE		(1 << 10)
328 #define ADPA_HSYNC_CNTL_ENABLE		0
329 #define ADPA_VSYNC_ACTIVE_HIGH		(1 << 4)
330 #define ADPA_VSYNC_ACTIVE_LOW		0
331 #define ADPA_HSYNC_ACTIVE_HIGH		(1 << 3)
332 #define ADPA_HSYNC_ACTIVE_LOW		0
333 
334 #define FPA0			0x06040
335 #define FPA1			0x06044
336 #define FPB0			0x06048
337 #define FPB1			0x0604c
338 #define FP_N_DIV_MASK			0x003f0000
339 #define FP_N_DIV_SHIFT			16
340 #define FP_M1_DIV_MASK			0x00003f00
341 #define FP_M1_DIV_SHIFT			8
342 #define FP_M2_DIV_MASK			0x0000003f
343 #define FP_M2_DIV_SHIFT			0
344 
345 #define PORT_HOTPLUG_EN		0x61110
346 #define SDVOB_HOTPLUG_INT_EN		(1 << 26)
347 #define SDVOC_HOTPLUG_INT_EN		(1 << 25)
348 #define TV_HOTPLUG_INT_EN		(1 << 18)
349 #define CRT_HOTPLUG_INT_EN		(1 << 9)
350 #define CRT_HOTPLUG_FORCE_DETECT	(1 << 3)
351 /* CDV.. */
352 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
353 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
354 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
355 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
356 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
357 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
358 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
359 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
360 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
361 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
362 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
363 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
364 #define CRT_HOTPLUG_DETECT_MASK			0x000000F8
365 
366 #define PORT_HOTPLUG_STAT	0x61114
367 #define CRT_HOTPLUG_INT_STATUS		(1 << 11)
368 #define TV_HOTPLUG_INT_STATUS		(1 << 10)
369 #define CRT_HOTPLUG_MONITOR_MASK	(3 << 8)
370 #define CRT_HOTPLUG_MONITOR_COLOR	(3 << 8)
371 #define CRT_HOTPLUG_MONITOR_MONO	(2 << 8)
372 #define CRT_HOTPLUG_MONITOR_NONE	(0 << 8)
373 #define SDVOC_HOTPLUG_INT_STATUS	(1 << 7)
374 #define SDVOB_HOTPLUG_INT_STATUS	(1 << 6)
375 
376 #define SDVOB			0x61140
377 #define SDVOC			0x61160
378 #define SDVO_ENABLE			(1 << 31)
379 #define SDVO_PIPE_B_SELECT		(1 << 30)
380 #define SDVO_STALL_SELECT		(1 << 29)
381 #define SDVO_INTERRUPT_ENABLE		(1 << 26)
382 #define SDVO_COLOR_RANGE_16_235		(1 << 8)
383 #define SDVO_AUDIO_ENABLE		(1 << 6)
384 
385 /**
386  * 915G/GM SDVO pixel multiplier.
387  *
388  * Programmed value is multiplier - 1, up to 5x.
389  *
390  * DPLL_MD_UDI_MULTIPLIER_MASK
391  */
392 #define SDVO_PORT_MULTIPLY_MASK		(7 << 23)
393 #define SDVO_PORT_MULTIPLY_SHIFT	23
394 #define SDVO_PHASE_SELECT_MASK		(15 << 19)
395 #define SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
396 #define SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
397 #define SDVOC_GANG_MODE			(1 << 16)
398 #define SDVO_BORDER_ENABLE		(1 << 7)
399 #define SDVOB_PCIE_CONCURRENCY		(1 << 3)
400 #define SDVO_DETECTED			(1 << 2)
401 /* Bits to be preserved when writing */
402 #define SDVOB_PRESERVE_MASK		((1 << 17) | (1 << 16) | (1 << 14))
403 #define SDVOC_PRESERVE_MASK		(1 << 17)
404 
405 /*
406  * This register controls the LVDS output enable, pipe selection, and data
407  * format selection.
408  *
409  * All of the clock/data pairs are force powered down by power sequencing.
410  */
411 #define LVDS			0x61180
412 /*
413  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
414  * the DPLL semantics change when the LVDS is assigned to that pipe.
415  */
416 #define LVDS_PORT_EN			(1 << 31)
417 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
418 #define LVDS_PIPEB_SELECT		(1 << 30)
419 
420 /* Turns on border drawing to allow centered display. */
421 #define LVDS_BORDER_EN			(1 << 15)
422 
423 /*
424  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
425  * pixel.
426  */
427 #define LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
428 #define LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
429 #define LVDS_A0A2_CLKA_POWER_UP		(3 << 8)
430 /*
431  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
432  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
433  * on.
434  */
435 #define LVDS_A3_POWER_MASK		(3 << 6)
436 #define LVDS_A3_POWER_DOWN		(0 << 6)
437 #define LVDS_A3_POWER_UP		(3 << 6)
438 /*
439  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
440  * is set.
441  */
442 #define LVDS_CLKB_POWER_MASK		(3 << 4)
443 #define LVDS_CLKB_POWER_DOWN		(0 << 4)
444 #define LVDS_CLKB_POWER_UP		(3 << 4)
445 /*
446  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
447  * setting for whether we are in dual-channel mode.  The B3 pair will
448  * additionally only be powered up when LVDS_A3_POWER_UP is set.
449  */
450 #define LVDS_B0B3_POWER_MASK		(3 << 2)
451 #define LVDS_B0B3_POWER_DOWN		(0 << 2)
452 #define LVDS_B0B3_POWER_UP		(3 << 2)
453 
454 #define PIPEACONF		0x70008
455 #define PIPEACONF_ENABLE		(1 << 31)
456 #define PIPEACONF_DISABLE		0
457 #define PIPEACONF_DOUBLE_WIDE		(1 << 30)
458 #define PIPECONF_ACTIVE			(1 << 30)
459 #define I965_PIPECONF_ACTIVE		(1 << 30)
460 #define PIPECONF_DSIPLL_LOCK		(1 << 29)
461 #define PIPEACONF_SINGLE_WIDE		0
462 #define PIPEACONF_PIPE_UNLOCKED		0
463 #define PIPEACONF_DSR			(1 << 26)
464 #define PIPEACONF_PIPE_LOCKED		(1 << 25)
465 #define PIPEACONF_PALETTE		0
466 #define PIPECONF_FORCE_BORDER		(1 << 25)
467 #define PIPEACONF_GAMMA			(1 << 24)
468 #define PIPECONF_PROGRESSIVE		(0 << 21)
469 #define PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
470 #define PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
471 #define PIPECONF_PLANE_OFF		(1 << 19)
472 #define PIPECONF_CURSOR_OFF		(1 << 18)
473 
474 #define PIPEBCONF		0x71008
475 #define PIPEBCONF_ENABLE		(1 << 31)
476 #define PIPEBCONF_DISABLE		0
477 #define PIPEBCONF_DOUBLE_WIDE		(1 << 30)
478 #define PIPEBCONF_DISABLE		0
479 #define PIPEBCONF_GAMMA			(1 << 24)
480 #define PIPEBCONF_PALETTE		0
481 
482 #define PIPECCONF		0x72008
483 
484 #define PIPEBGCMAXRED		0x71010
485 #define PIPEBGCMAXGREEN		0x71014
486 #define PIPEBGCMAXBLUE		0x71018
487 
488 #define PIPEASTAT		0x70024
489 #define PIPEBSTAT		0x71024
490 #define PIPECSTAT		0x72024
491 #define PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)
492 #define PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL << 2)
493 #define PIPE_VBLANK_CLEAR			(1 << 1)
494 #define PIPE_VBLANK_STATUS			(1 << 1)
495 #define PIPE_TE_STATUS				(1UL << 6)
496 #define PIPE_DPST_EVENT_STATUS			(1UL << 7)
497 #define PIPE_VSYNC_CLEAR			(1UL << 9)
498 #define PIPE_VSYNC_STATUS			(1UL << 9)
499 #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS		(1UL << 10)
500 #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS	(1UL << 11)
501 #define PIPE_VBLANK_INTERRUPT_ENABLE		(1UL << 17)
502 #define PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL << 18)
503 #define PIPE_TE_ENABLE				(1UL << 22)
504 #define PIPE_DPST_EVENT_ENABLE			(1UL << 23)
505 #define PIPE_VSYNC_ENABL			(1UL << 25)
506 #define PIPE_HDMI_AUDIO_UNDERRUN		(1UL << 26)
507 #define PIPE_HDMI_AUDIO_BUFFER_DONE		(1UL << 27)
508 #define PIPE_HDMI_AUDIO_INT_MASK		(PIPE_HDMI_AUDIO_UNDERRUN | \
509 						PIPE_HDMI_AUDIO_BUFFER_DONE)
510 #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
511 #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))
512 #define HISTOGRAM_INT_CONTROL		0x61268
513 #define HISTOGRAM_BIN_DATA		0X61264
514 #define HISTOGRAM_LOGIC_CONTROL		0x61260
515 #define PWM_CONTROL_LOGIC		0x61250
516 #define PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL << 10)
517 #define HISTOGRAM_INTERRUPT_ENABLE		(1UL << 31)
518 #define HISTOGRAM_LOGIC_ENABLE			(1UL << 31)
519 #define PWM_LOGIC_ENABLE			(1UL << 31)
520 #define PWM_PHASEIN_ENABLE			(1UL << 25)
521 #define PWM_PHASEIN_INT_ENABLE			(1UL << 24)
522 #define PWM_PHASEIN_VB_COUNT			0x00001f00
523 #define PWM_PHASEIN_INC				0x0000001f
524 #define HISTOGRAM_INT_CTRL_CLEAR		(1UL << 30)
525 #define DPST_YUV_LUMA_MODE			0
526 
527 struct dpst_ie_histogram_control {
528 	union {
529 		uint32_t data;
530 		struct {
531 			uint32_t bin_reg_index:7;
532 			uint32_t reserved:4;
533 			uint32_t bin_reg_func_select:1;
534 			uint32_t sync_to_phase_in:1;
535 			uint32_t alt_enhancement_mode:2;
536 			uint32_t reserved1:1;
537 			uint32_t sync_to_phase_in_count:8;
538 			uint32_t histogram_mode_select:1;
539 			uint32_t reserved2:4;
540 			uint32_t ie_pipe_assignment:1;
541 			uint32_t ie_mode_table_enabled:1;
542 			uint32_t ie_histogram_enable:1;
543 		};
544 	};
545 };
546 
547 struct dpst_guardband {
548 	union {
549 		uint32_t data;
550 		struct {
551 			uint32_t guardband:22;
552 			uint32_t guardband_interrupt_delay:8;
553 			uint32_t interrupt_status:1;
554 			uint32_t interrupt_enable:1;
555 		};
556 	};
557 };
558 
559 #define PIPEAFRAMEHIGH		0x70040
560 #define PIPEAFRAMEPIXEL		0x70044
561 #define PIPEBFRAMEHIGH		0x71040
562 #define PIPEBFRAMEPIXEL		0x71044
563 #define PIPECFRAMEHIGH		0x72040
564 #define PIPECFRAMEPIXEL		0x72044
565 #define PIPE_FRAME_HIGH_MASK	0x0000ffff
566 #define PIPE_FRAME_HIGH_SHIFT	0
567 #define PIPE_FRAME_LOW_MASK	0xff000000
568 #define PIPE_FRAME_LOW_SHIFT	24
569 #define PIPE_PIXEL_MASK		0x00ffffff
570 #define PIPE_PIXEL_SHIFT	0
571 
572 #define DSPARB			0x70030
573 #define DSPFW1			0x70034
574 #define DSPFW2			0x70038
575 #define DSPFW3			0x7003c
576 #define DSPFW4			0x70050
577 #define DSPFW5			0x70054
578 #define DSPFW6			0x70058
579 #define DSPCHICKENBIT		0x70400
580 #define DSPACNTR		0x70180
581 #define DSPBCNTR		0x71180
582 #define DSPCCNTR		0x72180
583 #define DISPLAY_PLANE_ENABLE			(1 << 31)
584 #define DISPLAY_PLANE_DISABLE			0
585 #define DISPPLANE_GAMMA_ENABLE			(1 << 30)
586 #define DISPPLANE_GAMMA_DISABLE			0
587 #define DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
588 #define DISPPLANE_8BPP				(0x2 << 26)
589 #define DISPPLANE_15_16BPP			(0x4 << 26)
590 #define DISPPLANE_16BPP				(0x5 << 26)
591 #define DISPPLANE_32BPP_NO_ALPHA		(0x6 << 26)
592 #define DISPPLANE_32BPP				(0x7 << 26)
593 #define DISPPLANE_STEREO_ENABLE			(1 << 25)
594 #define DISPPLANE_STEREO_DISABLE		0
595 #define DISPPLANE_SEL_PIPE_MASK			(1 << 24)
596 #define DISPPLANE_SEL_PIPE_POS			24
597 #define DISPPLANE_SEL_PIPE_A			0
598 #define DISPPLANE_SEL_PIPE_B			(1 << 24)
599 #define DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
600 #define DISPPLANE_SRC_KEY_DISABLE		0
601 #define DISPPLANE_LINE_DOUBLE			(1 << 20)
602 #define DISPPLANE_NO_LINE_DOUBLE		0
603 #define DISPPLANE_STEREO_POLARITY_FIRST		0
604 #define DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
605 /* plane B only */
606 #define DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
607 #define DISPPLANE_ALPHA_TRANS_DISABLE		0
608 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA		0
609 #define DISPPLANE_SPRITE_ABOVE_OVERLAY		(1)
610 #define DISPPLANE_BOTTOM			(4)
611 
612 #define DSPABASE		0x70184
613 #define DSPALINOFF		0x70184
614 #define DSPASTRIDE		0x70188
615 
616 #define DSPBBASE		0x71184
617 #define DSPBLINOFF		0X71184
618 #define DSPBADDR		DSPBBASE
619 #define DSPBSTRIDE		0x71188
620 
621 #define DSPCBASE		0x72184
622 #define DSPCLINOFF		0x72184
623 #define DSPCSTRIDE		0x72188
624 
625 #define DSPAKEYVAL		0x70194
626 #define DSPAKEYMASK		0x70198
627 
628 #define DSPAPOS			0x7018C	/* reserved */
629 #define DSPASIZE		0x70190
630 #define DSPBPOS			0x7118C
631 #define DSPBSIZE		0x71190
632 #define DSPCPOS			0x7218C
633 #define DSPCSIZE		0x72190
634 
635 #define DSPASURF		0x7019C
636 #define DSPATILEOFF		0x701A4
637 
638 #define DSPBSURF		0x7119C
639 #define DSPBTILEOFF		0x711A4
640 
641 #define DSPCSURF		0x7219C
642 #define DSPCTILEOFF		0x721A4
643 #define DSPCKEYMAXVAL		0x721A0
644 #define DSPCKEYMINVAL		0x72194
645 #define DSPCKEYMSK		0x72198
646 
647 #define VGACNTRL		0x71400
648 #define VGA_DISP_DISABLE		(1 << 31)
649 #define VGA_2X_MODE			(1 << 30)
650 #define VGA_PIPE_B_SELECT		(1 << 29)
651 
652 /*
653  * Overlay registers
654  */
655 #define OV_C_OFFSET		0x08000
656 #define OV_OVADD		0x30000
657 #define OV_DOVASTA		0x30008
658 # define OV_PIPE_SELECT			((1 << 6)|(1 << 7))
659 # define OV_PIPE_SELECT_POS		6
660 # define OV_PIPE_A			0
661 # define OV_PIPE_C			1
662 #define OV_OGAMC5		0x30010
663 #define OV_OGAMC4		0x30014
664 #define OV_OGAMC3		0x30018
665 #define OV_OGAMC2		0x3001C
666 #define OV_OGAMC1		0x30020
667 #define OV_OGAMC0		0x30024
668 #define OVC_OVADD		0x38000
669 #define OVC_DOVCSTA		0x38008
670 #define OVC_OGAMC5		0x38010
671 #define OVC_OGAMC4		0x38014
672 #define OVC_OGAMC3		0x38018
673 #define OVC_OGAMC2		0x3801C
674 #define OVC_OGAMC1		0x38020
675 #define OVC_OGAMC0		0x38024
676 
677 /*
678  * Some BIOS scratch area registers.  The 845 (and 830?) store the amount
679  * of video memory available to the BIOS in SWF1.
680  */
681 #define SWF0			0x71410
682 #define SWF1			0x71414
683 #define SWF2			0x71418
684 #define SWF3			0x7141c
685 #define SWF4			0x71420
686 #define SWF5			0x71424
687 #define SWF6			0x71428
688 
689 /*
690  * 855 scratch registers.
691  */
692 #define SWF00			0x70410
693 #define SWF01			0x70414
694 #define SWF02			0x70418
695 #define SWF03			0x7041c
696 #define SWF04			0x70420
697 #define SWF05			0x70424
698 #define SWF06			0x70428
699 
700 #define SWF10			SWF0
701 #define SWF11			SWF1
702 #define SWF12			SWF2
703 #define SWF13			SWF3
704 #define SWF14			SWF4
705 #define SWF15			SWF5
706 #define SWF16			SWF6
707 
708 #define SWF30			0x72414
709 #define SWF31			0x72418
710 #define SWF32			0x7241c
711 
712 
713 /*
714  * Palette registers
715  */
716 #define PALETTE_A		0x0a000
717 #define PALETTE_B		0x0a800
718 #define PALETTE_C		0x0ac00
719 
720 /* Cursor A & B regs */
721 #define CURACNTR		0x70080
722 #define CURSOR_MODE_DISABLE		0x00
723 #define CURSOR_MODE_64_32B_AX		0x07
724 #define CURSOR_MODE_64_ARGB_AX		((1 << 5) | CURSOR_MODE_64_32B_AX)
725 #define MCURSOR_GAMMA_ENABLE		(1 << 26)
726 #define CURABASE		0x70084
727 #define CURAPOS			0x70088
728 #define CURSOR_POS_MASK			0x007FF
729 #define CURSOR_POS_SIGN			0x8000
730 #define CURSOR_X_SHIFT			0
731 #define CURSOR_Y_SHIFT			16
732 #define CURBCNTR		0x700c0
733 #define CURBBASE		0x700c4
734 #define CURBPOS			0x700c8
735 #define CURCCNTR		0x700e0
736 #define CURCBASE		0x700e4
737 #define CURCPOS			0x700e8
738 
739 /*
740  * Interrupt Registers
741  */
742 #define IER			0x020a0
743 #define IIR			0x020a4
744 #define IMR			0x020a8
745 #define ISR			0x020ac
746 
747 /*
748  * MOORESTOWN delta registers
749  */
750 #define MRST_DPLL_A		0x0f014
751 #define MDFLD_DPLL_B		0x0f018
752 #define MDFLD_INPUT_REF_SEL		(1 << 14)
753 #define MDFLD_VCO_SEL			(1 << 16)
754 #define DPLLA_MODE_LVDS			(2 << 26)	/* mrst */
755 #define MDFLD_PLL_LATCHEN		(1 << 28)
756 #define MDFLD_PWR_GATE_EN		(1 << 30)
757 #define MDFLD_P1_MASK			(0x1FF << 17)
758 #define MRST_FPA0		0x0f040
759 #define MRST_FPA1		0x0f044
760 #define MDFLD_DPLL_DIV0		0x0f048
761 #define MDFLD_DPLL_DIV1		0x0f04c
762 #define MRST_PERF_MODE		0x020f4
763 
764 /*
765  * MEDFIELD HDMI registers
766  */
767 #define HDMIPHYMISCCTL		0x61134
768 #define HDMI_PHY_POWER_DOWN		0x7f
769 #define HDMIB_CONTROL		0x61140
770 #define HDMIB_PORT_EN			(1 << 31)
771 #define HDMIB_PIPE_B_SELECT		(1 << 30)
772 #define HDMIB_NULL_PACKET		(1 << 9)
773 #define HDMIB_HDCP_PORT			(1 << 5)
774 
775 /* #define LVDS			0x61180 */
776 #define MRST_PANEL_8TO6_DITHER_ENABLE	(1 << 25)
777 #define MRST_PANEL_24_DOT_1_FORMAT	(1 << 24)
778 #define LVDS_A3_POWER_UP_0_OUTPUT	(1 << 6)
779 
780 #define MIPI			0x61190
781 #define MIPI_C			0x62190
782 #define MIPI_PORT_EN			(1 << 31)
783 /* Turns on border drawing to allow centered display. */
784 #define SEL_FLOPPED_HSTX		(1 << 23)
785 #define PASS_FROM_SPHY_TO_AFE		(1 << 16)
786 #define MIPI_BORDER_EN			(1 << 15)
787 #define MIPIA_3LANE_MIPIC_1LANE		0x1
788 #define MIPIA_2LANE_MIPIC_2LANE		0x2
789 #define TE_TRIGGER_DSI_PROTOCOL		(1 << 2)
790 #define TE_TRIGGER_GPIO_PIN		(1 << 3)
791 #define MIPI_TE_COUNT		0x61194
792 
793 /* #define PP_CONTROL	0x61204 */
794 #define POWER_DOWN_ON_RESET		(1 << 1)
795 
796 /* #define PFIT_CONTROL	0x61230 */
797 #define PFIT_PIPE_SELECT		(3 << 29)
798 #define PFIT_PIPE_SELECT_SHIFT		(29)
799 
800 /* #define BLC_PWM_CTL		0x61254 */
801 #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT	(16)
802 #define MRST_BACKLIGHT_MODULATION_FREQ_MASK	(0xffff << 16)
803 
804 /* #define PIPEACONF 0x70008 */
805 #define PIPEACONF_PIPE_STATE		(1 << 30)
806 /* #define DSPACNTR		0x70180 */
807 
808 #define MRST_DSPABASE		0x7019c
809 #define MRST_DSPBBASE		0x7119c
810 #define MDFLD_DSPCBASE		0x7219c
811 
812 /*
813  * Moorestown registers.
814  */
815 
816 /*
817  *	MIPI IP registers
818  */
819 #define MIPIC_REG_OFFSET		0x800
820 
821 #define DEVICE_READY_REG		0xb000
822 #define LP_OUTPUT_HOLD				(1 << 16)
823 #define EXIT_ULPS_DEV_READY			0x3
824 #define LP_OUTPUT_HOLD_RELEASE			0x810000
825 # define ENTERING_ULPS				(2 << 1)
826 # define EXITING_ULPS				(1 << 1)
827 # define ULPS_MASK				(3 << 1)
828 # define BUS_POSSESSION				(1 << 3)
829 #define INTR_STAT_REG			0xb004
830 #define RX_SOT_ERROR				(1 << 0)
831 #define RX_SOT_SYNC_ERROR			(1 << 1)
832 #define RX_ESCAPE_MODE_ENTRY_ERROR		(1 << 3)
833 #define RX_LP_TX_SYNC_ERROR			(1 << 4)
834 #define RX_HS_RECEIVE_TIMEOUT_ERROR		(1 << 5)
835 #define RX_FALSE_CONTROL_ERROR			(1 << 6)
836 #define RX_ECC_SINGLE_BIT_ERROR			(1 << 7)
837 #define RX_ECC_MULTI_BIT_ERROR			(1 << 8)
838 #define RX_CHECKSUM_ERROR			(1 << 9)
839 #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED		(1 << 10)
840 #define RX_DSI_VC_ID_INVALID			(1 << 11)
841 #define TX_FALSE_CONTROL_ERROR			(1 << 12)
842 #define TX_ECC_SINGLE_BIT_ERROR			(1 << 13)
843 #define TX_ECC_MULTI_BIT_ERROR			(1 << 14)
844 #define TX_CHECKSUM_ERROR			(1 << 15)
845 #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED		(1 << 16)
846 #define TX_DSI_VC_ID_INVALID			(1 << 17)
847 #define HIGH_CONTENTION				(1 << 18)
848 #define LOW_CONTENTION				(1 << 19)
849 #define DPI_FIFO_UNDER_RUN			(1 << 20)
850 #define HS_TX_TIMEOUT				(1 << 21)
851 #define LP_RX_TIMEOUT				(1 << 22)
852 #define TURN_AROUND_ACK_TIMEOUT			(1 << 23)
853 #define ACK_WITH_NO_ERROR			(1 << 24)
854 #define HS_GENERIC_WR_FIFO_FULL			(1 << 27)
855 #define LP_GENERIC_WR_FIFO_FULL			(1 << 28)
856 #define SPL_PKT_SENT				(1 << 30)
857 #define INTR_EN_REG			0xb008
858 #define DSI_FUNC_PRG_REG		0xb00c
859 #define DPI_CHANNEL_NUMBER_POS			0x03
860 #define DBI_CHANNEL_NUMBER_POS			0x05
861 #define FMT_DPI_POS				0x07
862 #define FMT_DBI_POS				0x0A
863 #define DBI_DATA_WIDTH_POS			0x0D
864 
865 /* DPI PIXEL FORMATS */
866 #define RGB_565_FMT				0x01	/* RGB 565 FORMAT */
867 #define RGB_666_FMT				0x02	/* RGB 666 FORMAT */
868 #define LRGB_666_FMT				0x03	/* RGB LOOSELY PACKED
869 							 * 666 FORMAT
870 							 */
871 #define RGB_888_FMT				0x04	/* RGB 888 FORMAT */
872 #define VIRTUAL_CHANNEL_NUMBER_0		0x00	/* Virtual channel 0 */
873 #define VIRTUAL_CHANNEL_NUMBER_1		0x01	/* Virtual channel 1 */
874 #define VIRTUAL_CHANNEL_NUMBER_2		0x02	/* Virtual channel 2 */
875 #define VIRTUAL_CHANNEL_NUMBER_3		0x03	/* Virtual channel 3 */
876 
877 #define DBI_NOT_SUPPORTED			0x00	/* command mode
878 							 * is not supported
879 							 */
880 #define DBI_DATA_WIDTH_16BIT			0x01	/* 16 bit data */
881 #define DBI_DATA_WIDTH_9BIT			0x02	/* 9 bit data */
882 #define DBI_DATA_WIDTH_8BIT			0x03	/* 8 bit data */
883 #define DBI_DATA_WIDTH_OPT1			0x04	/* option 1 */
884 #define DBI_DATA_WIDTH_OPT2			0x05	/* option 2 */
885 
886 #define HS_TX_TIMEOUT_REG		0xb010
887 #define LP_RX_TIMEOUT_REG		0xb014
888 #define TURN_AROUND_TIMEOUT_REG		0xb018
889 #define DEVICE_RESET_REG		0xb01C
890 #define DPI_RESOLUTION_REG		0xb020
891 #define RES_V_POS				0x10
892 #define DBI_RESOLUTION_REG		0xb024 /* Reserved for MDFLD */
893 #define HORIZ_SYNC_PAD_COUNT_REG	0xb028
894 #define HORIZ_BACK_PORCH_COUNT_REG	0xb02C
895 #define HORIZ_FRONT_PORCH_COUNT_REG	0xb030
896 #define HORIZ_ACTIVE_AREA_COUNT_REG	0xb034
897 #define VERT_SYNC_PAD_COUNT_REG		0xb038
898 #define VERT_BACK_PORCH_COUNT_REG	0xb03c
899 #define VERT_FRONT_PORCH_COUNT_REG	0xb040
900 #define HIGH_LOW_SWITCH_COUNT_REG	0xb044
901 #define DPI_CONTROL_REG			0xb048
902 #define DPI_SHUT_DOWN				(1 << 0)
903 #define DPI_TURN_ON				(1 << 1)
904 #define DPI_COLOR_MODE_ON			(1 << 2)
905 #define DPI_COLOR_MODE_OFF			(1 << 3)
906 #define DPI_BACK_LIGHT_ON			(1 << 4)
907 #define DPI_BACK_LIGHT_OFF			(1 << 5)
908 #define DPI_LP					(1 << 6)
909 #define DPI_DATA_REG			0xb04c
910 #define DPI_BACK_LIGHT_ON_DATA			0x07
911 #define DPI_BACK_LIGHT_OFF_DATA			0x17
912 #define INIT_COUNT_REG			0xb050
913 #define MAX_RET_PAK_REG			0xb054
914 #define VIDEO_FMT_REG			0xb058
915 #define COMPLETE_LAST_PCKT			(1 << 2)
916 #define EOT_DISABLE_REG			0xb05c
917 #define ENABLE_CLOCK_STOPPING			(1 << 1)
918 #define LP_BYTECLK_REG			0xb060
919 #define LP_GEN_DATA_REG			0xb064
920 #define HS_GEN_DATA_REG			0xb068
921 #define LP_GEN_CTRL_REG			0xb06C
922 #define HS_GEN_CTRL_REG			0xb070
923 #define DCS_CHANNEL_NUMBER_POS		0x6
924 #define MCS_COMMANDS_POS		0x8
925 #define WORD_COUNTS_POS			0x8
926 #define MCS_PARAMETER_POS			0x10
927 #define GEN_FIFO_STAT_REG		0xb074
928 #define HS_DATA_FIFO_FULL			(1 << 0)
929 #define HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
930 #define HS_DATA_FIFO_EMPTY			(1 << 2)
931 #define LP_DATA_FIFO_FULL			(1 << 8)
932 #define LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
933 #define LP_DATA_FIFO_EMPTY			(1 << 10)
934 #define HS_CTRL_FIFO_FULL			(1 << 16)
935 #define HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
936 #define HS_CTRL_FIFO_EMPTY			(1 << 18)
937 #define LP_CTRL_FIFO_FULL			(1 << 24)
938 #define LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
939 #define LP_CTRL_FIFO_EMPTY			(1 << 26)
940 #define DBI_FIFO_EMPTY				(1 << 27)
941 #define DPI_FIFO_EMPTY				(1 << 28)
942 #define HS_LS_DBI_ENABLE_REG		0xb078
943 #define TXCLKESC_REG			0xb07c
944 #define DPHY_PARAM_REG			0xb080
945 #define DBI_BW_CTRL_REG			0xb084
946 #define CLK_LANE_SWT_REG		0xb088
947 
948 /*
949  * MIPI Adapter registers
950  */
951 #define MIPI_CONTROL_REG		0xb104
952 #define MIPI_2X_CLOCK_BITS			((1 << 0) | (1 << 1))
953 #define MIPI_DATA_ADDRESS_REG		0xb108
954 #define MIPI_DATA_LENGTH_REG		0xb10C
955 #define MIPI_COMMAND_ADDRESS_REG	0xb110
956 #define MIPI_COMMAND_LENGTH_REG		0xb114
957 #define MIPI_READ_DATA_RETURN_REG0	0xb118
958 #define MIPI_READ_DATA_RETURN_REG1	0xb11C
959 #define MIPI_READ_DATA_RETURN_REG2	0xb120
960 #define MIPI_READ_DATA_RETURN_REG3	0xb124
961 #define MIPI_READ_DATA_RETURN_REG4	0xb128
962 #define MIPI_READ_DATA_RETURN_REG5	0xb12C
963 #define MIPI_READ_DATA_RETURN_REG6	0xb130
964 #define MIPI_READ_DATA_RETURN_REG7	0xb134
965 #define MIPI_READ_DATA_VALID_REG	0xb138
966 
967 /* DBI COMMANDS */
968 #define soft_reset			0x01
969 /*
970  *	The display module performs a software reset.
971  *	Registers are written with their SW Reset default values.
972  */
973 #define get_power_mode			0x0a
974 /*
975  *	The display module returns the current power mode
976  */
977 #define get_address_mode		0x0b
978 /*
979  *	The display module returns the current status.
980  */
981 #define get_pixel_format		0x0c
982 /*
983  *	This command gets the pixel format for the RGB image data
984  *	used by the interface.
985  */
986 #define get_display_mode		0x0d
987 /*
988  *	The display module returns the Display Image Mode status.
989  */
990 #define get_signal_mode			0x0e
991 /*
992  *	The display module returns the Display Signal Mode.
993  */
994 #define get_diagnostic_result		0x0f
995 /*
996  *	The display module returns the self-diagnostic results following
997  *	a Sleep Out command.
998  */
999 #define enter_sleep_mode		0x10
1000 /*
1001  *	This command causes the display module to enter the Sleep mode.
1002  *	In this mode, all unnecessary blocks inside the display module are
1003  *	disabled except interface communication. This is the lowest power
1004  *	mode the display module supports.
1005  */
1006 #define exit_sleep_mode			0x11
1007 /*
1008  *	This command causes the display module to exit Sleep mode.
1009  *	All blocks inside the display module are enabled.
1010  */
1011 #define enter_partial_mode		0x12
1012 /*
1013  *	This command causes the display module to enter the Partial Display
1014  *	Mode. The Partial Display Mode window is described by the
1015  *	set_partial_area command.
1016  */
1017 #define enter_normal_mode		0x13
1018 /*
1019  *	This command causes the display module to enter the Normal mode.
1020  *	Normal Mode is defined as Partial Display mode and Scroll mode are off
1021  */
1022 #define exit_invert_mode		0x20
1023 /*
1024  *	This command causes the display module to stop inverting the image
1025  *	data on the display device. The frame memory contents remain unchanged.
1026  *	No status bits are changed.
1027  */
1028 #define enter_invert_mode		0x21
1029 /*
1030  *	This command causes the display module to invert the image data only on
1031  *	the display device. The frame memory contents remain unchanged.
1032  *	No status bits are changed.
1033  */
1034 #define set_gamma_curve			0x26
1035 /*
1036  *	This command selects the desired gamma curve for the display device.
1037  *	Four fixed gamma curves are defined in section DCS spec.
1038  */
1039 #define set_display_off			0x28
1040 /* ************************************************************************* *\
1041 This command causes the display module to stop displaying the image data
1042 on the display device. The frame memory contents remain unchanged.
1043 No status bits are changed.
1044 \* ************************************************************************* */
1045 #define set_display_on			0x29
1046 /* ************************************************************************* *\
1047 This command causes the display module to start displaying the image data
1048 on the display device. The frame memory contents remain unchanged.
1049 No status bits are changed.
1050 \* ************************************************************************* */
1051 #define set_column_address		0x2a
1052 /*
1053  *	This command defines the column extent of the frame memory accessed by
1054  *	the hostprocessor with the read_memory_continue and
1055  *	write_memory_continue commands.
1056  *	No status bits are changed.
1057  */
1058 #define set_page_addr			0x2b
1059 /*
1060  *	This command defines the page extent of the frame memory accessed by
1061  *	the host processor with the write_memory_continue and
1062  *	read_memory_continue command.
1063  *	No status bits are changed.
1064  */
1065 #define write_mem_start			0x2c
1066 /*
1067  *	This command transfers image data from the host processor to the
1068  *	display modules frame memory starting at the pixel location specified
1069  *	by preceding set_column_address and set_page_address commands.
1070  */
1071 #define set_partial_area		0x30
1072 /*
1073  *	This command defines the Partial Display mode s display area.
1074  *	There are two parameters associated with this command, the first
1075  *	defines the Start Row (SR) and the second the End Row (ER). SR and ER
1076  *	refer to the Frame Memory Line Pointer.
1077  */
1078 #define set_scroll_area			0x33
1079 /*
1080  *	This command defines the display modules Vertical Scrolling Area.
1081  */
1082 #define set_tear_off			0x34
1083 /*
1084  *	This command turns off the display modules Tearing Effect output
1085  *	signal on the TE signal line.
1086  */
1087 #define set_tear_on			0x35
1088 /*
1089  *	This command turns on the display modules Tearing Effect output signal
1090  *	on the TE signal line.
1091  */
1092 #define set_address_mode		0x36
1093 /*
1094  *	This command sets the data order for transfers from the host processor
1095  *	to display modules frame memory,bits B[7:5] and B3, and from the
1096  *	display modules frame memory to the display device, bits B[2:0] and B4.
1097  */
1098 #define set_scroll_start		0x37
1099 /*
1100  *	This command sets the start of the vertical scrolling area in the frame
1101  *	memory. The vertical scrolling area is fully defined when this command
1102  *	is used with the set_scroll_area command The set_scroll_start command
1103  *	has one parameter, the Vertical Scroll Pointer. The VSP defines the
1104  *	line in the frame memory that is written to the display device as the
1105  *	first line of the vertical scroll area.
1106  */
1107 #define exit_idle_mode			0x38
1108 /*
1109  *	This command causes the display module to exit Idle mode.
1110  */
1111 #define enter_idle_mode			0x39
1112 /*
1113  *	This command causes the display module to enter Idle Mode.
1114  *	In Idle Mode, color expression is reduced. Colors are shown on the
1115  *	display device using the MSB of each of the R, G and B color
1116  *	components in the frame memory
1117  */
1118 #define set_pixel_format		0x3a
1119 /*
1120  *	This command sets the pixel format for the RGB image data used by the
1121  *	interface.
1122  *	Bits D[6:4]  DPI Pixel Format Definition
1123  *	Bits D[2:0]  DBI Pixel Format Definition
1124  *	Bits D7 and D3 are not used.
1125  */
1126 #define DCS_PIXEL_FORMAT_3bpp		0x1
1127 #define DCS_PIXEL_FORMAT_8bpp		0x2
1128 #define DCS_PIXEL_FORMAT_12bpp		0x3
1129 #define DCS_PIXEL_FORMAT_16bpp		0x5
1130 #define DCS_PIXEL_FORMAT_18bpp		0x6
1131 #define DCS_PIXEL_FORMAT_24bpp		0x7
1132 
1133 #define write_mem_cont			0x3c
1134 
1135 /*
1136  *	This command transfers image data from the host processor to the
1137  *	display module's frame memory continuing from the pixel location
1138  *	following the previous write_memory_continue or write_memory_start
1139  *	command.
1140  */
1141 #define set_tear_scanline		0x44
1142 /*
1143  *	This command turns on the display modules Tearing Effect output signal
1144  *	on the TE signal line when the display module reaches line N.
1145  */
1146 #define get_scanline			0x45
1147 /*
1148  *	The display module returns the current scanline, N, used to update the
1149  *	 display device. The total number of scanlines on a display device is
1150  *	defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as
1151  *	the first line of V Sync and is denoted as Line 0.
1152  *	When in Sleep Mode, the value returned by get_scanline is undefined.
1153  */
1154 
1155 /* MCS or Generic COMMANDS */
1156 /* MCS/generic data type */
1157 #define GEN_SHORT_WRITE_0	0x03  /* generic short write, no parameters */
1158 #define GEN_SHORT_WRITE_1	0x13  /* generic short write, 1 parameters */
1159 #define GEN_SHORT_WRITE_2	0x23  /* generic short write, 2 parameters */
1160 #define GEN_READ_0		0x04  /* generic read, no parameters */
1161 #define GEN_READ_1		0x14  /* generic read, 1 parameters */
1162 #define GEN_READ_2		0x24  /* generic read, 2 parameters */
1163 #define GEN_LONG_WRITE		0x29  /* generic long write */
1164 #define MCS_SHORT_WRITE_0	0x05  /* MCS short write, no parameters */
1165 #define MCS_SHORT_WRITE_1	0x15  /* MCS short write, 1 parameters */
1166 #define MCS_READ		0x06  /* MCS read, no parameters */
1167 #define MCS_LONG_WRITE		0x39  /* MCS long write */
1168 /* MCS/generic commands */
1169 /* TPO MCS */
1170 #define write_display_profile		0x50
1171 #define write_display_brightness	0x51
1172 #define write_ctrl_display		0x53
1173 #define write_ctrl_cabc			0x55
1174   #define UI_IMAGE		0x01
1175   #define STILL_IMAGE		0x02
1176   #define MOVING_IMAGE		0x03
1177 #define write_hysteresis		0x57
1178 #define write_gamma_setting		0x58
1179 #define write_cabc_min_bright		0x5e
1180 #define write_kbbc_profile		0x60
1181 /* TMD MCS */
1182 #define tmd_write_display_brightness 0x8c
1183 
1184 /*
1185  *	This command is used to control ambient light, panel backlight
1186  *	brightness and gamma settings.
1187  */
1188 #define BRIGHT_CNTL_BLOCK_ON	(1 << 5)
1189 #define AMBIENT_LIGHT_SENSE_ON	(1 << 4)
1190 #define DISPLAY_DIMMING_ON	(1 << 3)
1191 #define BACKLIGHT_ON		(1 << 2)
1192 #define DISPLAY_BRIGHTNESS_AUTO	(1 << 1)
1193 #define GAMMA_AUTO		(1 << 0)
1194 
1195 /* DCS Interface Pixel Formats */
1196 #define DCS_PIXEL_FORMAT_3BPP	0x1
1197 #define DCS_PIXEL_FORMAT_8BPP	0x2
1198 #define DCS_PIXEL_FORMAT_12BPP	0x3
1199 #define DCS_PIXEL_FORMAT_16BPP	0x5
1200 #define DCS_PIXEL_FORMAT_18BPP	0x6
1201 #define DCS_PIXEL_FORMAT_24BPP	0x7
1202 /* ONE PARAMETER READ DATA */
1203 #define addr_mode_data		0xfc
1204 #define diag_res_data		0x00
1205 #define disp_mode_data		0x23
1206 #define pxl_fmt_data		0x77
1207 #define pwr_mode_data		0x74
1208 #define sig_mode_data		0x00
1209 /* TWO PARAMETERS READ DATA */
1210 #define scanline_data1		0xff
1211 #define scanline_data2		0xff
1212 #define NON_BURST_MODE_SYNC_PULSE	0x01	/* Non Burst Mode
1213 						 * with Sync Pulse
1214 						 */
1215 #define NON_BURST_MODE_SYNC_EVENTS	0x02	/* Non Burst Mode
1216 						 * with Sync events
1217 						 */
1218 #define BURST_MODE			0x03	/* Burst Mode */
1219 #define DBI_COMMAND_BUFFER_SIZE		0x240   /* 0x32 */    /* 0x120 */
1220 						/* Allocate at least
1221 						 * 0x100 Byte with 32
1222 						 * byte alignment
1223 						 */
1224 #define DBI_DATA_BUFFER_SIZE		0x120	/* Allocate at least
1225 						 * 0x100 Byte with 32
1226 						 * byte alignment
1227 						 */
1228 #define DBI_CB_TIME_OUT			0xFFFF
1229 
1230 #define GEN_FB_TIME_OUT			2000
1231 
1232 #define SKU_83				0x01
1233 #define SKU_100				0x02
1234 #define SKU_100L			0x04
1235 #define SKU_BYPASS			0x08
1236 
1237 /* Some handy macros for playing with bitfields. */
1238 #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1239 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
1240 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
1241 
1242 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1243 
1244 /* PCI config space */
1245 
1246 #define SB_PCKT         0x02100 /* cedarview */
1247 # define SB_OPCODE_MASK                         PSB_MASK(31, 16)
1248 # define SB_OPCODE_SHIFT                        16
1249 # define SB_OPCODE_READ                         0
1250 # define SB_OPCODE_WRITE                        1
1251 # define SB_DEST_MASK                           PSB_MASK(15, 8)
1252 # define SB_DEST_SHIFT                          8
1253 # define SB_DEST_DPLL                           0x88
1254 # define SB_BYTE_ENABLE_MASK                    PSB_MASK(7, 4)
1255 # define SB_BYTE_ENABLE_SHIFT                   4
1256 # define SB_BUSY                                (1 << 0)
1257 
1258 #define DSPCLK_GATE_D		0x6200
1259 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* Fixed value on CDV */
1260 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
1261 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6)
1262 
1263 #define RAMCLK_GATE_D		0x6210
1264 
1265 /* 32-bit value read/written from the DPIO reg. */
1266 #define SB_DATA		0x02104 /* cedarview */
1267 /* 32-bit address of the DPIO reg to be read/written. */
1268 #define SB_ADDR		0x02108 /* cedarview */
1269 #define DPIO_CFG	0x02110 /* cedarview */
1270 # define DPIO_MODE_SELECT_1			(1 << 3)
1271 # define DPIO_MODE_SELECT_0			(1 << 2)
1272 # define DPIO_SFR_BYPASS			(1 << 1)
1273 /* reset is active low */
1274 # define DPIO_CMN_RESET_N			(1 << 0)
1275 
1276 /* Cedarview sideband registers */
1277 #define _SB_M_A			0x8008
1278 #define _SB_M_B			0x8028
1279 #define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)
1280 # define SB_M_DIVIDER_MASK			(0xFF << 24)
1281 # define SB_M_DIVIDER_SHIFT			24
1282 
1283 #define _SB_N_VCO_A		0x8014
1284 #define _SB_N_VCO_B		0x8034
1285 #define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)
1286 #define SB_N_VCO_SEL_MASK			PSB_MASK(31, 30)
1287 #define SB_N_VCO_SEL_SHIFT			30
1288 #define SB_N_DIVIDER_MASK			PSB_MASK(29, 26)
1289 #define SB_N_DIVIDER_SHIFT			26
1290 #define SB_N_CB_TUNE_MASK			PSB_MASK(25, 24)
1291 #define SB_N_CB_TUNE_SHIFT			24
1292 
1293 #define _SB_REF_A		0x8018
1294 #define _SB_REF_B		0x8038
1295 #define SB_REF_SFR(pipe)	_PIPE(pipe, _SB_REF_A, _SB_REF_B)
1296 
1297 #define _SB_P_A			0x801c
1298 #define _SB_P_B			0x803c
1299 #define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)
1300 #define SB_P2_DIVIDER_MASK			PSB_MASK(31, 30)
1301 #define SB_P2_DIVIDER_SHIFT			30
1302 #define SB_P2_10				0 /* HDMI, DP, DAC */
1303 #define SB_P2_5				1 /* DAC */
1304 #define SB_P2_14				2 /* LVDS single */
1305 #define SB_P2_7				3 /* LVDS double */
1306 #define SB_P1_DIVIDER_MASK			PSB_MASK(15, 12)
1307 #define SB_P1_DIVIDER_SHIFT			12
1308 
1309 #define PSB_LANE0		0x120
1310 #define PSB_LANE1		0x220
1311 #define PSB_LANE2		0x2320
1312 #define PSB_LANE3		0x2420
1313 
1314 #define LANE_PLL_MASK		(0x7 << 20)
1315 #define LANE_PLL_ENABLE		(0x3 << 20)
1316 
1317 
1318 #endif
1319