1 /* 2 * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 * Author: Joonyoung Shim <jy0922.shim@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef __PLAT_S5P_REGS_USB_PHY_H 12 #define __PLAT_S5P_REGS_USB_PHY_H 13 14 #define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 15 16 #define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00) 17 #define PHY1_HSIC_NORMAL_MASK (0xf << 9) 18 #define PHY1_HSIC1_SLEEP (1 << 12) 19 #define PHY1_HSIC1_FORCE_SUSPEND (1 << 11) 20 #define PHY1_HSIC0_SLEEP (1 << 10) 21 #define PHY1_HSIC0_FORCE_SUSPEND (1 << 9) 22 23 #define PHY1_STD_NORMAL_MASK (0x7 << 6) 24 #define PHY1_STD_SLEEP (1 << 8) 25 #define PHY1_STD_ANALOG_POWERDOWN (1 << 7) 26 #define PHY1_STD_FORCE_SUSPEND (1 << 6) 27 28 #define PHY0_NORMAL_MASK (0x39 << 0) 29 #define PHY0_SLEEP (1 << 5) 30 #define PHY0_OTG_DISABLE (1 << 4) 31 #define PHY0_ANALOG_POWERDOWN (1 << 3) 32 #define PHY0_FORCE_SUSPEND (1 << 0) 33 34 #define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04) 35 #define PHY1_COMMON_ON_N (1 << 7) 36 #define PHY0_COMMON_ON_N (1 << 4) 37 #define PHY0_ID_PULLUP (1 << 2) 38 #define CLKSEL_MASK (0x3 << 0) 39 #define CLKSEL_SHIFT (0) 40 #define CLKSEL_48M (0x0 << 0) 41 #define CLKSEL_12M (0x2 << 0) 42 #define CLKSEL_24M (0x3 << 0) 43 44 #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) 45 #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) 46 #define HOST_LINK_PORT2_SWRST (1 << 9) 47 #define HOST_LINK_PORT1_SWRST (1 << 8) 48 #define HOST_LINK_PORT0_SWRST (1 << 7) 49 #define HOST_LINK_ALL_SWRST (1 << 6) 50 51 #define PHY1_SWRST_MASK (0x7 << 3) 52 #define PHY1_HSIC_SWRST (1 << 5) 53 #define PHY1_STD_SWRST (1 << 4) 54 #define PHY1_ALL_SWRST (1 << 3) 55 56 #define PHY0_SWRST_MASK (0x7 << 0) 57 #define PHY0_PHYLINK_SWRST (1 << 2) 58 #define PHY0_HLINK_SWRST (1 << 1) 59 #define PHY0_SWRST (1 << 0) 60 61 #define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34) 62 #define FPENABLEN (1 << 0) 63 64 #endif /* __PLAT_S5P_REGS_USB_PHY_H */ 65