1 /* 2 * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h 3 * 4 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> 5 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <mach/pcm027.h> 23 24 /* 25 * definitions relevant only when the PCM-990 26 * development base board is in use 27 */ 28 29 /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ 30 #define PCM990_CTRL_INT_IRQ_GPIO 9 31 #define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) 32 #define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING 33 #define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ 34 #define PCM990_CTRL_BASE 0xea000000 35 #define PCM990_CTRL_SIZE (1*1024*1024) 36 37 #define PCM990_CTRL_PWR_IRQ_GPIO 14 38 #define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) 39 #define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING 40 41 /* visible CPLD (U7) registers */ 42 #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ 43 #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ 44 #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ 45 #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ 46 47 #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ 48 #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ 49 #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ 50 #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ 51 52 #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ 53 #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ 54 #define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ 55 #define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ 56 57 #define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ 58 #define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ 59 #define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ 60 #define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ 61 #define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ 62 63 #define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ 64 #define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ 65 66 #define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ 67 #define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ 68 #define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ 69 #define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ 70 #define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ 71 72 #define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */ 73 #define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ 74 #define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ 75 #define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ 76 #define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ 77 78 #define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */ 79 #define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ 80 #define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ 81 #define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ 82 #define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ 83 84 #define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ 85 #define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ 86 #define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ 87 #define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ 88 #define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ 89 90 #define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ 91 #define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ 92 #define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ 93 #define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ 94 95 #define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ 96 #define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ 97 #define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ 98 99 #define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ 100 #define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ 101 #define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ 102 #define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ 103 #define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ 104 105 #define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE) 106 #define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS) 107 108 #ifndef __ASSEMBLY__ 109 # define __PCM990_CTRL_REG(x) \ 110 (*((volatile unsigned char *)PCM990_CTRL_P2V(x))) 111 #else 112 # define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x) 113 #endif 114 115 #define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) 116 #define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) 117 #define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0) 118 #define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1) 119 #define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2) 120 #define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) 121 #define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4) 122 #define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) 123 #define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) 124 #define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) 125 #define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8) 126 #define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9) 127 #define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10) 128 #define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11) 129 130 131 /* 132 * IDE 133 */ 134 #define PCM990_IDE_IRQ_GPIO 13 135 #define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) 136 #define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING 137 #define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ 138 #define PCM990_IDE_PLD_BASE 0xee000000 139 #define PCM990_IDE_PLD_SIZE (1*1024*1024) 140 141 /* visible CPLD (U6) registers */ 142 #define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ 143 #define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ 144 #define PCM990_IDE_STBY 0x0008 /* R System StandBy */ 145 146 #define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ 147 #define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ 148 #define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ 149 #define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ 150 151 #define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ 152 #define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ 153 #define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ 154 #define PCM990_IDE_RDY 0x0008 /* RDY */ 155 156 #define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ 157 #define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ 158 #define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ 159 #define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ 160 161 #define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ 162 #define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ 163 #define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ 164 #define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ 165 166 #define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) 167 #define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) 168 169 #ifndef __ASSEMBLY__ 170 # define __PCM990_IDE_PLD_REG(x) \ 171 (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x))) 172 #else 173 # define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x) 174 #endif 175 176 #define PCM990_IDE0 \ 177 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0) 178 #define PCM990_IDE1 \ 179 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1) 180 #define PCM990_IDE2 \ 181 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2) 182 #define PCM990_IDE3 \ 183 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3) 184 #define PCM990_IDE4 \ 185 __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4) 186 187 /* 188 * Compact Flash 189 */ 190 #define PCM990_CF_IRQ_GPIO 11 191 #define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) 192 #define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING 193 194 #define PCM990_CF_CD_GPIO 12 195 #define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) 196 #define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING 197 198 #define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ 199 #define PCM990_CF_PLD_BASE 0xef000000 200 #define PCM990_CF_PLD_SIZE (1*1024*1024) 201 #define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE) 202 #define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS) 203 204 /* visible CPLD (U6) registers */ 205 #define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ 206 #define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ 207 #define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ 208 #define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ 209 #define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ 210 211 #define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ 212 #define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ 213 #define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ 214 215 #define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ 216 #define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ 217 #define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ 218 #define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ 219 220 #define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ 221 #define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ 222 #define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ 223 #define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ 224 #define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ 225 226 #define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ 227 #define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ 228 #define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ 229 #define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ 230 #define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ 231 232 #define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ 233 #define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ 234 #define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ 235 #define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ 236 #define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ 237 238 #define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ 239 #define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ 240 #define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ 241 242 #ifndef __ASSEMBLY__ 243 # define __PCM990_CF_PLD_REG(x) \ 244 (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x))) 245 #else 246 # define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x) 247 #endif 248 249 #define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0) 250 #define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1) 251 #define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2) 252 #define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3) 253 #define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4) 254 #define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5) 255 #define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6) 256 257 /* 258 * Wolfson AC97 Touch 259 */ 260 #define PCM990_AC97_IRQ_GPIO 10 261 #define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) 262 #define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING 263 264 /* 265 * MMC phyCORE 266 */ 267 #define PCM990_MMC0_IRQ_GPIO 9 268 #define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) 269 #define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING 270 271 /* 272 * USB phyCore 273 */ 274 #define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) 275 #define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) 276