1 /* 2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights 3 * reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the NetLogic 9 * license below: 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in 19 * the documentation and/or other materials provided with the 20 * distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef __NLM_HAL_IOMAP_H__ 36 #define __NLM_HAL_IOMAP_H__ 37 38 #define XLP_DEFAULT_IO_BASE 0x18000000 39 #define NMI_BASE 0xbfc00000 40 #define XLP_IO_CLK 133333333 41 42 #define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ 43 #define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) 44 #define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) 45 #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 46 #define XLP_IO_PCI_HDRSZ 0x100 47 #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 48 #define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ 49 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 50 51 #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) 52 /* coherent inter chip */ 53 #define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) 54 #define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) 55 #define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) 56 #define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) 57 58 #define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) 59 #define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) 60 #define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) 61 #define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) 62 #define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) 63 64 #define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) 65 #define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) 66 #define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) 67 #define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) 68 #define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) 69 #define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) 70 #define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) 71 72 #define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) 73 #define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) 74 75 #define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) 76 77 #define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) 78 #define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) 79 #define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) 80 81 #define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) 82 #define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) 83 #define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) 84 #define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i) 85 #define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) 86 #define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) 87 #define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) 88 /* system management */ 89 #define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) 90 #define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) 91 92 #define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) 93 #define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) 94 #define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) 95 /* SD flash */ 96 #define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) 97 #define XLP_IO_MMC_OFFSET(node, slot) \ 98 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 99 100 /* PCI config header register id's */ 101 #define XLP_PCI_CFGREG0 0x00 102 #define XLP_PCI_CFGREG1 0x01 103 #define XLP_PCI_CFGREG2 0x02 104 #define XLP_PCI_CFGREG3 0x03 105 #define XLP_PCI_CFGREG4 0x04 106 #define XLP_PCI_CFGREG5 0x05 107 #define XLP_PCI_DEVINFO_REG0 0x30 108 #define XLP_PCI_DEVINFO_REG1 0x31 109 #define XLP_PCI_DEVINFO_REG2 0x32 110 #define XLP_PCI_DEVINFO_REG3 0x33 111 #define XLP_PCI_DEVINFO_REG4 0x34 112 #define XLP_PCI_DEVINFO_REG5 0x35 113 #define XLP_PCI_DEVINFO_REG6 0x36 114 #define XLP_PCI_DEVINFO_REG7 0x37 115 #define XLP_PCI_DEVSCRATCH_REG0 0x38 116 #define XLP_PCI_DEVSCRATCH_REG1 0x39 117 #define XLP_PCI_DEVSCRATCH_REG2 0x3a 118 #define XLP_PCI_DEVSCRATCH_REG3 0x3b 119 #define XLP_PCI_MSGSTN_REG 0x3c 120 #define XLP_PCI_IRTINFO_REG 0x3d 121 #define XLP_PCI_UCODEINFO_REG 0x3e 122 #define XLP_PCI_SBB_WT_REG 0x3f 123 124 /* PCI IDs for SoC device */ 125 #define PCI_VENDOR_NETLOGIC 0x184e 126 127 #define PCI_DEVICE_ID_NLM_ROOT 0x1001 128 #define PCI_DEVICE_ID_NLM_ICI 0x1002 129 #define PCI_DEVICE_ID_NLM_PIC 0x1003 130 #define PCI_DEVICE_ID_NLM_PCIE 0x1004 131 #define PCI_DEVICE_ID_NLM_EHCI 0x1007 132 #define PCI_DEVICE_ID_NLM_ILK 0x1008 133 #define PCI_DEVICE_ID_NLM_NAE 0x1009 134 #define PCI_DEVICE_ID_NLM_POE 0x100A 135 #define PCI_DEVICE_ID_NLM_FMN 0x100B 136 #define PCI_DEVICE_ID_NLM_RAID 0x100D 137 #define PCI_DEVICE_ID_NLM_SAE 0x100D 138 #define PCI_DEVICE_ID_NLM_RSA 0x100E 139 #define PCI_DEVICE_ID_NLM_CMP 0x100F 140 #define PCI_DEVICE_ID_NLM_UART 0x1010 141 #define PCI_DEVICE_ID_NLM_I2C 0x1011 142 #define PCI_DEVICE_ID_NLM_NOR 0x1015 143 #define PCI_DEVICE_ID_NLM_NAND 0x1016 144 #define PCI_DEVICE_ID_NLM_MMC 0x1018 145 146 #ifndef __ASSEMBLY__ 147 148 #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 149 #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) 150 151 #endif /* !__ASSEMBLY */ 152 153 #endif /* __NLM_HAL_IOMAP_H__ */ 154