1 /* 2 * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields 3 * 4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 5 * 6 * Benoit Cousson (b-cousson@ti.com) 7 * Santosh Shilimkar (santosh.shilimkar@ti.com) 8 * 9 * This file is automatically generated from the OMAP hardware databases. 10 * We respectfully ask that any modifications to this file be coordinated 11 * with the public linux-omap@vger.kernel.org mailing list and the 12 * authors above to ensure that the autogeneration scripts are kept 13 * up-to-date with the file contents. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 20 #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H 21 #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H 22 23 24 /* Base address */ 25 #define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 26 27 /* Registers offset */ 28 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 29 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 30 #define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 31 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 32 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc 33 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 34 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 35 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 36 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec 37 #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 38 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 39 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 40 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 41 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac 42 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 43 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 44 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 45 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc 46 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 47 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 48 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 49 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 50 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 51 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 52 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c 53 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 54 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 55 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 56 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c 57 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 58 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 59 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 60 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c 61 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 62 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 63 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 64 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c 65 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 66 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 67 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 68 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c 69 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 70 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 71 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 72 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c 73 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 74 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 75 #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 76 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 77 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 78 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 79 #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c 80 81 /* Registers shifts and masks */ 82 83 /* IP_REVISION */ 84 #define OMAP4_IP_REV_SCHEME_SHIFT 30 85 #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) 86 #define OMAP4_IP_REV_FUNC_SHIFT 16 87 #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) 88 #define OMAP4_IP_REV_RTL_SHIFT 11 89 #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) 90 #define OMAP4_IP_REV_MAJOR_SHIFT 8 91 #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) 92 #define OMAP4_IP_REV_CUSTOM_SHIFT 6 93 #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) 94 #define OMAP4_IP_REV_MINOR_SHIFT 0 95 #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) 96 97 /* IP_HWINFO */ 98 #define OMAP4_IP_HWINFO_SHIFT 0 99 #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) 100 101 /* IP_SYSCONFIG */ 102 #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 103 #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) 104 105 /* PADCONF_WAKEUPEVENT_0 */ 106 #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 107 #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) 108 #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 109 #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) 110 #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 111 #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) 112 #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 113 #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) 114 #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 115 #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) 116 #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 117 #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) 118 #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 119 #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) 120 #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 121 #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) 122 #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 123 #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) 124 #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 125 #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) 126 #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 127 #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) 128 #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 129 #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) 130 #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 131 #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) 132 #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 133 #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) 134 #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 135 #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) 136 #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 137 #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) 138 #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 139 #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) 140 #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 141 #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) 142 #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 143 #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) 144 #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 145 #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) 146 #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 147 #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) 148 #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 149 #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) 150 #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 151 #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) 152 #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 153 #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) 154 #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 155 #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 156 #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 157 #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 158 #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 159 #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 160 #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 161 #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 162 #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 163 #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 164 #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 165 #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 166 #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 167 #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 168 #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 169 #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 170 171 /* PADCONF_WAKEUPEVENT_1 */ 172 #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 173 #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) 174 #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 175 #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) 176 #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 177 #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) 178 #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 179 #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) 180 #define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 181 #define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) 182 #define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 183 #define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) 184 #define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 185 #define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) 186 #define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 187 #define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) 188 #define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 189 #define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) 190 #define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 191 #define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) 192 #define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 193 #define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) 194 #define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 195 #define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) 196 #define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 197 #define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) 198 #define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 199 #define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) 200 #define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 201 #define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) 202 #define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 203 #define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) 204 #define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 205 #define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) 206 #define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 207 #define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) 208 #define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 209 #define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) 210 #define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 211 #define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) 212 #define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 213 #define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) 214 #define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 215 #define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) 216 #define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 217 #define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) 218 #define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 219 #define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) 220 #define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 221 #define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 222 #define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 223 #define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 224 #define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 225 #define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 226 #define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 227 #define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 228 #define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 229 #define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 230 #define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 231 #define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 232 #define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 233 #define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 234 #define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 235 #define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 236 237 /* PADCONF_WAKEUPEVENT_2 */ 238 #define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 239 #define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) 240 #define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 241 #define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) 242 #define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 243 #define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) 244 #define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 245 #define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) 246 #define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 247 #define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) 248 #define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 249 #define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) 250 #define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 251 #define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) 252 #define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 253 #define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) 254 #define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 255 #define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) 256 #define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 257 #define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) 258 #define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 259 #define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) 260 #define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 261 #define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) 262 #define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 263 #define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) 264 #define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 265 #define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) 266 #define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 267 #define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) 268 #define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 269 #define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) 270 #define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 271 #define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) 272 #define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 273 #define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) 274 #define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 275 #define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) 276 #define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 277 #define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) 278 #define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 279 #define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) 280 #define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 281 #define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) 282 #define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 283 #define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) 284 #define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 285 #define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) 286 #define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 287 #define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 288 #define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 289 #define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 290 #define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 291 #define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 292 #define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 293 #define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 294 #define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 295 #define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 296 #define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 297 #define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 298 #define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 299 #define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 300 #define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 301 #define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 302 303 /* PADCONF_WAKEUPEVENT_3 */ 304 #define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 305 #define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) 306 #define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 307 #define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) 308 #define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 309 #define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) 310 #define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 311 #define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) 312 #define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 313 #define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) 314 #define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 315 #define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) 316 #define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 317 #define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) 318 #define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 319 #define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) 320 #define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 321 #define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) 322 #define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 323 #define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) 324 #define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 325 #define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) 326 #define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 327 #define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) 328 #define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 329 #define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) 330 #define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 331 #define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) 332 #define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 333 #define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) 334 #define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 335 #define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) 336 #define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 337 #define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) 338 #define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 339 #define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) 340 #define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 341 #define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) 342 #define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 343 #define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) 344 #define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 345 #define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) 346 #define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 347 #define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) 348 #define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 349 #define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) 350 #define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 351 #define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) 352 #define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 353 #define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 354 #define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 355 #define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 356 #define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 357 #define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 358 #define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 359 #define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 360 #define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 361 #define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 362 #define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 363 #define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 364 #define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 365 #define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 366 #define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 367 #define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 368 369 /* PADCONF_WAKEUPEVENT_4 */ 370 #define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 371 #define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) 372 #define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 373 #define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) 374 #define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 375 #define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) 376 #define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 377 #define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) 378 #define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 379 #define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) 380 #define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 381 #define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) 382 #define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 383 #define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) 384 #define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 385 #define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) 386 #define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 387 #define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) 388 #define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 389 #define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) 390 #define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 391 #define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) 392 #define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 393 #define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) 394 #define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 395 #define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) 396 #define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 397 #define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) 398 #define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 399 #define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) 400 #define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 401 #define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) 402 #define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 403 #define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) 404 #define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 405 #define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) 406 #define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 407 #define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) 408 #define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 409 #define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) 410 #define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 411 #define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) 412 #define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 413 #define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) 414 #define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 415 #define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) 416 #define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 417 #define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) 418 #define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 419 #define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 420 #define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 421 #define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 422 #define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 423 #define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 424 #define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 425 #define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 426 #define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 427 #define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 428 #define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 429 #define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 430 #define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 431 #define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 432 #define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 433 #define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 434 435 /* PADCONF_WAKEUPEVENT_5 */ 436 #define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 437 #define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) 438 #define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 439 #define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) 440 #define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 441 #define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) 442 #define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 443 #define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) 444 #define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 445 #define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) 446 #define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 447 #define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) 448 #define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 449 #define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) 450 #define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 451 #define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) 452 #define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 453 #define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) 454 #define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 455 #define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) 456 #define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 457 #define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) 458 #define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 459 #define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) 460 #define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 461 #define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) 462 #define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 463 #define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) 464 #define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 465 #define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) 466 #define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 467 #define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) 468 #define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 469 #define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) 470 #define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 471 #define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) 472 #define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 473 #define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) 474 #define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 475 #define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) 476 #define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 477 #define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) 478 #define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 479 #define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) 480 #define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 481 #define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) 482 #define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 483 #define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) 484 #define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 485 #define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 486 #define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 487 #define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 488 #define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 489 #define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 490 #define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 491 #define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 492 #define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 493 #define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 494 #define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 495 #define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 496 #define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 497 #define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 498 #define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 499 #define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 500 501 /* PADCONF_WAKEUPEVENT_6 */ 502 #define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 503 #define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) 504 #define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 505 #define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) 506 #define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 507 #define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) 508 #define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 509 #define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) 510 #define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 511 #define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) 512 #define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 513 #define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) 514 #define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 515 #define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) 516 #define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 517 #define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) 518 519 /* CONTROL_PADCONF_GLOBAL */ 520 #define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 521 #define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) 522 523 /* CONTROL_PADCONF_MODE */ 524 #define OMAP4_VDDS_DV_BANK0_SHIFT 31 525 #define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) 526 #define OMAP4_VDDS_DV_BANK1_SHIFT 30 527 #define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) 528 #define OMAP4_VDDS_DV_BANK3_SHIFT 29 529 #define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) 530 #define OMAP4_VDDS_DV_BANK4_SHIFT 28 531 #define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) 532 #define OMAP4_VDDS_DV_BANK5_SHIFT 27 533 #define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) 534 #define OMAP4_VDDS_DV_BANK6_SHIFT 26 535 #define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) 536 #define OMAP4_VDDS_DV_C2C_SHIFT 25 537 #define OMAP4_VDDS_DV_C2C_MASK (1 << 25) 538 #define OMAP4_VDDS_DV_CAM_SHIFT 24 539 #define OMAP4_VDDS_DV_CAM_MASK (1 << 24) 540 #define OMAP4_VDDS_DV_GPMC_SHIFT 23 541 #define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) 542 #define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 543 #define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) 544 545 /* CONTROL_SMART1IO_PADCONF_0 */ 546 #define OMAP4_ABE_DR0_SC_SHIFT 30 547 #define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) 548 #define OMAP4_CAM_DR0_SC_SHIFT 28 549 #define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) 550 #define OMAP4_FREF_DR2_SC_SHIFT 26 551 #define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) 552 #define OMAP4_FREF_DR3_SC_SHIFT 24 553 #define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) 554 #define OMAP4_GPIO_DR8_SC_SHIFT 22 555 #define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) 556 #define OMAP4_GPIO_DR9_SC_SHIFT 20 557 #define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) 558 #define OMAP4_GPMC_DR2_SC_SHIFT 18 559 #define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) 560 #define OMAP4_GPMC_DR3_SC_SHIFT 16 561 #define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) 562 #define OMAP4_GPMC_DR6_SC_SHIFT 14 563 #define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) 564 #define OMAP4_HDMI_DR0_SC_SHIFT 12 565 #define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) 566 #define OMAP4_MCSPI1_DR0_SC_SHIFT 10 567 #define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) 568 #define OMAP4_UART1_DR0_SC_SHIFT 8 569 #define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) 570 #define OMAP4_UART3_DR0_SC_SHIFT 6 571 #define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) 572 #define OMAP4_UART3_DR1_SC_SHIFT 4 573 #define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) 574 #define OMAP4_UNIPRO_DR0_SC_SHIFT 2 575 #define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) 576 #define OMAP4_UNIPRO_DR1_SC_SHIFT 0 577 #define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) 578 579 /* CONTROL_SMART1IO_PADCONF_1 */ 580 #define OMAP4_ABE_DR0_LB_SHIFT 30 581 #define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) 582 #define OMAP4_CAM_DR0_LB_SHIFT 28 583 #define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) 584 #define OMAP4_FREF_DR2_LB_SHIFT 26 585 #define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) 586 #define OMAP4_FREF_DR3_LB_SHIFT 24 587 #define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) 588 #define OMAP4_GPIO_DR8_LB_SHIFT 22 589 #define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) 590 #define OMAP4_GPIO_DR9_LB_SHIFT 20 591 #define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) 592 #define OMAP4_GPMC_DR2_LB_SHIFT 18 593 #define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) 594 #define OMAP4_GPMC_DR3_LB_SHIFT 16 595 #define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) 596 #define OMAP4_GPMC_DR6_LB_SHIFT 14 597 #define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) 598 #define OMAP4_HDMI_DR0_LB_SHIFT 12 599 #define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) 600 #define OMAP4_MCSPI1_DR0_LB_SHIFT 10 601 #define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) 602 #define OMAP4_UART1_DR0_LB_SHIFT 8 603 #define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) 604 #define OMAP4_UART3_DR0_LB_SHIFT 6 605 #define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) 606 #define OMAP4_UART3_DR1_LB_SHIFT 4 607 #define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) 608 #define OMAP4_UNIPRO_DR0_LB_SHIFT 2 609 #define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) 610 #define OMAP4_UNIPRO_DR1_LB_SHIFT 0 611 #define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) 612 613 /* CONTROL_SMART2IO_PADCONF_0 */ 614 #define OMAP4_C2C_DR0_LB_SHIFT 31 615 #define OMAP4_C2C_DR0_LB_MASK (1 << 31) 616 #define OMAP4_DPM_DR1_LB_SHIFT 30 617 #define OMAP4_DPM_DR1_LB_MASK (1 << 30) 618 #define OMAP4_DPM_DR2_LB_SHIFT 29 619 #define OMAP4_DPM_DR2_LB_MASK (1 << 29) 620 #define OMAP4_DPM_DR3_LB_SHIFT 28 621 #define OMAP4_DPM_DR3_LB_MASK (1 << 28) 622 #define OMAP4_GPIO_DR0_LB_SHIFT 27 623 #define OMAP4_GPIO_DR0_LB_MASK (1 << 27) 624 #define OMAP4_GPIO_DR1_LB_SHIFT 26 625 #define OMAP4_GPIO_DR1_LB_MASK (1 << 26) 626 #define OMAP4_GPIO_DR10_LB_SHIFT 25 627 #define OMAP4_GPIO_DR10_LB_MASK (1 << 25) 628 #define OMAP4_GPIO_DR2_LB_SHIFT 24 629 #define OMAP4_GPIO_DR2_LB_MASK (1 << 24) 630 #define OMAP4_GPMC_DR0_LB_SHIFT 23 631 #define OMAP4_GPMC_DR0_LB_MASK (1 << 23) 632 #define OMAP4_GPMC_DR1_LB_SHIFT 22 633 #define OMAP4_GPMC_DR1_LB_MASK (1 << 22) 634 #define OMAP4_GPMC_DR4_LB_SHIFT 21 635 #define OMAP4_GPMC_DR4_LB_MASK (1 << 21) 636 #define OMAP4_GPMC_DR5_LB_SHIFT 20 637 #define OMAP4_GPMC_DR5_LB_MASK (1 << 20) 638 #define OMAP4_GPMC_DR7_LB_SHIFT 19 639 #define OMAP4_GPMC_DR7_LB_MASK (1 << 19) 640 #define OMAP4_HSI2_DR0_LB_SHIFT 18 641 #define OMAP4_HSI2_DR0_LB_MASK (1 << 18) 642 #define OMAP4_HSI2_DR1_LB_SHIFT 17 643 #define OMAP4_HSI2_DR1_LB_MASK (1 << 17) 644 #define OMAP4_HSI2_DR2_LB_SHIFT 16 645 #define OMAP4_HSI2_DR2_LB_MASK (1 << 16) 646 #define OMAP4_KPD_DR0_LB_SHIFT 15 647 #define OMAP4_KPD_DR0_LB_MASK (1 << 15) 648 #define OMAP4_KPD_DR1_LB_SHIFT 14 649 #define OMAP4_KPD_DR1_LB_MASK (1 << 14) 650 #define OMAP4_PDM_DR0_LB_SHIFT 13 651 #define OMAP4_PDM_DR0_LB_MASK (1 << 13) 652 #define OMAP4_SDMMC2_DR0_LB_SHIFT 12 653 #define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) 654 #define OMAP4_SDMMC3_DR0_LB_SHIFT 11 655 #define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) 656 #define OMAP4_SDMMC4_DR0_LB_SHIFT 10 657 #define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) 658 #define OMAP4_SDMMC4_DR1_LB_SHIFT 9 659 #define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) 660 #define OMAP4_SPI3_DR0_LB_SHIFT 8 661 #define OMAP4_SPI3_DR0_LB_MASK (1 << 8) 662 #define OMAP4_SPI3_DR1_LB_SHIFT 7 663 #define OMAP4_SPI3_DR1_LB_MASK (1 << 7) 664 #define OMAP4_UART3_DR2_LB_SHIFT 6 665 #define OMAP4_UART3_DR2_LB_MASK (1 << 6) 666 #define OMAP4_UART3_DR3_LB_SHIFT 5 667 #define OMAP4_UART3_DR3_LB_MASK (1 << 5) 668 #define OMAP4_UART3_DR4_LB_SHIFT 4 669 #define OMAP4_UART3_DR4_LB_MASK (1 << 4) 670 #define OMAP4_UART3_DR5_LB_SHIFT 3 671 #define OMAP4_UART3_DR5_LB_MASK (1 << 3) 672 #define OMAP4_USBA0_DR1_LB_SHIFT 2 673 #define OMAP4_USBA0_DR1_LB_MASK (1 << 2) 674 #define OMAP4_USBA_DR2_LB_SHIFT 1 675 #define OMAP4_USBA_DR2_LB_MASK (1 << 1) 676 677 /* CONTROL_SMART2IO_PADCONF_1 */ 678 #define OMAP4_USBB1_DR0_LB_SHIFT 31 679 #define OMAP4_USBB1_DR0_LB_MASK (1 << 31) 680 #define OMAP4_USBB2_DR0_LB_SHIFT 30 681 #define OMAP4_USBB2_DR0_LB_MASK (1 << 30) 682 #define OMAP4_USBA0_DR0_LB_SHIFT 29 683 #define OMAP4_USBA0_DR0_LB_MASK (1 << 29) 684 685 /* CONTROL_SMART3IO_PADCONF_0 */ 686 #define OMAP4_DMIC_DR0_MB_SHIFT 30 687 #define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) 688 #define OMAP4_GPIO_DR3_MB_SHIFT 28 689 #define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) 690 #define OMAP4_GPIO_DR4_MB_SHIFT 26 691 #define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) 692 #define OMAP4_GPIO_DR5_MB_SHIFT 24 693 #define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) 694 #define OMAP4_GPIO_DR6_MB_SHIFT 22 695 #define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) 696 #define OMAP4_HSI_DR1_MB_SHIFT 20 697 #define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) 698 #define OMAP4_HSI_DR2_MB_SHIFT 18 699 #define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) 700 #define OMAP4_HSI_DR3_MB_SHIFT 16 701 #define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) 702 #define OMAP4_MCBSP2_DR0_MB_SHIFT 14 703 #define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) 704 #define OMAP4_MCSPI4_DR0_MB_SHIFT 12 705 #define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) 706 #define OMAP4_MCSPI4_DR1_MB_SHIFT 10 707 #define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) 708 #define OMAP4_SDMMC3_DR0_MB_SHIFT 8 709 #define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) 710 #define OMAP4_SPI2_DR0_MB_SHIFT 0 711 #define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) 712 713 /* CONTROL_SMART3IO_PADCONF_1 */ 714 #define OMAP4_SPI2_DR1_MB_SHIFT 30 715 #define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) 716 #define OMAP4_SPI2_DR2_MB_SHIFT 28 717 #define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) 718 #define OMAP4_UART2_DR0_MB_SHIFT 26 719 #define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) 720 #define OMAP4_UART2_DR1_MB_SHIFT 24 721 #define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) 722 #define OMAP4_UART4_DR0_MB_SHIFT 22 723 #define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) 724 #define OMAP4_HSI_DR0_MB_SHIFT 20 725 #define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) 726 727 /* CONTROL_SMART3IO_PADCONF_2 */ 728 #define OMAP4_DMIC_DR0_LB_SHIFT 31 729 #define OMAP4_DMIC_DR0_LB_MASK (1 << 31) 730 #define OMAP4_GPIO_DR3_LB_SHIFT 30 731 #define OMAP4_GPIO_DR3_LB_MASK (1 << 30) 732 #define OMAP4_GPIO_DR4_LB_SHIFT 29 733 #define OMAP4_GPIO_DR4_LB_MASK (1 << 29) 734 #define OMAP4_GPIO_DR5_LB_SHIFT 28 735 #define OMAP4_GPIO_DR5_LB_MASK (1 << 28) 736 #define OMAP4_GPIO_DR6_LB_SHIFT 27 737 #define OMAP4_GPIO_DR6_LB_MASK (1 << 27) 738 #define OMAP4_HSI_DR1_LB_SHIFT 26 739 #define OMAP4_HSI_DR1_LB_MASK (1 << 26) 740 #define OMAP4_HSI_DR2_LB_SHIFT 25 741 #define OMAP4_HSI_DR2_LB_MASK (1 << 25) 742 #define OMAP4_HSI_DR3_LB_SHIFT 24 743 #define OMAP4_HSI_DR3_LB_MASK (1 << 24) 744 #define OMAP4_MCBSP2_DR0_LB_SHIFT 23 745 #define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) 746 #define OMAP4_MCSPI4_DR0_LB_SHIFT 22 747 #define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) 748 #define OMAP4_MCSPI4_DR1_LB_SHIFT 21 749 #define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) 750 #define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 751 #define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) 752 #define OMAP4_SPI2_DR0_LB_SHIFT 16 753 #define OMAP4_SPI2_DR0_LB_MASK (1 << 16) 754 #define OMAP4_SPI2_DR1_LB_SHIFT 15 755 #define OMAP4_SPI2_DR1_LB_MASK (1 << 15) 756 #define OMAP4_SPI2_DR2_LB_SHIFT 14 757 #define OMAP4_SPI2_DR2_LB_MASK (1 << 14) 758 #define OMAP4_UART2_DR0_LB_SHIFT 13 759 #define OMAP4_UART2_DR0_LB_MASK (1 << 13) 760 #define OMAP4_UART2_DR1_LB_SHIFT 12 761 #define OMAP4_UART2_DR1_LB_MASK (1 << 12) 762 #define OMAP4_UART4_DR0_LB_SHIFT 11 763 #define OMAP4_UART4_DR0_LB_MASK (1 << 11) 764 #define OMAP4_HSI_DR0_LB_SHIFT 10 765 #define OMAP4_HSI_DR0_LB_MASK (1 << 10) 766 767 /* CONTROL_USBB_HSIC */ 768 #define OMAP4_USBB2_DR1_SR_SHIFT 30 769 #define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) 770 #define OMAP4_USBB2_DR1_I_SHIFT 27 771 #define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) 772 #define OMAP4_USBB1_DR1_SR_SHIFT 25 773 #define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) 774 #define OMAP4_USBB1_DR1_I_SHIFT 22 775 #define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) 776 #define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 777 #define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) 778 #define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 779 #define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) 780 #define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 781 #define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) 782 #define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 783 #define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) 784 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 785 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) 786 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 787 #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) 788 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 789 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) 790 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 791 #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) 792 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 793 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) 794 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 795 #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) 796 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 797 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) 798 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 799 #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) 800 801 /* CONTROL_SLIMBUS */ 802 #define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 803 #define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) 804 #define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 805 #define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) 806 #define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 807 #define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) 808 #define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 809 #define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) 810 #define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 811 #define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) 812 #define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 813 #define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) 814 #define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 815 #define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) 816 #define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 817 #define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) 818 819 /* CONTROL_PBIASLITE */ 820 #define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 821 #define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) 822 #define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 823 #define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) 824 #define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 825 #define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) 826 #define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 827 #define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) 828 #define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 829 #define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) 830 #define OMAP4_MMC1_PWRDNZ_SHIFT 26 831 #define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) 832 #define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 833 #define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) 834 #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 835 #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) 836 #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 837 #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) 838 #define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 839 #define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) 840 #define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 841 #define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) 842 #define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 843 #define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) 844 845 /* CONTROL_I2C_0 */ 846 #define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 847 #define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) 848 #define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 849 #define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) 850 #define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 851 #define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) 852 #define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 853 #define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) 854 #define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 855 #define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) 856 #define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 857 #define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) 858 #define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 859 #define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) 860 #define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 861 #define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) 862 #define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 863 #define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) 864 #define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 865 #define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) 866 #define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 867 #define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) 868 #define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 869 #define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) 870 #define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 871 #define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) 872 #define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 873 #define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) 874 #define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 875 #define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) 876 #define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 877 #define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) 878 #define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 879 #define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) 880 #define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 881 #define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) 882 #define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 883 #define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) 884 #define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 885 #define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) 886 #define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 887 #define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) 888 #define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 889 #define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) 890 #define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 891 #define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) 892 #define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 893 #define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) 894 895 /* CONTROL_CAMERA_RX */ 896 #define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 897 #define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) 898 #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 899 #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) 900 #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 901 #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) 902 #define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 903 #define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) 904 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 905 #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) 906 #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 907 #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) 908 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 909 #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) 910 #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 911 #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) 912 913 /* CONTROL_AVDAC */ 914 #define OMAP4_AVDAC_ACEN_SHIFT 31 915 #define OMAP4_AVDAC_ACEN_MASK (1 << 31) 916 #define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 917 #define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) 918 #define OMAP4_AVDAC_INPUTINV_SHIFT 29 919 #define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) 920 #define OMAP4_AVDAC_CTL_SHIFT 13 921 #define OMAP4_AVDAC_CTL_MASK (0xffff << 13) 922 #define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 923 #define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) 924 925 /* CONTROL_HDMI_TX_PHY */ 926 #define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 927 #define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) 928 #define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 929 #define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) 930 #define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 931 #define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) 932 #define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 933 #define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) 934 935 /* CONTROL_MMC2 */ 936 #define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 937 #define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) 938 939 /* CONTROL_DSIPHY */ 940 #define OMAP4_DSI2_LANEENABLE_SHIFT 29 941 #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 942 #define OMAP4_DSI1_LANEENABLE_SHIFT 24 943 #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 944 #define OMAP4_DSI1_PIPD_SHIFT 19 945 #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 946 #define OMAP4_DSI2_PIPD_SHIFT 14 947 #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 948 949 /* CONTROL_MCBSPLP */ 950 #define OMAP4_ALBCTRLRX_FSX_SHIFT 31 951 #define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) 952 #define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 953 #define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) 954 #define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 955 #define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) 956 957 /* CONTROL_USB2PHYCORE */ 958 #define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 959 #define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) 960 #define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 961 #define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) 962 #define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 963 #define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) 964 #define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 965 #define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) 966 #define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 967 #define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) 968 #define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 969 #define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) 970 #define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 971 #define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) 972 #define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 973 #define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) 974 #define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 975 #define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) 976 #define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 977 #define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) 978 #define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 979 #define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) 980 #define OMAP4_USB2PHY_DATADET_SHIFT 18 981 #define OMAP4_USB2PHY_DATADET_MASK (1 << 18) 982 #define OMAP4_USB2PHY_SINKONDP_SHIFT 17 983 #define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) 984 #define OMAP4_USB2PHY_SRCONDM_SHIFT 16 985 #define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) 986 #define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 987 #define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) 988 #define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 989 #define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) 990 #define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 991 #define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) 992 #define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 993 #define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) 994 #define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 995 #define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) 996 #define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 997 #define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) 998 #define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 999 #define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) 1000 #define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 1001 #define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) 1002 #define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 1003 #define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) 1004 #define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 1005 #define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) 1006 #define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 1007 #define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) 1008 1009 /* CONTROL_I2C_1 */ 1010 #define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 1011 #define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) 1012 #define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 1013 #define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) 1014 #define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 1015 #define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) 1016 #define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 1017 #define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) 1018 #define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 1019 #define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) 1020 #define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 1021 #define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) 1022 #define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 1023 #define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) 1024 #define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 1025 #define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) 1026 #define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 1027 #define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) 1028 #define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 1029 #define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) 1030 1031 /* CONTROL_MMC1 */ 1032 #define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 1033 #define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) 1034 #define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 1035 #define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) 1036 #define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 1037 #define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) 1038 #define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 1039 #define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) 1040 #define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 1041 #define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) 1042 #define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 1043 #define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) 1044 #define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 1045 #define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) 1046 #define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 1047 #define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) 1048 #define OMAP4_USB_FD_CDEN_SHIFT 23 1049 #define OMAP4_USB_FD_CDEN_MASK (1 << 23) 1050 #define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 1051 #define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) 1052 #define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 1053 #define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) 1054 1055 /* CONTROL_HSI */ 1056 #define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 1057 #define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) 1058 #define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 1059 #define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) 1060 #define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 1061 #define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) 1062 #define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 1063 #define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) 1064 1065 /* CONTROL_USB */ 1066 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 1067 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) 1068 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 1069 #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) 1070 1071 /* CONTROL_HDQ */ 1072 #define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 1073 #define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) 1074 1075 /* CONTROL_LPDDR2IO1_0 */ 1076 #define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 1077 #define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) 1078 #define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 1079 #define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) 1080 #define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 1081 #define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) 1082 #define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 1083 #define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) 1084 #define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 1085 #define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) 1086 #define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 1087 #define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) 1088 #define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 1089 #define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) 1090 #define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 1091 #define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) 1092 #define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 1093 #define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) 1094 #define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 1095 #define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) 1096 #define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 1097 #define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) 1098 #define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 1099 #define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) 1100 1101 /* CONTROL_LPDDR2IO1_1 */ 1102 #define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 1103 #define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) 1104 #define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 1105 #define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) 1106 #define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 1107 #define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) 1108 #define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 1109 #define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) 1110 #define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 1111 #define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) 1112 #define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 1113 #define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) 1114 #define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 1115 #define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) 1116 #define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 1117 #define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) 1118 #define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 1119 #define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) 1120 #define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 1121 #define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) 1122 #define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 1123 #define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) 1124 #define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 1125 #define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) 1126 1127 /* CONTROL_LPDDR2IO1_2 */ 1128 #define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 1129 #define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) 1130 #define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 1131 #define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) 1132 #define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 1133 #define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) 1134 #define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 1135 #define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) 1136 #define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 1137 #define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) 1138 #define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 1139 #define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) 1140 #define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 1141 #define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) 1142 #define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 1143 #define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) 1144 #define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 1145 #define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) 1146 1147 /* CONTROL_LPDDR2IO1_3 */ 1148 #define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 1149 #define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) 1150 #define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 1151 #define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) 1152 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 1153 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) 1154 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 1155 #define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) 1156 #define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 1157 #define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) 1158 #define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 1159 #define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) 1160 #define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 1161 #define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) 1162 #define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 1163 #define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) 1164 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 1165 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) 1166 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 1167 #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) 1168 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 1169 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) 1170 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 1171 #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) 1172 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 1173 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) 1174 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 1175 #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) 1176 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 1177 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) 1178 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 1179 #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) 1180 #define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 1181 #define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) 1182 #define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 1183 #define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) 1184 #define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 1185 #define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) 1186 #define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 1187 #define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) 1188 1189 /* CONTROL_LPDDR2IO2_0 */ 1190 #define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 1191 #define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) 1192 #define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 1193 #define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) 1194 #define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 1195 #define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) 1196 #define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 1197 #define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) 1198 #define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 1199 #define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) 1200 #define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 1201 #define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) 1202 #define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 1203 #define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) 1204 #define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 1205 #define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) 1206 #define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 1207 #define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) 1208 #define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 1209 #define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) 1210 #define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 1211 #define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) 1212 #define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 1213 #define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) 1214 1215 /* CONTROL_LPDDR2IO2_1 */ 1216 #define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 1217 #define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) 1218 #define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 1219 #define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) 1220 #define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 1221 #define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) 1222 #define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 1223 #define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) 1224 #define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 1225 #define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) 1226 #define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 1227 #define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) 1228 #define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 1229 #define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) 1230 #define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 1231 #define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) 1232 #define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 1233 #define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) 1234 #define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 1235 #define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) 1236 #define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 1237 #define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) 1238 #define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 1239 #define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) 1240 1241 /* CONTROL_LPDDR2IO2_2 */ 1242 #define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 1243 #define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) 1244 #define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 1245 #define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) 1246 #define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 1247 #define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) 1248 #define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 1249 #define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) 1250 #define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 1251 #define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) 1252 #define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 1253 #define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) 1254 #define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 1255 #define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) 1256 #define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 1257 #define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) 1258 #define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 1259 #define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) 1260 1261 /* CONTROL_LPDDR2IO2_3 */ 1262 #define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 1263 #define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) 1264 #define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 1265 #define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) 1266 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 1267 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) 1268 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 1269 #define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) 1270 #define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 1271 #define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) 1272 #define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 1273 #define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) 1274 #define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 1275 #define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) 1276 #define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 1277 #define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) 1278 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 1279 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) 1280 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 1281 #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) 1282 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 1283 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) 1284 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 1285 #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) 1286 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 1287 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) 1288 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 1289 #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) 1290 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 1291 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) 1292 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 1293 #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) 1294 #define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 1295 #define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) 1296 #define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 1297 #define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) 1298 #define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 1299 #define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) 1300 #define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 1301 #define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) 1302 1303 /* CONTROL_BUS_HOLD */ 1304 #define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 1305 #define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) 1306 #define OMAP4_MCSPI1_CS3_EN_SHIFT 30 1307 #define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) 1308 1309 /* CONTROL_C2C */ 1310 #define OMAP4_MIRROR_MODE_EN_SHIFT 31 1311 #define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) 1312 #define OMAP4_C2C_SPARE_SHIFT 24 1313 #define OMAP4_C2C_SPARE_MASK (0x7f << 24) 1314 1315 /* CORE_CONTROL_SPARE_RW */ 1316 #define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 1317 #define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) 1318 1319 /* CORE_CONTROL_SPARE_R */ 1320 #define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 1321 #define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) 1322 1323 /* CORE_CONTROL_SPARE_R_C0 */ 1324 #define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 1325 #define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) 1326 #define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 1327 #define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) 1328 #define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 1329 #define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) 1330 #define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 1331 #define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) 1332 #define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 1333 #define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) 1334 #define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 1335 #define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) 1336 #define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 1337 #define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) 1338 #define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 1339 #define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) 1340 1341 /* CONTROL_EFUSE_1 */ 1342 #define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 1343 #define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) 1344 #define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 1345 #define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) 1346 #define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 1347 #define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) 1348 #define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 1349 #define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) 1350 1351 /* CONTROL_EFUSE_2 */ 1352 #define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 1353 #define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) 1354 #define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 1355 #define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) 1356 #define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 1357 #define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) 1358 #define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 1359 #define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) 1360 #define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 1361 #define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) 1362 #define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 1363 #define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) 1364 #define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 1365 #define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) 1366 #define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 1367 #define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) 1368 #define OMAP4_LPDDR2_PTV_N1_SHIFT 23 1369 #define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) 1370 #define OMAP4_LPDDR2_PTV_N2_SHIFT 22 1371 #define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) 1372 #define OMAP4_LPDDR2_PTV_N3_SHIFT 21 1373 #define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) 1374 #define OMAP4_LPDDR2_PTV_N4_SHIFT 20 1375 #define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) 1376 #define OMAP4_LPDDR2_PTV_N5_SHIFT 19 1377 #define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) 1378 #define OMAP4_LPDDR2_PTV_P1_SHIFT 18 1379 #define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) 1380 #define OMAP4_LPDDR2_PTV_P2_SHIFT 17 1381 #define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) 1382 #define OMAP4_LPDDR2_PTV_P3_SHIFT 16 1383 #define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) 1384 #define OMAP4_LPDDR2_PTV_P4_SHIFT 15 1385 #define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) 1386 #define OMAP4_LPDDR2_PTV_P5_SHIFT 14 1387 #define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) 1388 1389 /* CONTROL_EFUSE_3 */ 1390 #define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 1391 #define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) 1392 #define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 1393 #define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) 1394 #define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 1395 #define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) 1396 #define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 1397 #define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) 1398 1399 /* CONTROL_EFUSE_4 */ 1400 #define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 1401 #define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) 1402 #define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 1403 #define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) 1404 #define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 1405 #define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) 1406 #define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 1407 #define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) 1408 1409 #endif 1410