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Searched refs:NV03_PMC_ENABLE (Results 1 – 14 of 14) sorted by relevance

/linux-3.4.99/drivers/gpu/drm/nouveau/
Dnv10_fifo.c177 nv_wr32(dev, NV03_PMC_ENABLE, in nv10_fifo_init_reset()
178 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO); in nv10_fifo_init_reset()
179 nv_wr32(dev, NV03_PMC_ENABLE, in nv10_fifo_init_reset()
180 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO); in nv10_fifo_init_reset()
Dnv40_fifo.c203 nv_wr32(dev, NV03_PMC_ENABLE, in nv40_fifo_init_reset()
204 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO); in nv40_fifo_init_reset()
205 nv_wr32(dev, NV03_PMC_ENABLE, in nv40_fifo_init_reset()
206 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO); in nv40_fifo_init_reset()
Dnv50_mc.c34 nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); in nv50_mc_init()
Dnv04_mc.c13 nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); in nv04_mc_init()
Dnv20_graph.c505 nv_wr32(dev, NV03_PMC_ENABLE, in nv20_graph_init()
506 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); in nv20_graph_init()
507 nv_wr32(dev, NV03_PMC_ENABLE, in nv20_graph_init()
508 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); in nv20_graph_init()
592 nv_wr32(dev, NV03_PMC_ENABLE, in nv30_graph_init()
593 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); in nv30_graph_init()
594 nv_wr32(dev, NV03_PMC_ENABLE, in nv30_graph_init()
595 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); in nv30_graph_init()
Dnv40_mc.c12 nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); in nv40_mc_init()
Dnv40_graph.c191 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & in nv40_graph_init()
193 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | in nv40_graph_init()
Dnv04_display.c86 uint32_t pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); in nv04_display_early_init()
89 nv_wr32(dev, NV03_PMC_ENABLE, pmc_enable | 1); in nv04_display_early_init()
Dnv04_fifo.c262 nv_wr32(dev, NV03_PMC_ENABLE, in nv04_fifo_init_reset()
263 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO); in nv04_fifo_init_reset()
264 nv_wr32(dev, NV03_PMC_ENABLE, in nv04_fifo_init_reset()
265 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO); in nv04_fifo_init_reset()
Dnv50_fifo.c101 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e); in nv50_fifo_init_reset()
102 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e); in nv50_fifo_init_reset()
Dnv04_graph.c501 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & in nv04_graph_init()
503 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | in nv04_graph_init()
Dnv10_graph.c914 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & in nv10_graph_init()
916 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | in nv10_graph_init()
Dnouveau_mem.c265 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); in nouveau_mem_reset_agp()
267 nv_wr32(dev, NV03_PMC_ENABLE, in nouveau_mem_reset_agp()
269 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | in nouveau_mem_reset_agp()
Dnouveau_reg.h134 #define NV03_PMC_ENABLE 0x00000200 macro