Searched refs:NUM_BANKS (Results 1 – 3 of 3) sorted by relevance
1106 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1116 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1126 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1136 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1146 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1156 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1166 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1176 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1186 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()1196 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()[all …]
607 # define NUM_BANKS(x) ((x) << 20) macro
70 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) macro272 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_glitch_slpm_init()290 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_glitch_slpm_restore()304 static unsigned int slpm[NUM_BANKS]; in __nmk_config_pins()966 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_clocks_enable()980 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_clocks_disable()1003 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_wakeups_suspend()1034 for (i = 0; i < NUM_BANKS; i++) { in nmk_gpio_wakeups_resume()1061 if (gpio_bank < NUM_BANKS) { in nmk_gpio_read_pull()