1 /*  *********************************************************************
2     *  SB1250 Board Support Package
3     *
4     *  SCD Constants and Macros			File: sb1250_scd.h
5     *
6     *  This module contains constants and macros useful for
7     *  manipulating the System Control and Debug module on the 1250.
8     *
9     *  SB1250 specification level:  User's manual 1/02/02
10     *
11     *********************************************************************
12     *
13     *  Copyright 2000,2001,2002,2003,2004,2005
14     *  Broadcom Corporation. All rights reserved.
15     *
16     *  This program is free software; you can redistribute it and/or
17     *  modify it under the terms of the GNU General Public License as
18     *  published by the Free Software Foundation; either version 2 of
19     *  the License, or (at your option) any later version.
20     *
21     *  This program is distributed in the hope that it will be useful,
22     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
23     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24     *  GNU General Public License for more details.
25     *
26     *  You should have received a copy of the GNU General Public License
27     *  along with this program; if not, write to the Free Software
28     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29     *  MA 02111-1307 USA
30     ********************************************************************* */
31 
32 #ifndef _SB1250_SCD_H
33 #define _SB1250_SCD_H
34 
35 #include "sb1250_defs.h"
36 
37 /*  *********************************************************************
38     *  System control/debug registers
39     ********************************************************************* */
40 
41 /*
42  * System Revision Register (Table 4-1)
43  */
44 
45 #define M_SYS_RESERVED		    _SB_MAKEMASK(8, 0)
46 
47 #define S_SYS_REVISION              _SB_MAKE64(8)
48 #define M_SYS_REVISION              _SB_MAKEMASK(8, S_SYS_REVISION)
49 #define V_SYS_REVISION(x)           _SB_MAKEVALUE(x, S_SYS_REVISION)
50 #define G_SYS_REVISION(x)           _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
51 
52 #define K_SYS_REVISION_BCM1250_PASS1	0x01
53 
54 #define K_SYS_REVISION_BCM1250_PASS2	0x03
55 #define K_SYS_REVISION_BCM1250_A1	0x03	/* Pass 2.0 WB */
56 #define K_SYS_REVISION_BCM1250_A2	0x04	/* Pass 2.0 FC */
57 #define K_SYS_REVISION_BCM1250_A3	0x05	/* Pass 2.1 FC */
58 #define K_SYS_REVISION_BCM1250_A4	0x06	/* Pass 2.1 WB */
59 #define K_SYS_REVISION_BCM1250_A6	0x07	/* OR 0x04 (A2) w/WID != 0 */
60 #define K_SYS_REVISION_BCM1250_A8	0x0b	/* A8/A10 */
61 #define K_SYS_REVISION_BCM1250_A9	0x08
62 #define K_SYS_REVISION_BCM1250_A10	K_SYS_REVISION_BCM1250_A8
63 
64 #define K_SYS_REVISION_BCM1250_PASS2_2	0x10
65 #define K_SYS_REVISION_BCM1250_B0	K_SYS_REVISION_BCM1250_B1
66 #define K_SYS_REVISION_BCM1250_B1	0x10
67 #define K_SYS_REVISION_BCM1250_B2	0x11
68 
69 #define K_SYS_REVISION_BCM1250_C0	0x20
70 #define K_SYS_REVISION_BCM1250_C1	0x21
71 #define K_SYS_REVISION_BCM1250_C2	0x22
72 #define K_SYS_REVISION_BCM1250_C3	0x23
73 
74 #if SIBYTE_HDR_FEATURE_CHIP(1250)
75 /* XXX: discourage people from using these constants.  */
76 #define K_SYS_REVISION_PASS1	    K_SYS_REVISION_BCM1250_PASS1
77 #define K_SYS_REVISION_PASS2	    K_SYS_REVISION_BCM1250_PASS2
78 #define K_SYS_REVISION_PASS2_2	    K_SYS_REVISION_BCM1250_PASS2_2
79 #define K_SYS_REVISION_PASS3	    K_SYS_REVISION_BCM1250_PASS3
80 #define K_SYS_REVISION_BCM1250_PASS3	K_SYS_REVISION_BCM1250_C0
81 #endif /* 1250 */
82 
83 #define K_SYS_REVISION_BCM112x_A1	0x20
84 #define K_SYS_REVISION_BCM112x_A2	0x21
85 #define K_SYS_REVISION_BCM112x_A3	0x22
86 #define K_SYS_REVISION_BCM112x_A4	0x23
87 #define K_SYS_REVISION_BCM112x_B0	0x30
88 
89 #define K_SYS_REVISION_BCM1480_S0	0x01
90 #define K_SYS_REVISION_BCM1480_A1	0x02
91 #define K_SYS_REVISION_BCM1480_A2	0x03
92 #define K_SYS_REVISION_BCM1480_A3	0x04
93 #define K_SYS_REVISION_BCM1480_B0	0x11
94 
95 /*Cache size - 23:20  of revision register*/
96 #define S_SYS_L2C_SIZE            _SB_MAKE64(20)
97 #define M_SYS_L2C_SIZE            _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
98 #define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
99 #define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
100 
101 #define K_SYS_L2C_SIZE_1MB	0
102 #define K_SYS_L2C_SIZE_512KB	5
103 #define K_SYS_L2C_SIZE_256KB	2
104 #define K_SYS_L2C_SIZE_128KB	1
105 
106 #define K_SYS_L2C_SIZE_BCM1250	K_SYS_L2C_SIZE_512KB
107 #define K_SYS_L2C_SIZE_BCM1125	K_SYS_L2C_SIZE_256KB
108 #define K_SYS_L2C_SIZE_BCM1122	K_SYS_L2C_SIZE_128KB
109 
110 
111 /* Number of CPU cores, bits 27:24  of revision register*/
112 #define S_SYS_NUM_CPUS            _SB_MAKE64(24)
113 #define M_SYS_NUM_CPUS            _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
114 #define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
115 #define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
116 
117 
118 /* XXX: discourage people from using these constants.  */
119 #define S_SYS_PART                  _SB_MAKE64(16)
120 #define M_SYS_PART                  _SB_MAKEMASK(16, S_SYS_PART)
121 #define V_SYS_PART(x)               _SB_MAKEVALUE(x, S_SYS_PART)
122 #define G_SYS_PART(x)               _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
123 
124 /* XXX: discourage people from using these constants.  */
125 #define K_SYS_PART_SB1250           0x1250
126 #define K_SYS_PART_BCM1120          0x1121
127 #define K_SYS_PART_BCM1125          0x1123
128 #define K_SYS_PART_BCM1125H         0x1124
129 #define K_SYS_PART_BCM1122          0x1113
130 
131 
132 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
133 #define S_SYS_SOC_TYPE              _SB_MAKE64(16)
134 #define M_SYS_SOC_TYPE              _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
135 #define V_SYS_SOC_TYPE(x)           _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
136 #define G_SYS_SOC_TYPE(x)           _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
137 
138 #define K_SYS_SOC_TYPE_BCM1250      0x0
139 #define K_SYS_SOC_TYPE_BCM1120      0x1
140 #define K_SYS_SOC_TYPE_BCM1250_ALT  0x2		/* 1250pass2 w/ 1/4 L2.  */
141 #define K_SYS_SOC_TYPE_BCM1125      0x3
142 #define K_SYS_SOC_TYPE_BCM1125H     0x4
143 #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5		/* 1250pass2 w/ 1/2 L2.  */
144 #define K_SYS_SOC_TYPE_BCM1x80      0x6
145 #define K_SYS_SOC_TYPE_BCM1x55      0x7
146 
147 /*
148  * Calculate correct SOC type given a copy of system revision register.
149  *
150  * (For the assembler version, sysrev and dest may be the same register.
151  * Also, it clobbers AT.)
152  */
153 #ifdef __ASSEMBLER__
154 #define SYS_SOC_TYPE(dest, sysrev)					\
155 	.set push ;							\
156 	.set reorder ;							\
157 	dsrl	dest, sysrev, S_SYS_SOC_TYPE ;				\
158 	andi	dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE);		\
159 	beq	dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ;		\
160 	beq	dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f	 ;		\
161 	b	992f ;							\
162 991:	li	dest, K_SYS_SOC_TYPE_BCM1250 ;				\
163 992:									\
164 	.set pop
165 #else
166 #define SYS_SOC_TYPE(sysrev)						\
167 	((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT		\
168 	  || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2)	\
169 	 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
170 #endif
171 
172 #define S_SYS_WID                   _SB_MAKE64(32)
173 #define M_SYS_WID                   _SB_MAKEMASK(32, S_SYS_WID)
174 #define V_SYS_WID(x)                _SB_MAKEVALUE(x, S_SYS_WID)
175 #define G_SYS_WID(x)                _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
176 
177 /*
178  * System Manufacturing Register
179  * Register: SCD_SYSTEM_MANUF
180  */
181 
182 #if SIBYTE_HDR_FEATURE_1250_112x
183 /* Wafer ID: bits 31:0 */
184 #define S_SYS_WAFERID1_200        _SB_MAKE64(0)
185 #define M_SYS_WAFERID1_200        _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
186 #define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
187 #define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
188 
189 #define S_SYS_BIN                 _SB_MAKE64(32)
190 #define M_SYS_BIN                 _SB_MAKEMASK(4, S_SYS_BIN)
191 #define V_SYS_BIN(x)              _SB_MAKEVALUE(x, S_SYS_BIN)
192 #define G_SYS_BIN(x)              _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
193 
194 /* Wafer ID: bits 39:36 */
195 #define S_SYS_WAFERID2_200        _SB_MAKE64(36)
196 #define M_SYS_WAFERID2_200        _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
197 #define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
198 #define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
199 
200 /* Wafer ID: bits 39:0 */
201 #define S_SYS_WAFERID_300         _SB_MAKE64(0)
202 #define M_SYS_WAFERID_300         _SB_MAKEMASK(40, S_SYS_WAFERID_300)
203 #define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
204 #define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
205 
206 #define S_SYS_XPOS                _SB_MAKE64(40)
207 #define M_SYS_XPOS                _SB_MAKEMASK(6, S_SYS_XPOS)
208 #define V_SYS_XPOS(x)             _SB_MAKEVALUE(x, S_SYS_XPOS)
209 #define G_SYS_XPOS(x)             _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
210 
211 #define S_SYS_YPOS                _SB_MAKE64(46)
212 #define M_SYS_YPOS                _SB_MAKEMASK(6, S_SYS_YPOS)
213 #define V_SYS_YPOS(x)             _SB_MAKEVALUE(x, S_SYS_YPOS)
214 #define G_SYS_YPOS(x)             _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
215 #endif
216 
217 
218 /*
219  * System Config Register (Table 4-2)
220  * Register: SCD_SYSTEM_CFG
221  */
222 
223 #if SIBYTE_HDR_FEATURE_1250_112x
224 #define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
225 #define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
226 #define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
227 #define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)
228 
229 #define S_SYS_PLL_DIV               _SB_MAKE64(7)
230 #define M_SYS_PLL_DIV               _SB_MAKEMASK(5, S_SYS_PLL_DIV)
231 #define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
232 #define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
233 
234 #define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
235 #define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
236 #define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
237 #define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
238 #define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
239 
240 #define S_SYS_BOOT_MODE             _SB_MAKE64(17)
241 #define M_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
242 #define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
243 #define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
244 #define K_SYS_BOOT_MODE_ROM32       0
245 #define K_SYS_BOOT_MODE_ROM8        1
246 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2
247 #define K_SYS_BOOT_MODE_SMBUS_BIG   3
248 
249 #define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
250 #define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
251 #define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
252 #define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
253 #define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
254 #define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
255 #define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)
256 
257 #define S_SYS_CONFIG                26
258 #define M_SYS_CONFIG                _SB_MAKEMASK(6, S_SYS_CONFIG)
259 #define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_SYS_CONFIG)
260 #define G_SYS_CONFIG(x)             _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
261 
262 /* The following bits are writeable by JTAG only. */
263 
264 #define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
265 #define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)
266 
267 #define S_SYS_CLKCOUNT              34
268 #define M_SYS_CLKCOUNT              _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
269 #define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
270 #define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
271 
272 #define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)
273 
274 #define S_SYS_PLL_IREF		    43
275 #define M_SYS_PLL_IREF		    _SB_MAKEMASK(2, S_SYS_PLL_IREF)
276 
277 #define S_SYS_PLL_VCO		    45
278 #define M_SYS_PLL_VCO		    _SB_MAKEMASK(2, S_SYS_PLL_VCO)
279 
280 #define S_SYS_PLL_VREG		    47
281 #define M_SYS_PLL_VREG		    _SB_MAKEMASK(2, S_SYS_PLL_VREG)
282 
283 #define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
284 #define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
285 #define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
286 #define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
287 #define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)
288 
289 /* End of bits writable by JTAG only. */
290 
291 #define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
292 #define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)
293 
294 #define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
295 #define M_SYS_UNICPU1               _SB_MAKEMASK1(57)
296 
297 #define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
298 #define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
299 #define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)
300 
301 #define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
302 #define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)
303 
304 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
305 #define M_SYS_SW_FLAG		    _SB_MAKEMASK1(63)
306 #endif /* 1250 PASS2 || 112x PASS1 */
307 
308 #endif
309 
310 
311 /*
312  * Mailbox Registers (Table 4-3)
313  * Registers: SCD_MBOX_CPU_x
314  */
315 
316 #define S_MBOX_INT_3                0
317 #define M_MBOX_INT_3                _SB_MAKEMASK(16, S_MBOX_INT_3)
318 #define S_MBOX_INT_2                16
319 #define M_MBOX_INT_2                _SB_MAKEMASK(16, S_MBOX_INT_2)
320 #define S_MBOX_INT_1                32
321 #define M_MBOX_INT_1                _SB_MAKEMASK(16, S_MBOX_INT_1)
322 #define S_MBOX_INT_0                48
323 #define M_MBOX_INT_0                _SB_MAKEMASK(16, S_MBOX_INT_0)
324 
325 /*
326  * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
327  * Registers: SCD_WDOG_INIT_CNT_x
328  */
329 
330 #define V_SCD_WDOG_FREQ             1000000
331 
332 #define S_SCD_WDOG_INIT             0
333 #define M_SCD_WDOG_INIT             _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
334 
335 #define S_SCD_WDOG_CNT              0
336 #define M_SCD_WDOG_CNT              _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
337 
338 #define S_SCD_WDOG_ENABLE           0
339 #define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
340 
341 #define S_SCD_WDOG_RESET_TYPE       2
342 #define M_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
343 #define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
344 #define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
345 
346 #define K_SCD_WDOG_RESET_FULL       0	/* actually, (x & 1) == 0  */
347 #define K_SCD_WDOG_RESET_SOFT       1
348 #define K_SCD_WDOG_RESET_CPU0       3
349 #define K_SCD_WDOG_RESET_CPU1       5
350 #define K_SCD_WDOG_RESET_BOTH_CPUS  7
351 
352 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
353 #if SIBYTE_HDR_FEATURE(1250, PASS3)
354 #define S_SCD_WDOG_HAS_RESET        8
355 #define M_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
356 #endif
357 
358 
359 /*
360  * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
361  */
362 
363 #define V_SCD_TIMER_FREQ            1000000
364 
365 #define S_SCD_TIMER_INIT            0
366 #define M_SCD_TIMER_INIT            _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
367 #define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
368 #define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
369 
370 #define V_SCD_TIMER_WIDTH	    23
371 #define S_SCD_TIMER_CNT             0
372 #define M_SCD_TIMER_CNT             _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
373 #define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
374 #define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
375 
376 #define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
377 #define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
378 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
379 
380 /*
381  * System Performance Counters
382  */
383 
384 #define S_SPC_CFG_SRC0            0
385 #define M_SPC_CFG_SRC0            _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
386 #define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
387 #define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
388 
389 #define S_SPC_CFG_SRC1            8
390 #define M_SPC_CFG_SRC1            _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
391 #define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
392 #define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
393 
394 #define S_SPC_CFG_SRC2            16
395 #define M_SPC_CFG_SRC2            _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
396 #define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
397 #define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
398 
399 #define S_SPC_CFG_SRC3            24
400 #define M_SPC_CFG_SRC3            _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
401 #define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
402 #define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
403 
404 #if SIBYTE_HDR_FEATURE_1250_112x
405 #define M_SPC_CFG_CLEAR		_SB_MAKEMASK1(32)
406 #define M_SPC_CFG_ENABLE	_SB_MAKEMASK1(33)
407 #endif
408 
409 
410 /*
411  * Bus Watcher
412  */
413 
414 #define S_SCD_BERR_TID            8
415 #define M_SCD_BERR_TID            _SB_MAKEMASK(10, S_SCD_BERR_TID)
416 #define V_SCD_BERR_TID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_TID)
417 #define G_SCD_BERR_TID(x)         _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
418 
419 #define S_SCD_BERR_RID            18
420 #define M_SCD_BERR_RID            _SB_MAKEMASK(4, S_SCD_BERR_RID)
421 #define V_SCD_BERR_RID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_RID)
422 #define G_SCD_BERR_RID(x)         _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
423 
424 #define S_SCD_BERR_DCODE          22
425 #define M_SCD_BERR_DCODE          _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
426 #define V_SCD_BERR_DCODE(x)       _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
427 #define G_SCD_BERR_DCODE(x)       _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
428 
429 #define M_SCD_BERR_MULTERRS       _SB_MAKEMASK1(30)
430 
431 
432 #define S_SCD_L2ECC_CORR_D        0
433 #define M_SCD_L2ECC_CORR_D        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
434 #define V_SCD_L2ECC_CORR_D(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
435 #define G_SCD_L2ECC_CORR_D(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
436 
437 #define S_SCD_L2ECC_BAD_D         8
438 #define M_SCD_L2ECC_BAD_D         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
439 #define V_SCD_L2ECC_BAD_D(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
440 #define G_SCD_L2ECC_BAD_D(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
441 
442 #define S_SCD_L2ECC_CORR_T        16
443 #define M_SCD_L2ECC_CORR_T        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
444 #define V_SCD_L2ECC_CORR_T(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
445 #define G_SCD_L2ECC_CORR_T(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
446 
447 #define S_SCD_L2ECC_BAD_T         24
448 #define M_SCD_L2ECC_BAD_T         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
449 #define V_SCD_L2ECC_BAD_T(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
450 #define G_SCD_L2ECC_BAD_T(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
451 
452 #define S_SCD_MEM_ECC_CORR        0
453 #define M_SCD_MEM_ECC_CORR        _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
454 #define V_SCD_MEM_ECC_CORR(x)     _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
455 #define G_SCD_MEM_ECC_CORR(x)     _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
456 
457 #define S_SCD_MEM_ECC_BAD         8
458 #define M_SCD_MEM_ECC_BAD         _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
459 #define V_SCD_MEM_ECC_BAD(x)      _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
460 #define G_SCD_MEM_ECC_BAD(x)      _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
461 
462 #define S_SCD_MEM_BUSERR          16
463 #define M_SCD_MEM_BUSERR          _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
464 #define V_SCD_MEM_BUSERR(x)       _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
465 #define G_SCD_MEM_BUSERR(x)       _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
466 
467 
468 /*
469  * Address Trap Registers
470  */
471 
472 #if SIBYTE_HDR_FEATURE_1250_112x
473 #define M_ATRAP_INDEX		  _SB_MAKEMASK(4, 0)
474 #define M_ATRAP_ADDRESS		  _SB_MAKEMASK(40, 0)
475 
476 #define S_ATRAP_CFG_CNT            0
477 #define M_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
478 #define V_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
479 #define G_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
480 
481 #define M_ATRAP_CFG_WRITE	   _SB_MAKEMASK1(3)
482 #define M_ATRAP_CFG_ALL	  	   _SB_MAKEMASK1(4)
483 #define M_ATRAP_CFG_INV	   	   _SB_MAKEMASK1(5)
484 #define M_ATRAP_CFG_USESRC	   _SB_MAKEMASK1(6)
485 #define M_ATRAP_CFG_SRCINV	   _SB_MAKEMASK1(7)
486 
487 #define S_ATRAP_CFG_AGENTID     8
488 #define M_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
489 #define V_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
490 #define G_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
491 
492 #define K_BUS_AGENT_CPU0	0
493 #define K_BUS_AGENT_CPU1	1
494 #define K_BUS_AGENT_IOB0	2
495 #define K_BUS_AGENT_IOB1	3
496 #define K_BUS_AGENT_SCD	4
497 #define K_BUS_AGENT_L2C	6
498 #define K_BUS_AGENT_MC	7
499 
500 #define S_ATRAP_CFG_CATTR     12
501 #define M_ATRAP_CFG_CATTR     _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
502 #define V_ATRAP_CFG_CATTR(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
503 #define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
504 
505 #define K_ATRAP_CFG_CATTR_IGNORE	0
506 #define K_ATRAP_CFG_CATTR_UNC    	1
507 #define K_ATRAP_CFG_CATTR_CACHEABLE	2
508 #define K_ATRAP_CFG_CATTR_NONCOH  	3
509 #define K_ATRAP_CFG_CATTR_COHERENT	4
510 #define K_ATRAP_CFG_CATTR_NOTUNC	5
511 #define K_ATRAP_CFG_CATTR_NOTNONCOH	6
512 #define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
513 
514 #endif	/* 1250/112x */
515 
516 /*
517  * Trace Buffer Config register
518  */
519 
520 #define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
521 #define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
522 #define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
523 #define M_SCD_TRACE_CFG_STOP            _SB_MAKEMASK1(3)
524 #define M_SCD_TRACE_CFG_FREEZE          _SB_MAKEMASK1(4)
525 #define M_SCD_TRACE_CFG_FREEZE_FULL     _SB_MAKEMASK1(5)
526 #define M_SCD_TRACE_CFG_DEBUG_FULL      _SB_MAKEMASK1(6)
527 #define M_SCD_TRACE_CFG_FULL            _SB_MAKEMASK1(7)
528 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
529 #define M_SCD_TRACE_CFG_FORCECNT        _SB_MAKEMASK1(8)
530 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
531 
532 /*
533  * This field is the same on the 1250/112x and 1480, just located in
534  * a slightly different place in the register.
535  */
536 #if SIBYTE_HDR_FEATURE_1250_112x
537 #define S_SCD_TRACE_CFG_CUR_ADDR        10
538 #else
539 #if SIBYTE_HDR_FEATURE_CHIP(1480)
540 #define S_SCD_TRACE_CFG_CUR_ADDR        24
541 #endif	/* 1480 */
542 #endif  /* 1250/112x */
543 
544 #define M_SCD_TRACE_CFG_CUR_ADDR        _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
545 #define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
546 #define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
547 
548 /*
549  * Trace Event registers
550  */
551 
552 #define S_SCD_TREVT_ADDR_MATCH          0
553 #define M_SCD_TREVT_ADDR_MATCH          _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
554 #define V_SCD_TREVT_ADDR_MATCH(x)       _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
555 #define G_SCD_TREVT_ADDR_MATCH(x)       _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
556 
557 #define M_SCD_TREVT_REQID_MATCH         _SB_MAKEMASK1(4)
558 #define M_SCD_TREVT_DATAID_MATCH        _SB_MAKEMASK1(5)
559 #define M_SCD_TREVT_RESPID_MATCH        _SB_MAKEMASK1(6)
560 #define M_SCD_TREVT_INTERRUPT           _SB_MAKEMASK1(7)
561 #define M_SCD_TREVT_DEBUG_PIN           _SB_MAKEMASK1(9)
562 #define M_SCD_TREVT_WRITE               _SB_MAKEMASK1(10)
563 #define M_SCD_TREVT_READ                _SB_MAKEMASK1(11)
564 
565 #define S_SCD_TREVT_REQID               12
566 #define M_SCD_TREVT_REQID               _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
567 #define V_SCD_TREVT_REQID(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
568 #define G_SCD_TREVT_REQID(x)            _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
569 
570 #define S_SCD_TREVT_RESPID              16
571 #define M_SCD_TREVT_RESPID              _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
572 #define V_SCD_TREVT_RESPID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
573 #define G_SCD_TREVT_RESPID(x)           _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
574 
575 #define S_SCD_TREVT_DATAID              20
576 #define M_SCD_TREVT_DATAID              _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
577 #define V_SCD_TREVT_DATAID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
578 #define G_SCD_TREVT_DATAID(x)           _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
579 
580 #define S_SCD_TREVT_COUNT               24
581 #define M_SCD_TREVT_COUNT               _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
582 #define V_SCD_TREVT_COUNT(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
583 #define G_SCD_TREVT_COUNT(x)            _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
584 
585 /*
586  * Trace Sequence registers
587  */
588 
589 #define S_SCD_TRSEQ_EVENT4              0
590 #define M_SCD_TRSEQ_EVENT4              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
591 #define V_SCD_TRSEQ_EVENT4(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
592 #define G_SCD_TRSEQ_EVENT4(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
593 
594 #define S_SCD_TRSEQ_EVENT3              4
595 #define M_SCD_TRSEQ_EVENT3              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
596 #define V_SCD_TRSEQ_EVENT3(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
597 #define G_SCD_TRSEQ_EVENT3(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
598 
599 #define S_SCD_TRSEQ_EVENT2              8
600 #define M_SCD_TRSEQ_EVENT2              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
601 #define V_SCD_TRSEQ_EVENT2(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
602 #define G_SCD_TRSEQ_EVENT2(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
603 
604 #define S_SCD_TRSEQ_EVENT1              12
605 #define M_SCD_TRSEQ_EVENT1              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
606 #define V_SCD_TRSEQ_EVENT1(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
607 #define G_SCD_TRSEQ_EVENT1(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
608 
609 #define K_SCD_TRSEQ_E0                  0
610 #define K_SCD_TRSEQ_E1                  1
611 #define K_SCD_TRSEQ_E2                  2
612 #define K_SCD_TRSEQ_E3                  3
613 #define K_SCD_TRSEQ_E0_E1               4
614 #define K_SCD_TRSEQ_E1_E2               5
615 #define K_SCD_TRSEQ_E2_E3               6
616 #define K_SCD_TRSEQ_E0_E1_E2            7
617 #define K_SCD_TRSEQ_E0_E1_E2_E3         8
618 #define K_SCD_TRSEQ_E0E1                9
619 #define K_SCD_TRSEQ_E0E1E2              10
620 #define K_SCD_TRSEQ_E0E1E2E3            11
621 #define K_SCD_TRSEQ_E0E1_E2             12
622 #define K_SCD_TRSEQ_E0E1_E2E3           13
623 #define K_SCD_TRSEQ_E0E1_E2_E3          14
624 #define K_SCD_TRSEQ_IGNORED             15
625 
626 #define K_SCD_TRSEQ_TRIGGER_ALL         (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
627                                          V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
628                                          V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
629                                          V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
630 
631 #define S_SCD_TRSEQ_FUNCTION            16
632 #define M_SCD_TRSEQ_FUNCTION            _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
633 #define V_SCD_TRSEQ_FUNCTION(x)         _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
634 #define G_SCD_TRSEQ_FUNCTION(x)         _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
635 
636 #define K_SCD_TRSEQ_FUNC_NOP            0
637 #define K_SCD_TRSEQ_FUNC_START          1
638 #define K_SCD_TRSEQ_FUNC_STOP           2
639 #define K_SCD_TRSEQ_FUNC_FREEZE         3
640 
641 #define V_SCD_TRSEQ_FUNC_NOP            V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
642 #define V_SCD_TRSEQ_FUNC_START          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
643 #define V_SCD_TRSEQ_FUNC_STOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
644 #define V_SCD_TRSEQ_FUNC_FREEZE         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
645 
646 #define M_SCD_TRSEQ_ASAMPLE             _SB_MAKEMASK1(18)
647 #define M_SCD_TRSEQ_DSAMPLE             _SB_MAKEMASK1(19)
648 #define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
649 #define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
650 #define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
651 #define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
652 #define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
653 
654 #endif
655