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Searched refs:MXC_PLL_DP_CTL (Results 1 – 2 of 2) sorted by relevance

/linux-3.4.99/arch/arm/mach-imx/
Dclock-mx51-mx53.c184 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); in clk_pll_get_rate()
249 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); in _clk_pll_set_rate()
251 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); in _clk_pll_set_rate()
275 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); in _clk_pll_enable()
280 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); in _clk_pll_enable()
284 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); in _clk_pll_enable()
305 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; in _clk_pll_disable()
306 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); in _clk_pll_disable()
Dcrm-regs-imx5.h29 #define MXC_PLL_DP_CTL 0x00 macro