1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20 #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 21 #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 22 23 #define CKIH_CLK_FREQ 26000000 24 #define CKIH_CLK_FREQ_27MHZ 27000000 25 #define CKIL_CLK_FREQ 32768 26 27 #define MXC_CCM_BASE (cpu_is_mx31() ? \ 28 MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)) 29 30 /* Register addresses */ 31 #define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) 32 #define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) 33 #define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) 34 #define MX35_CCM_PDR2 (MXC_CCM_BASE + 0x0C) 35 #define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C) 36 #define MX35_CCM_PDR3 (MXC_CCM_BASE + 0x10) 37 #define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10) 38 #define MX35_CCM_PDR4 (MXC_CCM_BASE + 0x14) 39 #define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14) 40 #define MX35_CCM_RCSR (MXC_CCM_BASE + 0x18) 41 #define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18) 42 #define MX35_CCM_MPCTL (MXC_CCM_BASE + 0x1C) 43 #define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C) 44 #define MX35_CCM_PPCTL (MXC_CCM_BASE + 0x20) 45 #define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20) 46 #define MX35_CCM_ACMR (MXC_CCM_BASE + 0x24) 47 #define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24) 48 #define MX35_CCM_COSR (MXC_CCM_BASE + 0x28) 49 #define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28) 50 #define MX35_CCM_CGR0 (MXC_CCM_BASE + 0x2C) 51 #define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C) 52 #define MX35_CCM_CGR1 (MXC_CCM_BASE + 0x30) 53 #define MXC_CCM_LDC (MXC_CCM_BASE + 0x30) 54 #define MX35_CCM_CGR2 (MXC_CCM_BASE + 0x34) 55 #define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34) 56 #define MX35_CCM_CGR3 (MXC_CCM_BASE + 0x38) 57 #define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38) 58 #define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C) 59 #define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40) 60 #define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44) 61 #define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48) 62 #define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C) 63 #define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50) 64 #define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54) 65 #define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58) 66 #define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C) 67 #define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60) 68 #define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64) 69 70 /* Register bit definitions */ 71 #define MXC_CCM_CCMR_WBEN (1 << 27) 72 #define MXC_CCM_CCMR_CSCS (1 << 25) 73 #define MXC_CCM_CCMR_PERCS (1 << 24) 74 #define MXC_CCM_CCMR_SSI1S_OFFSET 18 75 #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) 76 #define MXC_CCM_CCMR_SSI2S_OFFSET 21 77 #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) 78 #define MXC_CCM_CCMR_LPM_OFFSET 14 79 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 80 #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) 81 #define MXC_CCM_CCMR_FIRS_OFFSET 11 82 #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) 83 #define MXC_CCM_CCMR_UPE (1 << 9) 84 #define MXC_CCM_CCMR_SPE (1 << 8) 85 #define MXC_CCM_CCMR_MDS (1 << 7) 86 #define MXC_CCM_CCMR_SBYCS (1 << 4) 87 #define MXC_CCM_CCMR_MPE (1 << 3) 88 #define MXC_CCM_CCMR_PRCS_OFFSET 1 89 #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) 90 91 #define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 92 #define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) 93 #define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 94 #define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) 95 #define MXC_CCM_PDR0_PER_PODF_OFFSET 16 96 #define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) 97 #define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 98 #define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) 99 #define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 100 #define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) 101 #define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 102 #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) 103 #define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 104 #define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) 105 #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 106 #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 107 108 #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 109 #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 110 #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 111 #define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) 112 #define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 113 #define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) 114 #define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 115 #define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) 116 #define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 117 #define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) 118 #define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 119 #define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) 120 #define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 121 #define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) 122 #define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 123 #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F 124 125 /* Bit definitions for RCSR */ 126 #define MXC_CCM_RCSR_NF16B 0x80000000 127 128 /* 129 * LTR0 register offsets 130 */ 131 #define MXC_CCM_LTR0_DIV3CK_OFFSET 1 132 #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) 133 #define MXC_CCM_LTR0_DNTHR_OFFSET 16 134 #define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) 135 #define MXC_CCM_LTR0_UPTHR_OFFSET 22 136 #define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) 137 138 /* 139 * LTR1 register offsets 140 */ 141 #define MXC_CCM_LTR1_PNCTHR_OFFSET 0 142 #define MXC_CCM_LTR1_PNCTHR_MASK 0x3F 143 #define MXC_CCM_LTR1_UPCNT_OFFSET 6 144 #define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) 145 #define MXC_CCM_LTR1_DNCNT_OFFSET 14 146 #define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) 147 #define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 148 #define MXC_CCM_LTR1_LTBRSR_OFFSET 22 149 #define MXC_CCM_LTR1_LTBRSR 0x400000 150 #define MXC_CCM_LTR1_LTBRSH 0x800000 151 152 /* 153 * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 154 */ 155 #define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) 156 #define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ 157 MXC_CCM_LTR2_WSW_OFFSET((x))) 158 #define MXC_CCM_LTR2_EMAC_OFFSET 0 159 #define MXC_CCM_LTR2_EMAC_MASK 0x1FF 160 161 /* 162 * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 163 */ 164 #define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) 165 #define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ 166 MXC_CCM_LTR3_WSW_OFFSET((x))) 167 168 #define MXC_CCM_PMCR0_DFSUP1 0x80000000 169 #define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) 170 #define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) 171 #define MXC_CCM_PMCR0_DFSUP0 0x40000000 172 #define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) 173 #define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) 174 #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) 175 176 #define DVSUP_TURBO 0 177 #define DVSUP_HIGH 1 178 #define DVSUP_MEDIUM 2 179 #define DVSUP_LOW 3 180 #define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) 181 #define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) 182 #define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) 183 #define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) 184 #define MXC_CCM_PMCR0_DVSUP_OFFSET 28 185 #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) 186 #define MXC_CCM_PMCR0_UDSC 0x08000000 187 #define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) 188 #define MXC_CCM_PMCR0_UDSC_UP (1 << 27) 189 #define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) 190 191 #define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) 192 #define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) 193 #define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) 194 #define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) 195 #define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) 196 #define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) 197 #define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) 198 #define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) 199 #define MXC_CCM_PMCR0_VSCNT_OFFSET 24 200 #define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) 201 #define MXC_CCM_PMCR0_DVFEV 0x00800000 202 #define MXC_CCM_PMCR0_DVFIS 0x00400000 203 #define MXC_CCM_PMCR0_LBMI 0x00200000 204 #define MXC_CCM_PMCR0_LBFL 0x00100000 205 #define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) 206 #define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) 207 #define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) 208 #define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) 209 #define MXC_CCM_PMCR0_LBCF_OFFSET 18 210 #define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) 211 #define MXC_CCM_PMCR0_PTVIS 0x00020000 212 #define MXC_CCM_PMCR0_UPDTEN 0x00010000 213 #define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) 214 #define MXC_CCM_PMCR0_FSVAIM 0x00008000 215 #define MXC_CCM_PMCR0_FSVAI_OFFSET 13 216 #define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) 217 #define MXC_CCM_PMCR0_DPVCR 0x00001000 218 #define MXC_CCM_PMCR0_DPVV 0x00000800 219 #define MXC_CCM_PMCR0_WFIM 0x00000400 220 #define MXC_CCM_PMCR0_DRCE3 0x00000200 221 #define MXC_CCM_PMCR0_DRCE2 0x00000100 222 #define MXC_CCM_PMCR0_DRCE1 0x00000080 223 #define MXC_CCM_PMCR0_DRCE0 0x00000040 224 #define MXC_CCM_PMCR0_DCR 0x00000020 225 #define MXC_CCM_PMCR0_DVFEN 0x00000010 226 #define MXC_CCM_PMCR0_PTVAIM 0x00000008 227 #define MXC_CCM_PMCR0_PTVAI_OFFSET 1 228 #define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) 229 #define MXC_CCM_PMCR0_DPTEN 0x00000001 230 231 #define MXC_CCM_PMCR1_DVGP_OFFSET 0 232 #define MXC_CCM_PMCR1_DVGP_MASK (0xF) 233 234 #define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) 235 #define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) 236 237 #define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) 238 #define MXC_CCM_DCVR_ULV_OFFSET 22 239 #define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) 240 #define MXC_CCM_DCVR_LLV_OFFSET 12 241 #define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) 242 #define MXC_CCM_DCVR_ELV_OFFSET 2 243 244 #define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) 245 #define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 246 #define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F 247 #define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 248 249 #define MXC_CCM_COSR_CLKOSEL_MASK 0x0F 250 #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 251 #define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) 252 #define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 253 #define MXC_CCM_COSR_CLKOEN (1 << 9) 254 255 /* 256 * PMCR0 register offsets 257 */ 258 #define MXC_CCM_PMCR0_LBFL_OFFSET 20 259 #define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 260 #define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 261 262 #endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ 263