1 /************************************************************************** 2 * Copyright (c) 2007-2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 /* MID device specific descriptors */ 21 22 struct oaktrail_vbt { 23 s8 signature[4]; /*4 bytes,"$GCT" */ 24 u8 revision; 25 u8 size; 26 u8 checksum; 27 void *oaktrail_gct; 28 } __packed; 29 30 struct oaktrail_timing_info { 31 u16 pixel_clock; 32 u8 hactive_lo; 33 u8 hblank_lo; 34 u8 hblank_hi:4; 35 u8 hactive_hi:4; 36 u8 vactive_lo; 37 u8 vblank_lo; 38 u8 vblank_hi:4; 39 u8 vactive_hi:4; 40 u8 hsync_offset_lo; 41 u8 hsync_pulse_width_lo; 42 u8 vsync_pulse_width_lo:4; 43 u8 vsync_offset_lo:4; 44 u8 vsync_pulse_width_hi:2; 45 u8 vsync_offset_hi:2; 46 u8 hsync_pulse_width_hi:2; 47 u8 hsync_offset_hi:2; 48 u8 width_mm_lo; 49 u8 height_mm_lo; 50 u8 height_mm_hi:4; 51 u8 width_mm_hi:4; 52 u8 hborder; 53 u8 vborder; 54 u8 unknown0:1; 55 u8 hsync_positive:1; 56 u8 vsync_positive:1; 57 u8 separate_sync:2; 58 u8 stereo:1; 59 u8 unknown6:1; 60 u8 interlaced:1; 61 } __packed; 62 63 struct gct_r10_timing_info { 64 u16 pixel_clock; 65 u32 hactive_lo:8; 66 u32 hactive_hi:4; 67 u32 hblank_lo:8; 68 u32 hblank_hi:4; 69 u32 hsync_offset_lo:8; 70 u16 hsync_offset_hi:2; 71 u16 hsync_pulse_width_lo:8; 72 u16 hsync_pulse_width_hi:2; 73 u16 hsync_positive:1; 74 u16 rsvd_1:3; 75 u8 vactive_lo:8; 76 u16 vactive_hi:4; 77 u16 vblank_lo:8; 78 u16 vblank_hi:4; 79 u16 vsync_offset_lo:4; 80 u16 vsync_offset_hi:2; 81 u16 vsync_pulse_width_lo:4; 82 u16 vsync_pulse_width_hi:2; 83 u16 vsync_positive:1; 84 u16 rsvd_2:3; 85 } __packed; 86 87 struct oaktrail_panel_descriptor_v1 { 88 u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ 89 /* 0x61190 if MIPI */ 90 u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ 91 u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 92 u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */ 93 /* Register 0x61210 */ 94 struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */ 95 u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */ 96 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */ 97 /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */ 98 u16 Panel_MIPI_Display_Descriptor; 99 /*16 bits, Defined as follows: */ 100 /* if MIPI, 0x0000 if LVDS */ 101 /* Bit 0, Type, 2 bits, */ 102 /* 0: Type-1, */ 103 /* 1: Type-2, */ 104 /* 2: Type-3, */ 105 /* 3: Type-4 */ 106 /* Bit 2, Pixel Format, 4 bits */ 107 /* Bit0: 16bpp (not supported in LNC), */ 108 /* Bit1: 18bpp loosely packed, */ 109 /* Bit2: 18bpp packed, */ 110 /* Bit3: 24bpp */ 111 /* Bit 6, Reserved, 2 bits, 00b */ 112 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ 113 /* Bit 14, Reserved, 2 bits, 00b */ 114 } __packed; 115 116 struct oaktrail_panel_descriptor_v2 { 117 u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ 118 /* 0x61190 if MIPI */ 119 u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ 120 u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 121 u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */ 122 /* Register 0x61210 */ 123 struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */ 124 u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/ 125 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/ 126 u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */ 127 /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/ 128 u16 Panel_MIPI_Display_Descriptor; 129 /*16 bits, Defined as follows: */ 130 /* if MIPI, 0x0000 if LVDS */ 131 /* Bit 0, Type, 2 bits, */ 132 /* 0: Type-1, */ 133 /* 1: Type-2, */ 134 /* 2: Type-3, */ 135 /* 3: Type-4 */ 136 /* Bit 2, Pixel Format, 4 bits */ 137 /* Bit0: 16bpp (not supported in LNC), */ 138 /* Bit1: 18bpp loosely packed, */ 139 /* Bit2: 18bpp packed, */ 140 /* Bit3: 24bpp */ 141 /* Bit 6, Reserved, 2 bits, 00b */ 142 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ 143 /* Bit 14, Reserved, 2 bits, 00b */ 144 } __packed; 145 146 union oaktrail_panel_rx { 147 struct { 148 u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/ 149 /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */ 150 u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */ 151 /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/ 152 u16 SupportedVideoTransferMode:2; /*0: Non-burst only */ 153 /* 1: Burst and non-burst */ 154 /* 2/3: Reserved */ 155 u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/ 156 u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/ 157 u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/ 158 u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */ 159 u16 Rsvd:5;/*5 bits,00000b */ 160 } panelrx; 161 u16 panel_receiver; 162 } __packed; 163 164 struct oaktrail_gct_v1 { 165 union { /*8 bits,Defined as follows: */ 166 struct { 167 u8 PanelType:4; /*4 bits, Bit field for panels*/ 168 /* 0 - 3: 0 = LVDS, 1 = MIPI*/ 169 /*2 bits,Specifies which of the*/ 170 u8 BootPanelIndex:2; 171 /* 4 panels to use by default*/ 172 u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ 173 /* the 4 MIPI DSI receivers to use*/ 174 } PD; 175 u8 PanelDescriptor; 176 }; 177 struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/ 178 union oaktrail_panel_rx panelrx[4]; /* panel receivers*/ 179 } __packed; 180 181 struct oaktrail_gct_v2 { 182 union { /*8 bits,Defined as follows: */ 183 struct { 184 u8 PanelType:4; /*4 bits, Bit field for panels*/ 185 /* 0 - 3: 0 = LVDS, 1 = MIPI*/ 186 /*2 bits,Specifies which of the*/ 187 u8 BootPanelIndex:2; 188 /* 4 panels to use by default*/ 189 u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ 190 /* the 4 MIPI DSI receivers to use*/ 191 } PD; 192 u8 PanelDescriptor; 193 }; 194 struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/ 195 union oaktrail_panel_rx panelrx[4]; /* panel receivers*/ 196 } __packed; 197 198 struct oaktrail_gct_data { 199 u8 bpi; /* boot panel index, number of panel used during boot */ 200 u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */ 201 struct oaktrail_timing_info DTD; /* timing info for the selected panel */ 202 u32 Panel_Port_Control; 203 u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/ 204 u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 205 u32 PP_Cycle_Delay; 206 u16 Panel_Backlight_Inverter_Descriptor; 207 u16 Panel_MIPI_Display_Descriptor; 208 } __packed; 209 210 #define MODE_SETTING_IN_CRTC 0x1 211 #define MODE_SETTING_IN_ENCODER 0x2 212 #define MODE_SETTING_ON_GOING 0x3 213 #define MODE_SETTING_IN_DSR 0x4 214 #define MODE_SETTING_ENCODER_DONE 0x8 215 216 #define GCT_R10_HEADER_SIZE 16 217 #define GCT_R10_DISPLAY_DESC_SIZE 28 218 219 /* 220 * Moorestown HDMI interfaces 221 */ 222 223 struct oaktrail_hdmi_dev { 224 struct pci_dev *dev; 225 void __iomem *regs; 226 unsigned int mmio, mmio_len; 227 int dpms_mode; 228 struct hdmi_i2c_dev *i2c_dev; 229 230 /* register state */ 231 u32 saveDPLL_CTRL; 232 u32 saveDPLL_DIV_CTRL; 233 u32 saveDPLL_ADJUST; 234 u32 saveDPLL_UPDATE; 235 u32 saveDPLL_CLK_ENABLE; 236 u32 savePCH_HTOTAL_B; 237 u32 savePCH_HBLANK_B; 238 u32 savePCH_HSYNC_B; 239 u32 savePCH_VTOTAL_B; 240 u32 savePCH_VBLANK_B; 241 u32 savePCH_VSYNC_B; 242 u32 savePCH_PIPEBCONF; 243 u32 savePCH_PIPEBSRC; 244 }; 245 246 extern void oaktrail_hdmi_setup(struct drm_device *dev); 247 extern void oaktrail_hdmi_teardown(struct drm_device *dev); 248 extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev); 249 extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev); 250 extern void oaktrail_hdmi_save(struct drm_device *dev); 251 extern void oaktrail_hdmi_restore(struct drm_device *dev); 252 extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev); 253