Searched refs:MIPS_CPU_VEIC (Results 1 – 3 of 3) sorted by relevance
318 #define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ macro
232 # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
740 c->options |= MIPS_CPU_VEIC; in decode_config3()