1 /*********************************************************************
2 *
3 * Filename: nsc-ircc.h
4 * Version:
5 * Description:
6 * Status: Experimental.
7 * Author: Dag Brattli <dagb@cs.uit.no>
8 * Created at: Fri Nov 13 14:37:40 1998
9 * Modified at: Sun Jan 23 17:47:00 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
11 *
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
14 * Copyright (c) 1998 Actisys Corp., www.actisys.com
15 * All Rights Reserved
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * Neither Dag Brattli nor University of Tromsø admit liability nor
23 * provide warranty for any of this software. This material is
24 * provided "AS-IS" and at no charge.
25 *
26 ********************************************************************/
27
28 #ifndef NSC_IRCC_H
29 #define NSC_IRCC_H
30
31 #include <linux/time.h>
32
33 #include <linux/spinlock.h>
34 #include <linux/pm.h>
35 #include <linux/types.h>
36 #include <asm/io.h>
37
38 /* Features for chips (set in driver_data) */
39 #define NSC_FORCE_DONGLE_TYPE9 0x00000001
40
41 /* DMA modes needed */
42 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
43 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
44
45 /* Config registers for the '108 */
46 #define CFG_108_BAIC 0x00
47 #define CFG_108_CSRT 0x01
48 #define CFG_108_MCTL 0x02
49
50 /* Config registers for the '338 */
51 #define CFG_338_FER 0x00
52 #define CFG_338_FAR 0x01
53 #define CFG_338_PTR 0x02
54 #define CFG_338_PNP0 0x1b
55 #define CFG_338_PNP1 0x1c
56 #define CFG_338_PNP3 0x4f
57
58 /* Config registers for the '39x (in the logical device bank) */
59 #define CFG_39X_LDN 0x07 /* Logical device number (Super I/O bank) */
60 #define CFG_39X_SIOCF1 0x21 /* SuperI/O Config */
61 #define CFG_39X_ACT 0x30 /* Device activation */
62 #define CFG_39X_BASEH 0x60 /* Device base address (high bits) */
63 #define CFG_39X_BASEL 0x61 /* Device base address (low bits) */
64 #define CFG_39X_IRQNUM 0x70 /* Interrupt number & wake up enable */
65 #define CFG_39X_IRQSEL 0x71 /* Interrupt select (edge/level + polarity) */
66 #define CFG_39X_DMA0 0x74 /* DMA 0 configuration */
67 #define CFG_39X_DMA1 0x75 /* DMA 1 configuration */
68 #define CFG_39X_SPC 0xF0 /* Serial port configuration register */
69
70 /* Flags for configuration register CRF0 */
71 #define APEDCRC 0x02
72 #define ENBNKSEL 0x01
73
74 /* Set 0 */
75 #define TXD 0x00 /* Transmit data port */
76 #define RXD 0x00 /* Receive data port */
77
78 /* Register 1 */
79 #define IER 0x01 /* Interrupt Enable Register*/
80 #define IER_RXHDL_IE 0x01 /* Receiver high data level interrupt */
81 #define IER_TXLDL_IE 0x02 /* Transeiver low data level interrupt */
82 #define IER_LS_IE 0x04//* Link Status Interrupt */
83 #define IER_ETXURI 0x04 /* Tx underrun */
84 #define IER_DMA_IE 0x10 /* DMA finished interrupt */
85 #define IER_TXEMP_IE 0x20
86 #define IER_SFIF_IE 0x40 /* Frame status FIFO intr */
87 #define IER_TMR_IE 0x80 /* Timer event */
88
89 #define FCR 0x02 /* (write only) */
90 #define FCR_FIFO_EN 0x01 /* Enable FIFO's */
91 #define FCR_RXSR 0x02 /* Rx FIFO soft reset */
92 #define FCR_TXSR 0x04 /* Tx FIFO soft reset */
93 #define FCR_RXTH 0x40 /* Rx FIFO threshold (set to 16) */
94 #define FCR_TXTH 0x20 /* Tx FIFO threshold (set to 17) */
95
96 #define EIR 0x02 /* (read only) */
97 #define EIR_RXHDL_EV 0x01
98 #define EIR_TXLDL_EV 0x02
99 #define EIR_LS_EV 0x04
100 #define EIR_DMA_EV 0x10
101 #define EIR_TXEMP_EV 0x20
102 #define EIR_SFIF_EV 0x40
103 #define EIR_TMR_EV 0x80
104
105 #define LCR 0x03 /* Link control register */
106 #define LCR_WLS_8 0x03 /* 8 bits */
107
108 #define BSR 0x03 /* Bank select register */
109 #define BSR_BKSE 0x80
110 #define BANK0 LCR_WLS_8 /* Must make sure that we set 8N1 */
111 #define BANK1 0x80
112 #define BANK2 0xe0
113 #define BANK3 0xe4
114 #define BANK4 0xe8
115 #define BANK5 0xec
116 #define BANK6 0xf0
117 #define BANK7 0xf4
118
119 #define MCR 0x04 /* Mode Control Register */
120 #define MCR_MODE_MASK ~(0xd0)
121 #define MCR_UART 0x00
122 #define MCR_RESERVED 0x20
123 #define MCR_SHARP_IR 0x40
124 #define MCR_SIR 0x60
125 #define MCR_MIR 0x80
126 #define MCR_FIR 0xa0
127 #define MCR_CEIR 0xb0
128 #define MCR_IR_PLS 0x10
129 #define MCR_DMA_EN 0x04
130 #define MCR_EN_IRQ 0x08
131 #define MCR_TX_DFR 0x08
132
133 #define LSR 0x05 /* Link status register */
134 #define LSR_RXDA 0x01 /* Receiver data available */
135 #define LSR_TXRDY 0x20 /* Transmitter ready */
136 #define LSR_TXEMP 0x40 /* Transmitter empty */
137
138 #define ASCR 0x07 /* Auxiliary Status and Control Register */
139 #define ASCR_RXF_TOUT 0x01 /* Rx FIFO timeout */
140 #define ASCR_FEND_INF 0x02 /* Frame end bytes in rx FIFO */
141 #define ASCR_S_EOT 0x04 /* Set end of transmission */
142 #define ASCT_RXBSY 0x20 /* Rx busy */
143 #define ASCR_TXUR 0x40 /* Transeiver underrun */
144 #define ASCR_CTE 0x80 /* Clear timer event */
145
146 /* Bank 2 */
147 #define BGDL 0x00 /* Baud Generator Divisor Port (Low Byte) */
148 #define BGDH 0x01 /* Baud Generator Divisor Port (High Byte) */
149
150 #define ECR1 0x02 /* Extended Control Register 1 */
151 #define ECR1_EXT_SL 0x01 /* Extended Mode Select */
152 #define ECR1_DMANF 0x02 /* DMA Fairness */
153 #define ECR1_DMATH 0x04 /* DMA Threshold */
154 #define ECR1_DMASWP 0x08 /* DMA Swap */
155
156 #define EXCR2 0x04
157 #define EXCR2_TFSIZ 0x01 /* Rx FIFO size = 32 */
158 #define EXCR2_RFSIZ 0x04 /* Tx FIFO size = 32 */
159
160 #define TXFLV 0x06 /* Tx FIFO level */
161 #define RXFLV 0x07 /* Rx FIFO level */
162
163 /* Bank 3 */
164 #define MID 0x00
165
166 /* Bank 4 */
167 #define TMRL 0x00 /* Timer low byte */
168 #define TMRH 0x01 /* Timer high byte */
169 #define IRCR1 0x02 /* Infrared control register 1 */
170 #define IRCR1_TMR_EN 0x01 /* Timer enable */
171
172 #define TFRLL 0x04
173 #define TFRLH 0x05
174 #define RFRLL 0x06
175 #define RFRLH 0x07
176
177 /* Bank 5 */
178 #define IRCR2 0x04 /* Infrared control register 2 */
179 #define IRCR2_MDRS 0x04 /* MIR data rate select */
180 #define IRCR2_FEND_MD 0x20 /* */
181
182 #define FRM_ST 0x05 /* Frame status FIFO */
183 #define FRM_ST_VLD 0x80 /* Frame status FIFO data valid */
184 #define FRM_ST_ERR_MSK 0x5f
185 #define FRM_ST_LOST_FR 0x40 /* Frame lost */
186 #define FRM_ST_MAX_LEN 0x10 /* Max frame len exceeded */
187 #define FRM_ST_PHY_ERR 0x08 /* Physical layer error */
188 #define FRM_ST_BAD_CRC 0x04
189 #define FRM_ST_OVR1 0x02 /* Rx FIFO overrun */
190 #define FRM_ST_OVR2 0x01 /* Frame status FIFO overrun */
191
192 #define RFLFL 0x06
193 #define RFLFH 0x07
194
195 /* Bank 6 */
196 #define IR_CFG2 0x00
197 #define IR_CFG2_DIS_CRC 0x02
198
199 /* Bank 7 */
200 #define IRM_CR 0x07 /* Infrared module control register */
201 #define IRM_CR_IRX_MSL 0x40
202 #define IRM_CR_AF_MNT 0x80 /* Automatic format */
203
204 /* NSC chip information */
205 struct nsc_chip {
206 char *name; /* Name of chipset */
207 int cfg[3]; /* Config registers */
208 u_int8_t cid_index; /* Chip identification index reg */
209 u_int8_t cid_value; /* Chip identification expected value */
210 u_int8_t cid_mask; /* Chip identification revision mask */
211
212 /* Functions for probing and initializing the specific chip */
213 int (*probe)(struct nsc_chip *chip, chipio_t *info);
214 int (*init)(struct nsc_chip *chip, chipio_t *info);
215 };
216 typedef struct nsc_chip nsc_chip_t;
217
218 /* For storing entries in the status FIFO */
219 struct st_fifo_entry {
220 int status;
221 int len;
222 };
223
224 #define MAX_TX_WINDOW 7
225 #define MAX_RX_WINDOW 7
226
227 struct st_fifo {
228 struct st_fifo_entry entries[MAX_RX_WINDOW];
229 int pending_bytes;
230 int head;
231 int tail;
232 int len;
233 };
234
235 struct frame_cb {
236 void *start; /* Start of frame in DMA mem */
237 int len; /* Length of frame in DMA mem */
238 };
239
240 struct tx_fifo {
241 struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
242 int ptr; /* Currently being sent */
243 int len; /* Length of queue */
244 int free; /* Next free slot */
245 void *tail; /* Next free start in DMA mem */
246 };
247
248 /* Private data for each instance */
249 struct nsc_ircc_cb {
250 struct st_fifo st_fifo; /* Info about received frames */
251 struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
252
253 struct net_device *netdev; /* Yes! we are some kind of netdevice */
254
255 struct irlap_cb *irlap; /* The link layer we are binded to */
256 struct qos_info qos; /* QoS capabilities for this device */
257
258 chipio_t io; /* IrDA controller information */
259 iobuff_t tx_buff; /* Transmit buffer */
260 iobuff_t rx_buff; /* Receive buffer */
261 dma_addr_t tx_buff_dma;
262 dma_addr_t rx_buff_dma;
263
264 __u8 ier; /* Interrupt enable register */
265
266 struct timeval stamp;
267 struct timeval now;
268
269 spinlock_t lock; /* For serializing operations */
270
271 __u32 new_speed;
272 int index; /* Instance index */
273
274 struct platform_device *pldev;
275 };
276
switch_bank(int iobase,int bank)277 static inline void switch_bank(int iobase, int bank)
278 {
279 outb(bank, iobase+BSR);
280 }
281
282 #endif /* NSC_IRCC_H */
283