1 /* 2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * 20 * File: mac.h 21 * 22 * Purpose: MAC routines 23 * 24 * Author: Tevin Chen 25 * 26 * Date: May 21, 1996 27 * 28 * Revision History: 29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. 30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. 31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD 32 */ 33 34 #ifndef __MAC_H__ 35 #define __MAC_H__ 36 37 #include "ttype.h" 38 #include "device.h" 39 #include "tmacro.h" 40 41 /*--------------------- Export Definitions -------------------------*/ 42 43 #define REV_ID_VT3253_A0 0x00 44 #define REV_ID_VT3253_A1 0x01 45 #define REV_ID_VT3253_B0 0x08 46 #define REV_ID_VT3253_B1 0x09 47 48 // 49 // Registers in the MAC 50 // 51 #define MAC_REG_BISTCMD 0x04 52 #define MAC_REG_BISTSR0 0x05 53 #define MAC_REG_BISTSR1 0x06 54 #define MAC_REG_BISTSR2 0x07 55 #define MAC_REG_I2MCSR 0x08 56 #define MAC_REG_I2MTGID 0x09 57 #define MAC_REG_I2MTGAD 0x0A 58 #define MAC_REG_I2MCFG 0x0B 59 #define MAC_REG_I2MDIPT 0x0C 60 #define MAC_REG_I2MDOPT 0x0E 61 #define MAC_REG_USBSUS 0x0F 62 63 #define MAC_REG_LOCALID 0x14 64 #define MAC_REG_TESTCFG 0x15 65 #define MAC_REG_JUMPER0 0x16 66 #define MAC_REG_JUMPER1 0x17 67 #define MAC_REG_TMCTL 0x18 68 #define MAC_REG_TMDATA0 0x1C 69 #define MAC_REG_TMDATA1 0x1D 70 #define MAC_REG_TMDATA2 0x1E 71 #define MAC_REG_TMDATA3 0x1F 72 73 // MAC Parameter related 74 #define MAC_REG_LRT 0x20 // 75 #define MAC_REG_SRT 0x21 // 76 #define MAC_REG_SIFS 0x22 // 77 #define MAC_REG_DIFS 0x23 // 78 #define MAC_REG_EIFS 0x24 // 79 #define MAC_REG_SLOT 0x25 // 80 #define MAC_REG_BI 0x26 // 81 #define MAC_REG_CWMAXMIN0 0x28 // 82 #define MAC_REG_LINKOFFTOTM 0x2A 83 #define MAC_REG_SWTMOT 0x2B 84 #define MAC_REG_RTSOKCNT 0x2C 85 #define MAC_REG_RTSFAILCNT 0x2D 86 #define MAC_REG_ACKFAILCNT 0x2E 87 #define MAC_REG_FCSERRCNT 0x2F 88 // TSF Related 89 #define MAC_REG_TSFCNTR 0x30 // 90 #define MAC_REG_NEXTTBTT 0x38 // 91 #define MAC_REG_TSFOFST 0x40 // 92 #define MAC_REG_TFTCTL 0x48 // 93 // WMAC Control/Status Related 94 #define MAC_REG_ENCFG0 0x4C // 95 #define MAC_REG_ENCFG1 0x4D // 96 #define MAC_REG_ENCFG2 0x4E // 97 98 #define MAC_REG_CFG 0x50 // 99 #define MAC_REG_TEST 0x52 // 100 #define MAC_REG_HOSTCR 0x54 // 101 #define MAC_REG_MACCR 0x55 // 102 #define MAC_REG_RCR 0x56 // 103 #define MAC_REG_TCR 0x57 // 104 #define MAC_REG_IMR 0x58 // 105 #define MAC_REG_ISR 0x5C 106 #define MAC_REG_ISR1 0x5D 107 // Power Saving Related 108 #define MAC_REG_PSCFG 0x60 // 109 #define MAC_REG_PSCTL 0x61 // 110 #define MAC_REG_PSPWRSIG 0x62 // 111 #define MAC_REG_BBCR13 0x63 112 #define MAC_REG_AIDATIM 0x64 113 #define MAC_REG_PWBT 0x66 114 #define MAC_REG_WAKEOKTMR 0x68 115 #define MAC_REG_CALTMR 0x69 116 #define MAC_REG_SYNSPACCNT 0x6A 117 #define MAC_REG_WAKSYNOPT 0x6B 118 // Baseband/IF Control Group 119 #define MAC_REG_BBREGCTL 0x6C // 120 #define MAC_REG_CHANNEL 0x6D 121 #define MAC_REG_BBREGADR 0x6E 122 #define MAC_REG_BBREGDATA 0x6F 123 #define MAC_REG_IFREGCTL 0x70 // 124 #define MAC_REG_IFDATA 0x71 // 125 #define MAC_REG_ITRTMSET 0x74 // 126 #define MAC_REG_PAPEDELAY 0x77 127 #define MAC_REG_SOFTPWRCTL 0x78 // 128 #define MAC_REG_SOFTPWRCTL2 0x79 // 129 #define MAC_REG_GPIOCTL0 0x7A // 130 #define MAC_REG_GPIOCTL1 0x7B // 131 132 // MiscFF PIO related 133 #define MAC_REG_MISCFFNDEX 0xBC 134 #define MAC_REG_MISCFFCTL 0xBE 135 #define MAC_REG_MISCFFDATA 0xC0 136 137 // MAC Configuration Group 138 #define MAC_REG_PAR0 0xC4 139 #define MAC_REG_PAR4 0xC8 140 #define MAC_REG_BSSID0 0xCC 141 #define MAC_REG_BSSID4 0xD0 142 #define MAC_REG_MAR0 0xD4 143 #define MAC_REG_MAR4 0xD8 144 // MAC RSPPKT INFO Group 145 #define MAC_REG_RSPINF_B_1 0xDC 146 #define MAC_REG_RSPINF_B_2 0xE0 147 #define MAC_REG_RSPINF_B_5 0xE4 148 #define MAC_REG_RSPINF_B_11 0xE8 149 #define MAC_REG_RSPINF_A_6 0xEC 150 #define MAC_REG_RSPINF_A_9 0xEE 151 #define MAC_REG_RSPINF_A_12 0xF0 152 #define MAC_REG_RSPINF_A_18 0xF2 153 #define MAC_REG_RSPINF_A_24 0xF4 154 #define MAC_REG_RSPINF_A_36 0xF6 155 #define MAC_REG_RSPINF_A_48 0xF8 156 #define MAC_REG_RSPINF_A_54 0xFA 157 #define MAC_REG_RSPINF_A_72 0xFC 158 159 160 // 161 // Bits in the I2MCFG EEPROM register 162 // 163 #define I2MCFG_BOUNDCTL 0x80 164 #define I2MCFG_WAITCTL 0x20 165 #define I2MCFG_SCLOECTL 0x10 166 #define I2MCFG_WBUSYCTL 0x08 167 #define I2MCFG_NORETRY 0x04 168 #define I2MCFG_I2MLDSEQ 0x02 169 #define I2MCFG_I2CMFAST 0x01 170 171 // 172 // Bits in the I2MCSR EEPROM register 173 // 174 #define I2MCSR_EEMW 0x80 175 #define I2MCSR_EEMR 0x40 176 #define I2MCSR_AUTOLD 0x08 177 #define I2MCSR_NACK 0x02 178 #define I2MCSR_DONE 0x01 179 180 // 181 // Bits in the TMCTL register 182 // 183 #define TMCTL_TSUSP 0x04 184 #define TMCTL_TMD 0x02 185 #define TMCTL_TE 0x01 186 187 // 188 // Bits in the TFTCTL register 189 // 190 #define TFTCTL_HWUTSF 0x80 // 191 #define TFTCTL_TBTTSYNC 0x40 192 #define TFTCTL_HWUTSFEN 0x20 193 #define TFTCTL_TSFCNTRRD 0x10 // 194 #define TFTCTL_TBTTSYNCEN 0x08 // 195 #define TFTCTL_TSFSYNCEN 0x04 // 196 #define TFTCTL_TSFCNTRST 0x02 // 197 #define TFTCTL_TSFCNTREN 0x01 // 198 199 // 200 // Bits in the EnhanceCFG_0 register 201 // 202 #define EnCFG_BBType_a 0x00 203 #define EnCFG_BBType_b 0x01 204 #define EnCFG_BBType_g 0x02 205 #define EnCFG_BBType_MASK 0x03 206 #define EnCFG_ProtectMd 0x20 207 208 // 209 // Bits in the EnhanceCFG_1 register 210 // 211 #define EnCFG_BcnSusInd 0x01 212 #define EnCFG_BcnSusClr 0x02 213 214 // 215 // Bits in the EnhanceCFG_2 register 216 // 217 #define EnCFG_NXTBTTCFPSTR 0x01 218 #define EnCFG_BarkerPream 0x02 219 #define EnCFG_PktBurstMode 0x04 220 221 // 222 // Bits in the CFG register 223 // 224 #define CFG_TKIPOPT 0x80 225 #define CFG_RXDMAOPT 0x40 226 #define CFG_TMOT_SW 0x20 227 #define CFG_TMOT_HWLONG 0x10 228 #define CFG_TMOT_HW 0x00 229 #define CFG_CFPENDOPT 0x08 230 #define CFG_BCNSUSEN 0x04 231 #define CFG_NOTXTIMEOUT 0x02 232 #define CFG_NOBUFOPT 0x01 233 234 // 235 // Bits in the TEST register 236 // 237 #define TEST_LBEXT 0x80 // 238 #define TEST_LBINT 0x40 // 239 #define TEST_LBNONE 0x00 // 240 #define TEST_SOFTINT 0x20 // 241 #define TEST_CONTTX 0x10 // 242 #define TEST_TXPE 0x08 // 243 #define TEST_NAVDIS 0x04 // 244 #define TEST_NOCTS 0x02 // 245 #define TEST_NOACK 0x01 // 246 247 // 248 // Bits in the HOSTCR register 249 // 250 #define HOSTCR_TXONST 0x80 // 251 #define HOSTCR_RXONST 0x40 // 252 #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc 253 #define HOSTCR_AP 0x10 // Port Type 1 = AP 254 #define HOSTCR_TXON 0x08 //0000 1000 255 #define HOSTCR_RXON 0x04 //0000 0100 256 #define HOSTCR_MACEN 0x02 //0000 0010 257 #define HOSTCR_SOFTRST 0x01 //0000 0001 258 259 // 260 // Bits in the MACCR register 261 // 262 #define MACCR_SYNCFLUSHOK 0x04 // 263 #define MACCR_SYNCFLUSH 0x02 // 264 #define MACCR_CLRNAV 0x01 // 265 266 // 267 // Bits in the RCR register 268 // 269 #define RCR_SSID 0x80 270 #define RCR_RXALLTYPE 0x40 // 271 #define RCR_UNICAST 0x20 // 272 #define RCR_BROADCAST 0x10 // 273 #define RCR_MULTICAST 0x08 // 274 #define RCR_WPAERR 0x04 // 275 #define RCR_ERRCRC 0x02 // 276 #define RCR_BSSID 0x01 // 277 278 // 279 // Bits in the TCR register 280 // 281 #define TCR_SYNCDCFOPT 0x02 // 282 #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable 283 284 285 //ISR1 286 #define ISR_GPIO3 0x40 287 #define ISR_RXNOBUF 0x08 288 #define ISR_MIBNEARFULL 0x04 289 #define ISR_SOFTINT 0x02 290 #define ISR_FETALERR 0x01 291 292 #define LEDSTS_STS 0x06 293 #define LEDSTS_TMLEN 0x78 294 #define LEDSTS_OFF 0x00 295 #define LEDSTS_ON 0x02 296 #define LEDSTS_SLOW 0x04 297 #define LEDSTS_INTER 0x06 298 299 //ISR0 300 #define ISR_WATCHDOG 0x80 301 #define ISR_SOFTTIMER 0x40 302 #define ISR_GPIO0 0x20 303 #define ISR_TBTT 0x10 304 #define ISR_RXDMA0 0x08 305 #define ISR_BNTX 0x04 306 #define ISR_ACTX 0x01 307 308 // 309 // Bits in the PSCFG register 310 // 311 #define PSCFG_PHILIPMD 0x40 // 312 #define PSCFG_WAKECALEN 0x20 // 313 #define PSCFG_WAKETMREN 0x10 // 314 #define PSCFG_BBPSPROG 0x08 // 315 #define PSCFG_WAKESYN 0x04 // 316 #define PSCFG_SLEEPSYN 0x02 // 317 #define PSCFG_AUTOSLEEP 0x01 // 318 319 // 320 // Bits in the PSCTL register 321 // 322 #define PSCTL_WAKEDONE 0x20 // 323 #define PSCTL_PS 0x10 // 324 #define PSCTL_GO2DOZE 0x08 // 325 #define PSCTL_LNBCN 0x04 // 326 #define PSCTL_ALBCN 0x02 // 327 #define PSCTL_PSEN 0x01 // 328 329 // 330 // Bits in the PSPWSIG register 331 // 332 #define PSSIG_WPE3 0x80 // 333 #define PSSIG_WPE2 0x40 // 334 #define PSSIG_WPE1 0x20 // 335 #define PSSIG_WRADIOPE 0x10 // 336 #define PSSIG_SPE3 0x08 // 337 #define PSSIG_SPE2 0x04 // 338 #define PSSIG_SPE1 0x02 // 339 #define PSSIG_SRADIOPE 0x01 // 340 341 // 342 // Bits in the BBREGCTL register 343 // 344 #define BBREGCTL_DONE 0x04 // 345 #define BBREGCTL_REGR 0x02 // 346 #define BBREGCTL_REGW 0x01 // 347 348 // 349 // Bits in the IFREGCTL register 350 // 351 #define IFREGCTL_DONE 0x04 // 352 #define IFREGCTL_IFRF 0x02 // 353 #define IFREGCTL_REGW 0x01 // 354 355 // 356 // Bits in the SOFTPWRCTL register 357 // 358 #define SOFTPWRCTL_RFLEOPT 0x08 // 359 #define SOFTPWRCTL_TXPEINV 0x02 // 360 #define SOFTPWRCTL_SWPECTI 0x01 // 361 #define SOFTPWRCTL_SWPAPE 0x20 // 362 #define SOFTPWRCTL_SWCALEN 0x10 // 363 #define SOFTPWRCTL_SWRADIO_PE 0x08 // 364 #define SOFTPWRCTL_SWPE2 0x04 // 365 #define SOFTPWRCTL_SWPE1 0x02 // 366 #define SOFTPWRCTL_SWPE3 0x01 // 367 368 // 369 // Bits in the GPIOCTL1 register 370 // 371 #define GPIO3_MD 0x20 // 372 #define GPIO3_DATA 0x40 // 373 #define GPIO3_INTMD 0x80 // 374 375 // 376 // Bits in the MISCFFCTL register 377 // 378 #define MISCFFCTL_WRITE 0x0001 // 379 380 381 // Loopback mode 382 #define MAC_LB_EXT 0x02 // 383 #define MAC_LB_INTERNAL 0x01 // 384 #define MAC_LB_NONE 0x00 // 385 386 // Ethernet address filter type 387 #define PKT_TYPE_NONE 0x00 // turn off receiver 388 #define PKT_TYPE_ALL_MULTICAST 0x80 389 #define PKT_TYPE_PROMISCUOUS 0x40 390 #define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted 391 #define PKT_TYPE_BROADCAST 0x10 392 #define PKT_TYPE_MULTICAST 0x08 393 #define PKT_TYPE_ERROR_WPA 0x04 394 #define PKT_TYPE_ERROR_CRC 0x02 395 #define PKT_TYPE_BSSID 0x01 396 397 #define Default_BI 0x200 398 399 // MiscFIFO Offset 400 #define MISCFIFO_KEYETRY0 32 401 #define MISCFIFO_KEYENTRYSIZE 22 402 403 // max time out delay time 404 #define W_MAX_TIMEOUT 0xFFF0U // 405 406 // wait time within loop 407 #define CB_DELAY_LOOP_WAIT 10 // 10ms 408 409 #define MAC_REVISION_A0 0x00 410 #define MAC_REVISION_A1 0x01 411 412 413 /*--------------------- Export Types ------------------------------*/ 414 415 /*--------------------- Export Macros ------------------------------*/ 416 417 /*--------------------- Export Classes ----------------------------*/ 418 419 /*--------------------- Export Variables --------------------------*/ 420 421 /*--------------------- Export Functions --------------------------*/ 422 423 void MACvSetMultiAddrByHash(PSDevice pDevice, BYTE byHashIdx); 424 void MACvWriteMultiAddr(PSDevice pDevice, unsigned int uByteIdx, BYTE byData); 425 void MACbShutdown(PSDevice pDevice); 426 void MACvSetBBType(PSDevice pDevice, BYTE byType); 427 void MACvSetMISCFifo(PSDevice pDevice, WORD wOffset, DWORD dwData); 428 void MACvDisableKeyEntry(PSDevice pDevice, unsigned int uEntryIdx); 429 void MACvSetKeyEntry(PSDevice pDevice, WORD wKeyCtl, unsigned int uEntryIdx, 430 unsigned int uKeyIdx, PBYTE pbyAddr, PDWORD pdwKey); 431 432 void MACvRegBitsOff(PSDevice pDevice, BYTE byRegOfs, BYTE byBits); 433 void MACvRegBitsOn(PSDevice pDevice, BYTE byRegOfs, BYTE byBits); 434 void MACvWriteWord(PSDevice pDevice, BYTE byRegOfs, WORD wData); 435 436 void MACvWriteBSSIDAddress(PSDevice pDevice, PBYTE pbyEtherAddr); 437 void MACvEnableProtectMD(PSDevice pDevice); 438 void MACvDisableProtectMD(PSDevice pDevice); 439 void MACvEnableBarkerPreambleMd(PSDevice pDevice); 440 void MACvDisableBarkerPreambleMd(PSDevice pDevice); 441 void MACvWriteBeaconInterval(PSDevice pDevice, WORD wInterval); 442 443 #endif /* __MAC_H__ */ 444