1 /*
2  * QLogic iSCSI HBA Driver
3  * Copyright (c)  2003-2010 QLogic Corporation
4  *
5  * See LICENSE.qla4xxx for copyright and licensing details.
6  */
7 
8 #ifndef _QLA4X_FW_H
9 #define _QLA4X_FW_H
10 
11 
12 #define MAX_PRST_DEV_DB_ENTRIES		64
13 #define MIN_DISC_DEV_DB_ENTRY		MAX_PRST_DEV_DB_ENTRIES
14 #define MAX_DEV_DB_ENTRIES		512
15 #define MAX_DEV_DB_ENTRIES_40XX		256
16 
17 /*************************************************************************
18  *
19  *		ISP 4010 I/O Register Set Structure and Definitions
20  *
21  *************************************************************************/
22 
23 struct port_ctrl_stat_regs {
24 	__le32 ext_hw_conf;	/* 0x50  R/W */
25 	__le32 rsrvd0;		/* 0x54 */
26 	__le32 port_ctrl;	/* 0x58 */
27 	__le32 port_status;	/* 0x5c */
28 	__le32 rsrvd1[32];	/* 0x60-0xdf */
29 	__le32 gp_out;		/* 0xe0 */
30 	__le32 gp_in;		/* 0xe4 */
31 	__le32 rsrvd2[5];	/* 0xe8-0xfb */
32 	__le32 port_err_status; /* 0xfc */
33 };
34 
35 struct host_mem_cfg_regs {
36 	__le32 rsrvd0[12];	/* 0x50-0x79 */
37 	__le32 req_q_out;	/* 0x80 */
38 	__le32 rsrvd1[31];	/* 0x84-0xFF */
39 };
40 
41 /*
42  * ISP 82xx I/O Register Set structure definitions.
43  */
44 struct device_reg_82xx {
45 	__le32 req_q_out;	/* 0x0000 (R): Request Queue out-Pointer. */
46 	__le32 reserve1[63];	/* Request Queue out-Pointer. (64 * 4) */
47 	__le32 rsp_q_in;	/* 0x0100 (R/W): Response Queue In-Pointer. */
48 	__le32 reserve2[63];	/* Response Queue In-Pointer. */
49 	__le32 rsp_q_out;	/* 0x0200 (R/W): Response Queue Out-Pointer. */
50 	__le32 reserve3[63];	/* Response Queue Out-Pointer. */
51 
52 	__le32 mailbox_in[8];	/* 0x0300 (R/W): Mail box In registers */
53 	__le32 reserve4[24];
54 	__le32 hint;		/* 0x0380 (R/W): Host interrupt register */
55 #define HINT_MBX_INT_PENDING	BIT_0
56 	__le32 reserve5[31];
57 	__le32 mailbox_out[8];	/* 0x0400 (R): Mail box Out registers */
58 	__le32 reserve6[56];
59 
60 	__le32 host_status;	/* Offset 0x500 (R): host status */
61 #define HSRX_RISC_MB_INT	BIT_0  /* RISC to Host Mailbox interrupt */
62 #define HSRX_RISC_IOCB_INT	BIT_1  /* RISC to Host IOCB interrupt */
63 
64 	__le32 host_int;	/* Offset 0x0504 (R/W): Interrupt status. */
65 #define ISRX_82XX_RISC_INT	BIT_0 /* RISC interrupt. */
66 };
67 
68 /*  remote register set (access via PCI memory read/write) */
69 struct isp_reg {
70 #define MBOX_REG_COUNT 8
71 	__le32 mailbox[MBOX_REG_COUNT];
72 
73 	__le32 flash_address;	/* 0x20 */
74 	__le32 flash_data;
75 	__le32 ctrl_status;
76 
77 	union {
78 		struct {
79 			__le32 nvram;
80 			__le32 reserved1[2]; /* 0x30 */
81 		} __attribute__ ((packed)) isp4010;
82 		struct {
83 			__le32 intr_mask;
84 			__le32 nvram; /* 0x30 */
85 			__le32 semaphore;
86 		} __attribute__ ((packed)) isp4022;
87 	} u1;
88 
89 	__le32 req_q_in;    /* SCSI Request Queue Producer Index */
90 	__le32 rsp_q_out;   /* SCSI Completion Queue Consumer Index */
91 
92 	__le32 reserved2[4];	/* 0x40 */
93 
94 	union {
95 		struct {
96 			__le32 ext_hw_conf; /* 0x50 */
97 			__le32 flow_ctrl;
98 			__le32 port_ctrl;
99 			__le32 port_status;
100 
101 			__le32 reserved3[8]; /* 0x60 */
102 
103 			__le32 req_q_out; /* 0x80 */
104 
105 			__le32 reserved4[23]; /* 0x84 */
106 
107 			__le32 gp_out; /* 0xe0 */
108 			__le32 gp_in;
109 
110 			__le32 reserved5[5];
111 
112 			__le32 port_err_status; /* 0xfc */
113 		} __attribute__ ((packed)) isp4010;
114 		struct {
115 			union {
116 				struct port_ctrl_stat_regs p0;
117 				struct host_mem_cfg_regs p1;
118 			};
119 		} __attribute__ ((packed)) isp4022;
120 	} u2;
121 };				/* 256 x100 */
122 
123 
124 /* Semaphore Defines for 4010 */
125 #define QL4010_DRVR_SEM_BITS	0x00000030
126 #define QL4010_GPIO_SEM_BITS	0x000000c0
127 #define QL4010_SDRAM_SEM_BITS	0x00000300
128 #define QL4010_PHY_SEM_BITS	0x00000c00
129 #define QL4010_NVRAM_SEM_BITS	0x00003000
130 #define QL4010_FLASH_SEM_BITS	0x0000c000
131 
132 #define QL4010_DRVR_SEM_MASK	0x00300000
133 #define QL4010_GPIO_SEM_MASK	0x00c00000
134 #define QL4010_SDRAM_SEM_MASK	0x03000000
135 #define QL4010_PHY_SEM_MASK	0x0c000000
136 #define QL4010_NVRAM_SEM_MASK	0x30000000
137 #define QL4010_FLASH_SEM_MASK	0xc0000000
138 
139 /* Semaphore Defines for 4022 */
140 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
141 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
142 
143 
144 #define QL4022_DRVR_SEM_MASK	(QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
145 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
146 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
147 #define QL4022_NVRAM_SEM_MASK	(QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
148 #define QL4022_FLASH_SEM_MASK	(QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
149 
150 /* nvram address for 4032 */
151 #define NVRAM_PORT0_BOOT_MODE		0x03b1
152 #define NVRAM_PORT0_BOOT_PRI_TGT	0x03b2
153 #define NVRAM_PORT0_BOOT_SEC_TGT	0x03bb
154 #define NVRAM_PORT1_BOOT_MODE		0x07b1
155 #define NVRAM_PORT1_BOOT_PRI_TGT	0x07b2
156 #define NVRAM_PORT1_BOOT_SEC_TGT	0x07bb
157 
158 
159 /* Page # defines for 4022 */
160 #define PORT_CTRL_STAT_PAGE			0	/* 4022 */
161 #define HOST_MEM_CFG_PAGE			1	/* 4022 */
162 #define LOCAL_RAM_CFG_PAGE			2	/* 4022 */
163 #define PROT_STAT_PAGE				3	/* 4022 */
164 
165 /* Register Mask - sets corresponding mask bits in the upper word */
set_rmask(uint32_t val)166 static inline uint32_t set_rmask(uint32_t val)
167 {
168 	return (val & 0xffff) | (val << 16);
169 }
170 
171 
clr_rmask(uint32_t val)172 static inline uint32_t clr_rmask(uint32_t val)
173 {
174 	return 0 | (val << 16);
175 }
176 
177 /*  ctrl_status definitions */
178 #define CSR_SCSI_PAGE_SELECT			0x00000003
179 #define CSR_SCSI_INTR_ENABLE			0x00000004	/* 4010 */
180 #define CSR_SCSI_RESET_INTR			0x00000008
181 #define CSR_SCSI_COMPLETION_INTR		0x00000010
182 #define CSR_SCSI_PROCESSOR_INTR			0x00000020
183 #define CSR_INTR_RISC				0x00000040
184 #define CSR_BOOT_ENABLE				0x00000080
185 #define CSR_NET_PAGE_SELECT			0x00000300	/* 4010 */
186 #define CSR_FUNC_NUM				0x00000700	/* 4022 */
187 #define CSR_NET_RESET_INTR			0x00000800	/* 4010 */
188 #define CSR_FORCE_SOFT_RESET			0x00002000	/* 4022 */
189 #define CSR_FATAL_ERROR				0x00004000
190 #define CSR_SOFT_RESET				0x00008000
191 #define ISP_CONTROL_FN_MASK			CSR_FUNC_NUM
192 #define ISP_CONTROL_FN0_SCSI			0x0500
193 #define ISP_CONTROL_FN1_SCSI			0x0700
194 
195 #define INTR_PENDING				(CSR_SCSI_COMPLETION_INTR |\
196 						 CSR_SCSI_PROCESSOR_INTR |\
197 						 CSR_SCSI_RESET_INTR)
198 
199 /* ISP InterruptMask definitions */
200 #define IMR_SCSI_INTR_ENABLE			0x00000004	/* 4022 */
201 
202 /* ISP 4022 nvram definitions */
203 #define NVR_WRITE_ENABLE			0x00000010	/* 4022 */
204 
205 #define QL4010_NVRAM_SIZE			0x200
206 #define QL40X2_NVRAM_SIZE			0x800
207 
208 /*  ISP port_status definitions */
209 
210 /*  ISP Semaphore definitions */
211 
212 /*  ISP General Purpose Output definitions */
213 #define GPOR_TOPCAT_RESET			0x00000004
214 
215 /*  shadow registers (DMA'd from HA to system memory.  read only) */
216 struct shadow_regs {
217 	/* SCSI Request Queue Consumer Index */
218 	__le32 req_q_out;	/*  0 x0   R */
219 
220 	/* SCSI Completion Queue Producer Index */
221 	__le32 rsp_q_in;	/*  4 x4   R */
222 };		  /*  8 x8 */
223 
224 
225 /*  External hardware configuration register */
226 union external_hw_config_reg {
227 	struct {
228 		/* FIXME: Do we even need this?	 All values are
229 		 * referred to by 16 bit quantities.  Platform and
230 		 * endianess issues. */
231 		__le32 bReserved0:1;
232 		__le32 bSDRAMProtectionMethod:2;
233 		__le32 bSDRAMBanks:1;
234 		__le32 bSDRAMChipWidth:1;
235 		__le32 bSDRAMChipSize:2;
236 		__le32 bParityDisable:1;
237 		__le32 bExternalMemoryType:1;
238 		__le32 bFlashBIOSWriteEnable:1;
239 		__le32 bFlashUpperBankSelect:1;
240 		__le32 bWriteBurst:2;
241 		__le32 bReserved1:3;
242 		__le32 bMask:16;
243 	};
244 	uint32_t Asuint32_t;
245 };
246 
247 /* 82XX Support  start */
248 /* 82xx Default FLT Addresses */
249 #define FA_FLASH_LAYOUT_ADDR_82		0xFC400
250 #define FA_FLASH_DESCR_ADDR_82		0xFC000
251 #define FA_BOOT_LOAD_ADDR_82		0x04000
252 #define FA_BOOT_CODE_ADDR_82		0x20000
253 #define FA_RISC_CODE_ADDR_82		0x40000
254 #define FA_GOLD_RISC_CODE_ADDR_82	0x80000
255 #define FA_FLASH_ISCSI_CHAP		0x540000
256 #define FA_FLASH_CHAP_SIZE		0xC0000
257 
258 /* Flash Description Table */
259 struct qla_fdt_layout {
260 	uint8_t sig[4];
261 	uint16_t version;
262 	uint16_t len;
263 	uint16_t checksum;
264 	uint8_t unused1[2];
265 	uint8_t model[16];
266 	uint16_t man_id;
267 	uint16_t id;
268 	uint8_t flags;
269 	uint8_t erase_cmd;
270 	uint8_t alt_erase_cmd;
271 	uint8_t wrt_enable_cmd;
272 	uint8_t wrt_enable_bits;
273 	uint8_t wrt_sts_reg_cmd;
274 	uint8_t unprotect_sec_cmd;
275 	uint8_t read_man_id_cmd;
276 	uint32_t block_size;
277 	uint32_t alt_block_size;
278 	uint32_t flash_size;
279 	uint32_t wrt_enable_data;
280 	uint8_t read_id_addr_len;
281 	uint8_t wrt_disable_bits;
282 	uint8_t read_dev_id_len;
283 	uint8_t chip_erase_cmd;
284 	uint16_t read_timeout;
285 	uint8_t protect_sec_cmd;
286 	uint8_t unused2[65];
287 };
288 
289 /* Flash Layout Table */
290 
291 struct qla_flt_location {
292 	uint8_t sig[4];
293 	uint16_t start_lo;
294 	uint16_t start_hi;
295 	uint8_t version;
296 	uint8_t unused[5];
297 	uint16_t checksum;
298 };
299 
300 struct qla_flt_header {
301 	uint16_t version;
302 	uint16_t length;
303 	uint16_t checksum;
304 	uint16_t unused;
305 };
306 
307 /* 82xx FLT Regions */
308 #define FLT_REG_FDT		0x1a
309 #define FLT_REG_FLT		0x1c
310 #define FLT_REG_BOOTLOAD_82	0x72
311 #define FLT_REG_FW_82		0x74
312 #define FLT_REG_FW_82_1		0x97
313 #define FLT_REG_GOLD_FW_82	0x75
314 #define FLT_REG_BOOT_CODE_82	0x78
315 #define FLT_REG_ISCSI_PARAM	0x65
316 #define FLT_REG_ISCSI_CHAP	0x63
317 
318 struct qla_flt_region {
319 	uint32_t code;
320 	uint32_t size;
321 	uint32_t start;
322 	uint32_t end;
323 };
324 
325 /*************************************************************************
326  *
327  *		Mailbox Commands Structures and Definitions
328  *
329  *************************************************************************/
330 
331 /*  Mailbox command definitions */
332 #define MBOX_CMD_ABOUT_FW			0x0009
333 #define MBOX_CMD_PING				0x000B
334 #define PING_IPV6_PROTOCOL_ENABLE		0x1
335 #define PING_IPV6_LINKLOCAL_ADDR		0x4
336 #define PING_IPV6_ADDR0				0x8
337 #define PING_IPV6_ADDR1				0xC
338 #define MBOX_CMD_ENABLE_INTRS			0x0010
339 #define INTR_DISABLE				0
340 #define INTR_ENABLE				1
341 #define MBOX_CMD_STOP_FW			0x0014
342 #define MBOX_CMD_ABORT_TASK			0x0015
343 #define MBOX_CMD_LUN_RESET			0x0016
344 #define MBOX_CMD_TARGET_WARM_RESET		0x0017
345 #define MBOX_CMD_GET_MANAGEMENT_DATA		0x001E
346 #define MBOX_CMD_GET_FW_STATUS			0x001F
347 #define MBOX_CMD_SET_ISNS_SERVICE		0x0021
348 #define ISNS_DISABLE				0
349 #define ISNS_ENABLE				1
350 #define MBOX_CMD_COPY_FLASH			0x0024
351 #define MBOX_CMD_WRITE_FLASH			0x0025
352 #define MBOX_CMD_READ_FLASH			0x0026
353 #define MBOX_CMD_CLEAR_DATABASE_ENTRY		0x0031
354 #define MBOX_CMD_CONN_OPEN			0x0074
355 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT		0x0056
356 #define LOGOUT_OPTION_CLOSE_SESSION		0x0002
357 #define LOGOUT_OPTION_RELOGIN			0x0004
358 #define LOGOUT_OPTION_FREE_DDB			0x0008
359 #define MBOX_CMD_EXECUTE_IOCB_A64		0x005A
360 #define MBOX_CMD_INITIALIZE_FIRMWARE		0x0060
361 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK		0x0061
362 #define MBOX_CMD_REQUEST_DATABASE_ENTRY		0x0062
363 #define MBOX_CMD_SET_DATABASE_ENTRY		0x0063
364 #define MBOX_CMD_GET_DATABASE_ENTRY		0x0064
365 #define DDB_DS_UNASSIGNED			0x00
366 #define DDB_DS_NO_CONNECTION_ACTIVE		0x01
367 #define DDB_DS_DISCOVERY			0x02
368 #define DDB_DS_SESSION_ACTIVE			0x04
369 #define DDB_DS_SESSION_FAILED			0x06
370 #define DDB_DS_LOGIN_IN_PROCESS			0x07
371 #define MBOX_CMD_GET_FW_STATE			0x0069
372 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
373 #define MBOX_CMD_GET_SYS_INFO			0x0078
374 #define MBOX_CMD_GET_NVRAM			0x0078	/* For 40xx */
375 #define MBOX_CMD_SET_NVRAM			0x0079	/* For 40xx */
376 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS	0x0087
377 #define MBOX_CMD_SET_ACB			0x0088
378 #define MBOX_CMD_GET_ACB			0x0089
379 #define MBOX_CMD_DISABLE_ACB			0x008A
380 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE	0x008B
381 #define MBOX_CMD_GET_IPV6_DEST_CACHE		0x008C
382 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST	0x008D
383 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST	0x008E
384 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE	0x0090
385 #define MBOX_CMD_GET_IP_ADDR_STATE		0x0091
386 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL		0x0092
387 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR	0x0093
388 
389 /* Mailbox 1 */
390 #define FW_STATE_READY				0x0000
391 #define FW_STATE_CONFIG_WAIT			0x0001
392 #define FW_STATE_WAIT_AUTOCONNECT		0x0002
393 #define FW_STATE_ERROR				0x0004
394 #define FW_STATE_CONFIGURING_IP			0x0008
395 
396 /* Mailbox 3 */
397 #define FW_ADDSTATE_OPTICAL_MEDIA		0x0001
398 #define FW_ADDSTATE_DHCPv4_ENABLED		0x0002
399 #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED	0x0004
400 #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED	0x0008
401 #define FW_ADDSTATE_LINK_UP			0x0010
402 #define FW_ADDSTATE_ISNS_SVC_ENABLED		0x0020
403 #define FW_ADDSTATE_LINK_SPEED_10MBPS		0x0100
404 #define FW_ADDSTATE_LINK_SPEED_100MBPS		0x0200
405 #define FW_ADDSTATE_LINK_SPEED_1GBPS		0x0400
406 #define FW_ADDSTATE_LINK_SPEED_10GBPS		0x0800
407 
408 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS	0x006B
409 #define IPV6_DEFAULT_DDB_ENTRY			0x0001
410 
411 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN		0x0074
412 #define MBOX_CMD_GET_CRASH_RECORD		0x0076	/* 4010 only */
413 #define MBOX_CMD_GET_CONN_EVENT_LOG		0x0077
414 
415 /*  Mailbox status definitions */
416 #define MBOX_COMPLETION_STATUS			4
417 #define MBOX_STS_BUSY				0x0007
418 #define MBOX_STS_INTERMEDIATE_COMPLETION	0x1000
419 #define MBOX_STS_COMMAND_COMPLETE		0x4000
420 #define MBOX_STS_COMMAND_ERROR			0x4005
421 
422 #define MBOX_ASYNC_EVENT_STATUS			8
423 #define MBOX_ASTS_SYSTEM_ERROR			0x8002
424 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR	0x8003
425 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR	0x8004
426 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM	0x8005
427 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED	0x8006
428 #define MBOX_ASTS_LINK_UP			0x8010
429 #define MBOX_ASTS_LINK_DOWN			0x8011
430 #define MBOX_ASTS_DATABASE_CHANGED		0x8014
431 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED	0x8015
432 #define MBOX_ASTS_SELF_TEST_FAILED		0x8016
433 #define MBOX_ASTS_LOGIN_FAILED			0x8017
434 #define MBOX_ASTS_DNS				0x8018
435 #define MBOX_ASTS_HEARTBEAT			0x8019
436 #define MBOX_ASTS_NVRAM_INVALID			0x801A
437 #define MBOX_ASTS_MAC_ADDRESS_CHANGED		0x801B
438 #define MBOX_ASTS_IP_ADDRESS_CHANGED		0x801C
439 #define MBOX_ASTS_DHCP_LEASE_EXPIRED		0x801D
440 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED		0x801F
441 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
442 #define MBOX_ASTS_DUPLICATE_IP			0x8025
443 #define MBOX_ASTS_ARP_COMPLETE			0x8026
444 #define MBOX_ASTS_SUBNET_STATE_CHANGE		0x8027
445 #define MBOX_ASTS_RESPONSE_QUEUE_FULL		0x8028
446 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED		0x8029
447 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED		0x802B
448 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED	0x802C
449 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED	0x802D
450 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD		0x802E
451 #define MBOX_ASTS_TXSCVR_INSERTED		0x8130
452 #define MBOX_ASTS_TXSCVR_REMOVED		0x8131
453 
454 #define ISNS_EVENT_DATA_RECEIVED		0x0000
455 #define ISNS_EVENT_CONNECTION_OPENED		0x0001
456 #define ISNS_EVENT_CONNECTION_FAILED		0x0002
457 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR	0x8022
458 #define MBOX_ASTS_SUBNET_STATE_CHANGE		0x8027
459 
460 /* ACB State Defines */
461 #define ACB_STATE_UNCONFIGURED	0x00
462 #define ACB_STATE_INVALID	0x01
463 #define ACB_STATE_ACQUIRING	0x02
464 #define ACB_STATE_TENTATIVE	0x03
465 #define ACB_STATE_DEPRICATED	0x04
466 #define ACB_STATE_VALID		0x05
467 #define ACB_STATE_DISABLING	0x06
468 
469 /* FLASH offsets */
470 #define FLASH_SEGMENT_IFCB	0x04000000
471 
472 #define FLASH_OPT_RMW_HOLD	0
473 #define FLASH_OPT_RMW_INIT	1
474 #define FLASH_OPT_COMMIT	2
475 #define FLASH_OPT_RMW_COMMIT	3
476 
477 /*************************************************************************/
478 
479 /* Host Adapter Initialization Control Block (from host) */
480 struct addr_ctrl_blk {
481 	uint8_t version;	/* 00 */
482 #define  IFCB_VER_MIN			0x01
483 #define  IFCB_VER_MAX			0x02
484 	uint8_t control;	/* 01 */
485 
486 	uint16_t fw_options;	/* 02-03 */
487 #define	 FWOPT_HEARTBEAT_ENABLE		  0x1000
488 #define	 FWOPT_SESSION_MODE		  0x0040
489 #define	 FWOPT_INITIATOR_MODE		  0x0020
490 #define	 FWOPT_TARGET_MODE		  0x0010
491 #define	 FWOPT_ENABLE_CRBDB		  0x8000
492 
493 	uint16_t exec_throttle;	/* 04-05 */
494 	uint8_t zio_count;	/* 06 */
495 	uint8_t res0;	/* 07 */
496 	uint16_t eth_mtu_size;	/* 08-09 */
497 	uint16_t add_fw_options;	/* 0A-0B */
498 #define ADFWOPT_SERIALIZE_TASK_MGMT	0x0400
499 #define ADFWOPT_AUTOCONN_DISABLE	0x0002
500 
501 	uint8_t hb_interval;	/* 0C */
502 	uint8_t inst_num; /* 0D */
503 	uint16_t res1;		/* 0E-0F */
504 	uint16_t rqq_consumer_idx;	/* 10-11 */
505 	uint16_t compq_producer_idx;	/* 12-13 */
506 	uint16_t rqq_len;	/* 14-15 */
507 	uint16_t compq_len;	/* 16-17 */
508 	uint32_t rqq_addr_lo;	/* 18-1B */
509 	uint32_t rqq_addr_hi;	/* 1C-1F */
510 	uint32_t compq_addr_lo;	/* 20-23 */
511 	uint32_t compq_addr_hi;	/* 24-27 */
512 	uint32_t shdwreg_addr_lo;	/* 28-2B */
513 	uint32_t shdwreg_addr_hi;	/* 2C-2F */
514 
515 	uint16_t iscsi_opts;	/* 30-31 */
516 	uint16_t ipv4_tcp_opts;	/* 32-33 */
517 #define TCPOPT_DHCP_ENABLE		0x0200
518 	uint16_t ipv4_ip_opts;	/* 34-35 */
519 #define IPOPT_IPV4_PROTOCOL_ENABLE	0x8000
520 #define IPOPT_VLAN_TAGGING_ENABLE	0x2000
521 
522 	uint16_t iscsi_max_pdu_size;	/* 36-37 */
523 	uint8_t ipv4_tos;	/* 38 */
524 	uint8_t ipv4_ttl;	/* 39 */
525 	uint8_t acb_version;	/* 3A */
526 #define ACB_NOT_SUPPORTED		0x00
527 #define ACB_SUPPORTED			0x02 /* Capable of ACB Version 2
528 						Features */
529 
530 	uint8_t res2;	/* 3B */
531 	uint16_t def_timeout;	/* 3C-3D */
532 	uint16_t iscsi_fburst_len;	/* 3E-3F */
533 	uint16_t iscsi_def_time2wait;	/* 40-41 */
534 	uint16_t iscsi_def_time2retain;	/* 42-43 */
535 	uint16_t iscsi_max_outstnd_r2t;	/* 44-45 */
536 	uint16_t conn_ka_timeout;	/* 46-47 */
537 	uint16_t ipv4_port;	/* 48-49 */
538 	uint16_t iscsi_max_burst_len;	/* 4A-4B */
539 	uint32_t res5;		/* 4C-4F */
540 	uint8_t ipv4_addr[4];	/* 50-53 */
541 	uint16_t ipv4_vlan_tag;	/* 54-55 */
542 	uint8_t ipv4_addr_state;	/* 56 */
543 	uint8_t ipv4_cacheid;	/* 57 */
544 	uint8_t res6[8];	/* 58-5F */
545 	uint8_t ipv4_subnet[4];	/* 60-63 */
546 	uint8_t res7[12];	/* 64-6F */
547 	uint8_t ipv4_gw_addr[4];	/* 70-73 */
548 	uint8_t res8[0xc];	/* 74-7F */
549 	uint8_t pri_dns_srvr_ip[4];/* 80-83 */
550 	uint8_t sec_dns_srvr_ip[4];/* 84-87 */
551 	uint16_t min_eph_port;	/* 88-89 */
552 	uint16_t max_eph_port;	/* 8A-8B */
553 	uint8_t res9[4];	/* 8C-8F */
554 	uint8_t iscsi_alias[32];/* 90-AF */
555 	uint8_t res9_1[0x16];	/* B0-C5 */
556 	uint16_t tgt_portal_grp;/* C6-C7 */
557 	uint8_t abort_timer;	/* C8	 */
558 	uint8_t ipv4_tcp_wsf;	/* C9	 */
559 	uint8_t res10[6];	/* CA-CF */
560 	uint8_t ipv4_sec_ip_addr[4];	/* D0-D3 */
561 	uint8_t ipv4_dhcp_vid_len;	/* D4 */
562 	uint8_t ipv4_dhcp_vid[11];	/* D5-DF */
563 	uint8_t res11[20];	/* E0-F3 */
564 	uint8_t ipv4_dhcp_alt_cid_len;	/* F4 */
565 	uint8_t ipv4_dhcp_alt_cid[11];	/* F5-FF */
566 	uint8_t iscsi_name[224];	/* 100-1DF */
567 	uint8_t res12[32];	/* 1E0-1FF */
568 	uint32_t cookie;	/* 200-203 */
569 	uint16_t ipv6_port;	/* 204-205 */
570 	uint16_t ipv6_opts;	/* 206-207 */
571 #define IPV6_OPT_IPV6_PROTOCOL_ENABLE	0x8000
572 #define IPV6_OPT_VLAN_TAGGING_ENABLE	0x2000
573 
574 	uint16_t ipv6_addtl_opts;	/* 208-209 */
575 #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE	0x0002 /* Pri ACB
576 								  Only */
577 #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR		0x0001
578 
579 	uint16_t ipv6_tcp_opts;	/* 20A-20B */
580 	uint8_t ipv6_tcp_wsf;	/* 20C */
581 	uint16_t ipv6_flow_lbl;	/* 20D-20F */
582 	uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
583 	uint16_t ipv6_vlan_tag;	/* 220-221 */
584 	uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
585 	uint8_t ipv6_addr0_state;	/* 223 */
586 	uint8_t ipv6_addr1_state;	/* 224 */
587 #define IP_ADDRSTATE_UNCONFIGURED	0
588 #define IP_ADDRSTATE_INVALID		1
589 #define IP_ADDRSTATE_ACQUIRING		2
590 #define IP_ADDRSTATE_TENTATIVE		3
591 #define IP_ADDRSTATE_DEPRICATED		4
592 #define IP_ADDRSTATE_PREFERRED		5
593 #define IP_ADDRSTATE_DISABLING		6
594 
595 	uint8_t ipv6_dflt_rtr_state;    /* 225 */
596 #define IPV6_RTRSTATE_UNKNOWN                   0
597 #define IPV6_RTRSTATE_MANUAL                    1
598 #define IPV6_RTRSTATE_ADVERTISED                3
599 #define IPV6_RTRSTATE_STALE                     4
600 
601 	uint8_t ipv6_traffic_class;	/* 226 */
602 	uint8_t ipv6_hop_limit;	/* 227 */
603 	uint8_t ipv6_if_id[8];	/* 228-22F */
604 	uint8_t ipv6_addr0[16];	/* 230-23F */
605 	uint8_t ipv6_addr1[16];	/* 240-24F */
606 	uint32_t ipv6_nd_reach_time;	/* 250-253 */
607 	uint32_t ipv6_nd_rexmit_timer;	/* 254-257 */
608 	uint32_t ipv6_nd_stale_timeout;	/* 258-25B */
609 	uint8_t ipv6_dup_addr_detect_count;	/* 25C */
610 	uint8_t ipv6_cache_id;	/* 25D */
611 	uint8_t res13[18];	/* 25E-26F */
612 	uint32_t ipv6_gw_advrt_mtu;	/* 270-273 */
613 	uint8_t res14[140];	/* 274-2FF */
614 };
615 
616 #define IP_ADDR_COUNT	4 /* Total 4 IP address supported in one interface
617 			   * One IPv4, one IPv6 link local and 2 IPv6
618 			   */
619 
620 #define IP_STATE_MASK	0x0F000000
621 #define IP_STATE_SHIFT	24
622 
623 struct init_fw_ctrl_blk {
624 	struct addr_ctrl_blk pri;
625 /*	struct addr_ctrl_blk sec;*/
626 };
627 
628 #define PRIMARI_ACB		0
629 #define SECONDARY_ACB		1
630 
631 struct addr_ctrl_blk_def {
632 	uint8_t reserved1[1];	/* 00 */
633 	uint8_t control;	/* 01 */
634 	uint8_t reserved2[11];	/* 02-0C */
635 	uint8_t inst_num;	/* 0D */
636 	uint8_t reserved3[34];	/* 0E-2F */
637 	uint16_t iscsi_opts;	/* 30-31 */
638 	uint16_t ipv4_tcp_opts;	/* 32-33 */
639 	uint16_t ipv4_ip_opts;	/* 34-35 */
640 	uint16_t iscsi_max_pdu_size;	/* 36-37 */
641 	uint8_t ipv4_tos;	/* 38 */
642 	uint8_t ipv4_ttl;	/* 39 */
643 	uint8_t reserved4[2];	/* 3A-3B */
644 	uint16_t def_timeout;	/* 3C-3D */
645 	uint16_t iscsi_fburst_len;	/* 3E-3F */
646 	uint8_t reserved5[4];	/* 40-43 */
647 	uint16_t iscsi_max_outstnd_r2t;	/* 44-45 */
648 	uint8_t reserved6[2];	/* 46-47 */
649 	uint16_t ipv4_port;	/* 48-49 */
650 	uint16_t iscsi_max_burst_len;	/* 4A-4B */
651 	uint8_t reserved7[4];	/* 4C-4F */
652 	uint8_t ipv4_addr[4];	/* 50-53 */
653 	uint16_t ipv4_vlan_tag;	/* 54-55 */
654 	uint8_t ipv4_addr_state;	/* 56 */
655 	uint8_t ipv4_cacheid;	/* 57 */
656 	uint8_t reserved8[8];	/* 58-5F */
657 	uint8_t ipv4_subnet[4];	/* 60-63 */
658 	uint8_t reserved9[12];	/* 64-6F */
659 	uint8_t ipv4_gw_addr[4];	/* 70-73 */
660 	uint8_t reserved10[84];	/* 74-C7 */
661 	uint8_t abort_timer;	/* C8    */
662 	uint8_t ipv4_tcp_wsf;	/* C9    */
663 	uint8_t reserved11[10];	/* CA-D3 */
664 	uint8_t ipv4_dhcp_vid_len;	/* D4 */
665 	uint8_t ipv4_dhcp_vid[11];	/* D5-DF */
666 	uint8_t reserved12[20];	/* E0-F3 */
667 	uint8_t ipv4_dhcp_alt_cid_len;	/* F4 */
668 	uint8_t ipv4_dhcp_alt_cid[11];	/* F5-FF */
669 	uint8_t iscsi_name[224];	/* 100-1DF */
670 	uint8_t reserved13[32];	/* 1E0-1FF */
671 	uint32_t cookie;	/* 200-203 */
672 	uint16_t ipv6_port;	/* 204-205 */
673 	uint16_t ipv6_opts;	/* 206-207 */
674 	uint16_t ipv6_addtl_opts;	/* 208-209 */
675 	uint16_t ipv6_tcp_opts;		/* 20A-20B */
676 	uint8_t ipv6_tcp_wsf;		/* 20C */
677 	uint16_t ipv6_flow_lbl;		/* 20D-20F */
678 	uint8_t ipv6_dflt_rtr_addr[16];	/* 210-21F */
679 	uint16_t ipv6_vlan_tag;		/* 220-221 */
680 	uint8_t ipv6_lnk_lcl_addr_state;	/* 222 */
681 	uint8_t ipv6_addr0_state;	/* 223 */
682 	uint8_t ipv6_addr1_state;	/* 224 */
683 	uint8_t ipv6_dflt_rtr_state;	/* 225 */
684 	uint8_t ipv6_traffic_class;	/* 226 */
685 	uint8_t ipv6_hop_limit;		/* 227 */
686 	uint8_t ipv6_if_id[8];		/* 228-22F */
687 	uint8_t ipv6_addr0[16];		/* 230-23F */
688 	uint8_t ipv6_addr1[16];		/* 240-24F */
689 	uint32_t ipv6_nd_reach_time;	/* 250-253 */
690 	uint32_t ipv6_nd_rexmit_timer;	/* 254-257 */
691 	uint32_t ipv6_nd_stale_timeout;	/* 258-25B */
692 	uint8_t ipv6_dup_addr_detect_count;	/* 25C */
693 	uint8_t ipv6_cache_id;		/* 25D */
694 	uint8_t reserved14[18];		/* 25E-26F */
695 	uint32_t ipv6_gw_advrt_mtu;	/* 270-273 */
696 	uint8_t reserved15[140];	/* 274-2FF */
697 };
698 
699 /*************************************************************************/
700 
701 #define MAX_CHAP_ENTRIES_40XX	128
702 #define MAX_CHAP_ENTRIES_82XX	1024
703 #define MAX_RESRV_CHAP_IDX	3
704 #define FLASH_CHAP_OFFSET	0x06000000
705 
706 struct ql4_chap_table {
707 	uint16_t link;
708 	uint8_t flags;
709 	uint8_t secret_len;
710 #define MIN_CHAP_SECRET_LEN	12
711 #define MAX_CHAP_SECRET_LEN	100
712 	uint8_t secret[MAX_CHAP_SECRET_LEN];
713 #define MAX_CHAP_NAME_LEN	256
714 	uint8_t name[MAX_CHAP_NAME_LEN];
715 	uint16_t reserved;
716 #define CHAP_VALID_COOKIE	0x4092
717 #define CHAP_INVALID_COOKIE	0xFFEE
718 	uint16_t cookie;
719 };
720 
721 struct dev_db_entry {
722 	uint16_t options;	/* 00-01 */
723 #define DDB_OPT_DISC_SESSION  0x10
724 #define DDB_OPT_TARGET	      0x02 /* device is a target */
725 #define DDB_OPT_IPV6_DEVICE	0x100
726 #define DDB_OPT_AUTO_SENDTGTS_DISABLE		0x40
727 #define DDB_OPT_IPV6_NULL_LINK_LOCAL		0x800 /* post connection */
728 #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL	0x800 /* pre connection */
729 
730 	uint16_t exec_throttle;	/* 02-03 */
731 	uint16_t exec_count;	/* 04-05 */
732 	uint16_t res0;	/* 06-07 */
733 	uint16_t iscsi_options;	/* 08-09 */
734 	uint16_t tcp_options;	/* 0A-0B */
735 	uint16_t ip_options;	/* 0C-0D */
736 	uint16_t iscsi_max_rcv_data_seg_len;	/* 0E-0F */
737 #define BYTE_UNITS	512
738 	uint32_t res1;	/* 10-13 */
739 	uint16_t iscsi_max_snd_data_seg_len;	/* 14-15 */
740 	uint16_t iscsi_first_burst_len;	/* 16-17 */
741 	uint16_t iscsi_def_time2wait;	/* 18-19 */
742 	uint16_t iscsi_def_time2retain;	/* 1A-1B */
743 	uint16_t iscsi_max_outsnd_r2t;	/* 1C-1D */
744 	uint16_t ka_timeout;	/* 1E-1F */
745 	uint8_t isid[6];	/* 20-25 big-endian, must be converted
746 				 * to little-endian */
747 	uint16_t tsid;		/* 26-27 */
748 	uint16_t port;	/* 28-29 */
749 	uint16_t iscsi_max_burst_len;	/* 2A-2B */
750 	uint16_t def_timeout;	/* 2C-2D */
751 	uint16_t res2;	/* 2E-2F */
752 	uint8_t ip_addr[0x10];	/* 30-3F */
753 	uint8_t iscsi_alias[0x20];	/* 40-5F */
754 	uint8_t tgt_addr[0x20];	/* 60-7F */
755 	uint16_t mss;	/* 80-81 */
756 	uint16_t res3;	/* 82-83 */
757 	uint16_t lcl_port;	/* 84-85 */
758 	uint8_t ipv4_tos;	/* 86 */
759 	uint16_t ipv6_flow_lbl;	/* 87-89 */
760 	uint8_t res4[0x36];	/* 8A-BF */
761 	uint8_t iscsi_name[0xE0];	/* C0-19F : xxzzy Make this a
762 					 * pointer to a string so we
763 					 * don't have to reserve so
764 					 * much RAM */
765 	uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
766 	uint8_t res5[0x10];	/* 1B0-1BF */
767 	uint16_t ddb_link;	/* 1C0-1C1 */
768 	uint16_t chap_tbl_idx;	/* 1C2-1C3 */
769 	uint16_t tgt_portal_grp; /* 1C4-1C5 */
770 	uint8_t tcp_xmt_wsf;	/* 1C6 */
771 	uint8_t tcp_rcv_wsf;	/* 1C7 */
772 	uint32_t stat_sn;	/* 1C8-1CB */
773 	uint32_t exp_stat_sn;	/* 1CC-1CF */
774 	uint8_t res6[0x2b];	/* 1D0-1FB */
775 #define DDB_VALID_COOKIE	0x9034
776 	uint16_t cookie;	/* 1FC-1FD */
777 	uint16_t len;		/* 1FE-1FF */
778 };
779 
780 /*************************************************************************/
781 
782 /* Flash definitions */
783 
784 #define FLASH_OFFSET_SYS_INFO	0x02000000
785 #define FLASH_DEFAULTBLOCKSIZE	0x20000
786 #define FLASH_EOF_OFFSET	(FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
787 							    * for EOF
788 							    * signature */
789 #define FLASH_RAW_ACCESS_ADDR	0x8e000000
790 
791 #define BOOT_PARAM_OFFSET_PORT0 0x3b0
792 #define BOOT_PARAM_OFFSET_PORT1 0x7b0
793 
794 #define FLASH_OFFSET_DB_INFO	0x05000000
795 #define FLASH_OFFSET_DB_END	(FLASH_OFFSET_DB_INFO + 0x7fff)
796 
797 
798 struct sys_info_phys_addr {
799 	uint8_t address[6];	/* 00-05 */
800 	uint8_t filler[2];	/* 06-07 */
801 };
802 
803 struct flash_sys_info {
804 	uint32_t cookie;	/* 00-03 */
805 	uint32_t physAddrCount; /* 04-07 */
806 	struct sys_info_phys_addr physAddr[4]; /* 08-27 */
807 	uint8_t vendorId[128];	/* 28-A7 */
808 	uint8_t productId[128]; /* A8-127 */
809 	uint32_t serialNumber;	/* 128-12B */
810 
811 	/*  PCI Configuration values */
812 	uint32_t pciDeviceVendor;	/* 12C-12F */
813 	uint32_t pciDeviceId;	/* 130-133 */
814 	uint32_t pciSubsysVendor;	/* 134-137 */
815 	uint32_t pciSubsysId;	/* 138-13B */
816 
817 	/*  This validates version 1. */
818 	uint32_t crumbs;	/* 13C-13F */
819 
820 	uint32_t enterpriseNumber;	/* 140-143 */
821 
822 	uint32_t mtu;		/* 144-147 */
823 	uint32_t reserved0;	/* 148-14b */
824 	uint32_t crumbs2;	/* 14c-14f */
825 	uint8_t acSerialNumber[16];	/* 150-15f */
826 	uint32_t crumbs3;	/* 160-16f */
827 
828 	/* Leave this last in the struct so it is declared invalid if
829 	 * any new items are added.
830 	 */
831 	uint32_t reserved1[39]; /* 170-1ff */
832 };	/* 200 */
833 
834 struct mbx_sys_info {
835 	uint8_t board_id_str[16];   /*  0-f  Keep board ID string first */
836 				/* in this structure for GUI. */
837 	uint16_t board_id;	/* 10-11 board ID code */
838 	uint16_t phys_port_cnt;	/* 12-13 number of physical network ports */
839 	uint16_t port_num;	/* 14-15 network port for this PCI function */
840 				/* (port 0 is first port) */
841 	uint8_t mac_addr[6];	/* 16-1b MAC address for this PCI function */
842 	uint32_t iscsi_pci_func_cnt;  /* 1c-1f number of iSCSI PCI functions */
843 	uint32_t pci_func;	      /* 20-23 this PCI function */
844 	unsigned char serial_number[16];  /* 24-33 serial number string */
845 	uint8_t reserved[12];		  /* 34-3f */
846 };
847 
848 struct about_fw_info {
849 	uint16_t fw_major;		/* 00 - 01 */
850 	uint16_t fw_minor;		/* 02 - 03 */
851 	uint16_t fw_patch;		/* 04 - 05 */
852 	uint16_t fw_build;		/* 06 - 07 */
853 	uint8_t fw_build_date[16];	/* 08 - 17 ASCII String */
854 	uint8_t fw_build_time[16];	/* 18 - 27 ASCII String */
855 	uint8_t fw_build_user[16];	/* 28 - 37 ASCII String */
856 	uint16_t fw_load_source;	/* 38 - 39 */
857 					/* 1 = Flash Primary,
858 					   2 = Flash Secondary,
859 					   3 = Host Download
860 					*/
861 	uint8_t reserved1[6];		/* 3A - 3F */
862 	uint16_t iscsi_major;		/* 40 - 41 */
863 	uint16_t iscsi_minor;		/* 42 - 43 */
864 	uint16_t bootload_major;	/* 44 - 45 */
865 	uint16_t bootload_minor;	/* 46 - 47 */
866 	uint16_t bootload_patch;	/* 48 - 49 */
867 	uint16_t bootload_build;	/* 4A - 4B */
868 	uint8_t reserved2[180];		/* 4C - FF */
869 };
870 
871 struct crash_record {
872 	uint16_t fw_major_version;	/* 00 - 01 */
873 	uint16_t fw_minor_version;	/* 02 - 03 */
874 	uint16_t fw_patch_version;	/* 04 - 05 */
875 	uint16_t fw_build_version;	/* 06 - 07 */
876 
877 	uint8_t build_date[16]; /* 08 - 17 */
878 	uint8_t build_time[16]; /* 18 - 27 */
879 	uint8_t build_user[16]; /* 28 - 37 */
880 	uint8_t card_serial_num[16];	/* 38 - 47 */
881 
882 	uint32_t time_of_crash_in_secs; /* 48 - 4B */
883 	uint32_t time_of_crash_in_ms;	/* 4C - 4F */
884 
885 	uint16_t out_RISC_sd_num_frames;	/* 50 - 51 */
886 	uint16_t OAP_sd_num_words;	/* 52 - 53 */
887 	uint16_t IAP_sd_num_frames;	/* 54 - 55 */
888 	uint16_t in_RISC_sd_num_words;	/* 56 - 57 */
889 
890 	uint8_t reserved1[28];	/* 58 - 7F */
891 
892 	uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
893 	uint8_t in_RISC_reg_dump[256];	/*180 -27F */
894 	uint8_t in_out_RISC_stack_dump[0];	/*280 - ??? */
895 };
896 
897 struct conn_event_log_entry {
898 #define MAX_CONN_EVENT_LOG_ENTRIES	100
899 	uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
900 	uint32_t timestamp_ms;	/* 04 - 07 milliseconds since boot */
901 	uint16_t device_index;	/* 08 - 09  */
902 	uint16_t fw_conn_state; /* 0A - 0B  */
903 	uint8_t event_type;	/* 0C - 0C  */
904 	uint8_t error_code;	/* 0D - 0D  */
905 	uint16_t error_code_detail;	/* 0E - 0F  */
906 	uint8_t num_consecutive_events; /* 10 - 10  */
907 	uint8_t rsvd[3];	/* 11 - 13  */
908 };
909 
910 /*************************************************************************
911  *
912  *				IOCB Commands Structures and Definitions
913  *
914  *************************************************************************/
915 #define IOCB_MAX_CDB_LEN	    16	/* Bytes in a CBD */
916 #define IOCB_MAX_SENSEDATA_LEN	    32	/* Bytes of sense data */
917 #define IOCB_MAX_EXT_SENSEDATA_LEN  60  /* Bytes of extended sense data */
918 
919 /* IOCB header structure */
920 struct qla4_header {
921 	uint8_t entryType;
922 #define ET_STATUS		 0x03
923 #define ET_MARKER		 0x04
924 #define ET_CONT_T1		 0x0A
925 #define ET_STATUS_CONTINUATION	 0x10
926 #define ET_CMND_T3		 0x19
927 #define ET_PASSTHRU0		 0x3A
928 #define ET_PASSTHRU_STATUS	 0x3C
929 #define ET_MBOX_CMD		0x38
930 #define ET_MBOX_STATUS		0x39
931 
932 	uint8_t entryStatus;
933 	uint8_t systemDefined;
934 #define SD_ISCSI_PDU	0x01
935 	uint8_t entryCount;
936 
937 	/* SyetemDefined definition */
938 };
939 
940 /* Generic queue entry structure*/
941 struct queue_entry {
942 	uint8_t data[60];
943 	uint32_t signature;
944 
945 };
946 
947 /* 64 bit addressing segment counts*/
948 
949 #define COMMAND_SEG_A64	  1
950 #define CONTINUE_SEG_A64  5
951 
952 /* 64 bit addressing segment definition*/
953 
954 struct data_seg_a64 {
955 	struct {
956 		uint32_t addrLow;
957 		uint32_t addrHigh;
958 
959 	} base;
960 
961 	uint32_t count;
962 
963 };
964 
965 /* Command Type 3 entry structure*/
966 
967 struct command_t3_entry {
968 	struct qla4_header hdr;	/* 00-03 */
969 
970 	uint32_t handle;	/* 04-07 */
971 	uint16_t target;	/* 08-09 */
972 	uint16_t connection_id; /* 0A-0B */
973 
974 	uint8_t control_flags;	/* 0C */
975 
976 	/* data direction  (bits 5-6) */
977 #define CF_WRITE		0x20
978 #define CF_READ			0x40
979 #define CF_NO_DATA		0x00
980 
981 	/* task attributes (bits 2-0) */
982 #define CF_HEAD_TAG		0x03
983 #define CF_ORDERED_TAG		0x02
984 #define CF_SIMPLE_TAG		0x01
985 
986 	/* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
987 	 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
988 	 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
989 	 * PROPERLY.
990 	 */
991 	uint8_t state_flags;	/* 0D */
992 	uint8_t cmdRefNum;	/* 0E */
993 	uint8_t reserved1;	/* 0F */
994 	uint8_t cdb[IOCB_MAX_CDB_LEN];	/* 10-1F */
995 	struct scsi_lun lun;	/* FCP LUN (BE). */
996 	uint32_t cmdSeqNum;	/* 28-2B */
997 	uint16_t timeout;	/* 2C-2D */
998 	uint16_t dataSegCnt;	/* 2E-2F */
999 	uint32_t ttlByteCnt;	/* 30-33 */
1000 	struct data_seg_a64 dataseg[COMMAND_SEG_A64];	/* 34-3F */
1001 
1002 };
1003 
1004 
1005 /* Continuation Type 1 entry structure*/
1006 struct continuation_t1_entry {
1007 	struct qla4_header hdr;
1008 
1009 	struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
1010 
1011 };
1012 
1013 /* Parameterize for 64 or 32 bits */
1014 #define COMMAND_SEG	COMMAND_SEG_A64
1015 #define CONTINUE_SEG	CONTINUE_SEG_A64
1016 
1017 #define ET_COMMAND	ET_CMND_T3
1018 #define ET_CONTINUE	ET_CONT_T1
1019 
1020 /* Marker entry structure*/
1021 struct qla4_marker_entry {
1022 	struct qla4_header hdr;	/* 00-03 */
1023 
1024 	uint32_t system_defined; /* 04-07 */
1025 	uint16_t target;	/* 08-09 */
1026 	uint16_t modifier;	/* 0A-0B */
1027 #define MM_LUN_RESET		0
1028 #define MM_TGT_WARM_RESET	1
1029 
1030 	uint16_t flags;		/* 0C-0D */
1031 	uint16_t reserved1;	/* 0E-0F */
1032 	struct scsi_lun lun;	/* FCP LUN (BE). */
1033 	uint64_t reserved2;	/* 18-1F */
1034 	uint64_t reserved3;	/* 20-27 */
1035 	uint64_t reserved4;	/* 28-2F */
1036 	uint64_t reserved5;	/* 30-37 */
1037 	uint64_t reserved6;	/* 38-3F */
1038 };
1039 
1040 /* Status entry structure*/
1041 struct status_entry {
1042 	struct qla4_header hdr;	/* 00-03 */
1043 
1044 	uint32_t handle;	/* 04-07 */
1045 
1046 	uint8_t scsiStatus;	/* 08 */
1047 #define SCSI_CHECK_CONDITION		  0x02
1048 
1049 	uint8_t iscsiFlags;	/* 09 */
1050 #define ISCSI_FLAG_RESIDUAL_UNDER	  0x02
1051 #define ISCSI_FLAG_RESIDUAL_OVER	  0x04
1052 
1053 	uint8_t iscsiResponse;	/* 0A */
1054 
1055 	uint8_t completionStatus;	/* 0B */
1056 #define SCS_COMPLETE			  0x00
1057 #define SCS_INCOMPLETE			  0x01
1058 #define SCS_RESET_OCCURRED		  0x04
1059 #define SCS_ABORTED			  0x05
1060 #define SCS_TIMEOUT			  0x06
1061 #define SCS_DATA_OVERRUN		  0x07
1062 #define SCS_DATA_UNDERRUN		  0x15
1063 #define SCS_QUEUE_FULL			  0x1C
1064 #define SCS_DEVICE_UNAVAILABLE		  0x28
1065 #define SCS_DEVICE_LOGGED_OUT		  0x29
1066 
1067 	uint8_t reserved1;	/* 0C */
1068 
1069 	/* state_flags MUST be at the same location as state_flags in
1070 	 * the Command_T3/4_Entry */
1071 	uint8_t state_flags;	/* 0D */
1072 
1073 	uint16_t senseDataByteCnt;	/* 0E-0F */
1074 	uint32_t residualByteCnt;	/* 10-13 */
1075 	uint32_t bidiResidualByteCnt;	/* 14-17 */
1076 	uint32_t expSeqNum;	/* 18-1B */
1077 	uint32_t maxCmdSeqNum;	/* 1C-1F */
1078 	uint8_t senseData[IOCB_MAX_SENSEDATA_LEN];	/* 20-3F */
1079 
1080 };
1081 
1082 /* Status Continuation entry */
1083 struct status_cont_entry {
1084        struct qla4_header hdr; /* 00-03 */
1085        uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
1086 };
1087 
1088 struct passthru0 {
1089 	struct qla4_header hdr;		       /* 00-03 */
1090 	uint32_t handle;	/* 04-07 */
1091 	uint16_t target;	/* 08-09 */
1092 	uint16_t connection_id;	/* 0A-0B */
1093 #define ISNS_DEFAULT_SERVER_CONN_ID	((uint16_t)0x8000)
1094 
1095 	uint16_t control_flags;	/* 0C-0D */
1096 #define PT_FLAG_ETHERNET_FRAME		0x8000
1097 #define PT_FLAG_ISNS_PDU		0x8000
1098 #define PT_FLAG_SEND_BUFFER		0x0200
1099 #define PT_FLAG_WAIT_4_RESPONSE		0x0100
1100 #define PT_FLAG_ISCSI_PDU		0x1000
1101 
1102 	uint16_t timeout;	/* 0E-0F */
1103 #define PT_DEFAULT_TIMEOUT		30 /* seconds */
1104 
1105 	struct data_seg_a64 out_dsd;    /* 10-1B */
1106 	uint32_t res1;		/* 1C-1F */
1107 	struct data_seg_a64 in_dsd;     /* 20-2B */
1108 	uint8_t res2[20];	/* 2C-3F */
1109 };
1110 
1111 struct passthru_status {
1112 	struct qla4_header hdr;		       /* 00-03 */
1113 	uint32_t handle;	/* 04-07 */
1114 	uint16_t target;	/* 08-09 */
1115 	uint16_t connectionID;	/* 0A-0B */
1116 
1117 	uint8_t completionStatus;	/* 0C */
1118 #define PASSTHRU_STATUS_COMPLETE		0x01
1119 
1120 	uint8_t residualFlags;	/* 0D */
1121 
1122 	uint16_t timeout;	/* 0E-0F */
1123 	uint16_t portNumber;	/* 10-11 */
1124 	uint8_t res1[10];	/* 12-1B */
1125 	uint32_t outResidual;	/* 1C-1F */
1126 	uint8_t res2[12];	/* 20-2B */
1127 	uint32_t inResidual;	/* 2C-2F */
1128 	uint8_t res4[16];	/* 30-3F */
1129 };
1130 
1131 struct mbox_cmd_iocb {
1132 	struct qla4_header hdr;	/* 00-03 */
1133 	uint32_t handle;	/* 04-07 */
1134 	uint32_t in_mbox[8];	/* 08-25 */
1135 	uint32_t res1[6];	/* 26-3F */
1136 };
1137 
1138 struct mbox_status_iocb {
1139 	struct qla4_header hdr;	/* 00-03 */
1140 	uint32_t handle;	/* 04-07 */
1141 	uint32_t out_mbox[8];	/* 08-25 */
1142 	uint32_t res1[6];	/* 26-3F */
1143 };
1144 
1145 /*
1146  * ISP queue - response queue entry definition.
1147  */
1148 struct response {
1149 	uint8_t data[60];
1150 	uint32_t signature;
1151 #define RESPONSE_PROCESSED	0xDEADDEAD	/* Signature */
1152 };
1153 
1154 struct ql_iscsi_stats {
1155 	uint8_t reserved1[656]; /* 0000-028F */
1156 	uint32_t tx_cmd_pdu; /* 0290-0293 */
1157 	uint32_t tx_resp_pdu; /* 0294-0297 */
1158 	uint32_t rx_cmd_pdu; /* 0298-029B */
1159 	uint32_t rx_resp_pdu; /* 029C-029F */
1160 
1161 	uint64_t tx_data_octets; /* 02A0-02A7 */
1162 	uint64_t rx_data_octets; /* 02A8-02AF */
1163 
1164 	uint32_t hdr_digest_err; /* 02B0–02B3 */
1165 	uint32_t data_digest_err; /* 02B4–02B7 */
1166 	uint32_t conn_timeout_err; /* 02B8–02BB */
1167 	uint32_t framing_err; /* 02BC–02BF */
1168 
1169 	uint32_t tx_nopout_pdus; /* 02C0–02C3 */
1170 	uint32_t tx_scsi_cmd_pdus;  /* 02C4–02C7 */
1171 	uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */
1172 	uint32_t tx_login_cmd_pdus; /* 02CC–02CF */
1173 	uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */
1174 	uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */
1175 	uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */
1176 	uint32_t tx_snack_req_pdus; /* 02DC–02DF */
1177 
1178 	uint32_t rx_nopin_pdus; /* 02E0–02E3 */
1179 	uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */
1180 	uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */
1181 	uint32_t rx_login_resp_pdus; /* 02EC–02EF */
1182 	uint32_t rx_text_resp_pdus; /* 02F0–02F3 */
1183 	uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */
1184 	uint32_t rx_logout_resp_pdus; /* 02F8–02FB */
1185 
1186 	uint32_t rx_r2t_pdus; /* 02FC–02FF */
1187 	uint32_t rx_async_pdus; /* 0300–0303 */
1188 	uint32_t rx_reject_pdus; /* 0304–0307 */
1189 
1190 	uint8_t reserved2[264]; /* 0x0308 - 0x040F */
1191 };
1192 
1193 #endif /*  _QLA4X_FW_H */
1194