1 /* mb-regs.h: motherboard registers 2 * 3 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef _ASM_MB_REGS_H 13 #define _ASM_MB_REGS_H 14 15 #include <asm/cpu-irqs.h> 16 #include <asm/sections.h> 17 #include <asm/mem-layout.h> 18 19 #ifndef __ASSEMBLY__ 20 /* gcc builtins, annotated */ 21 22 unsigned long __builtin_read8(volatile void __iomem *); 23 unsigned long __builtin_read16(volatile void __iomem *); 24 unsigned long __builtin_read32(volatile void __iomem *); 25 void __builtin_write8(volatile void __iomem *, unsigned char); 26 void __builtin_write16(volatile void __iomem *, unsigned short); 27 void __builtin_write32(volatile void __iomem *, unsigned long); 28 #endif 29 30 #define __region_IO KERNEL_IO_START /* the region from 0xe0000000 to 0xffffffff has suitable 31 * protection laid over the top for use in memory-mapped 32 * I/O 33 */ 34 35 #define __region_CS0 0xff000000 /* Boot ROMs area */ 36 37 #ifdef CONFIG_MB93091_VDK 38 /* 39 * VDK motherboard and CPU card specific stuff 40 */ 41 42 #include <asm/mb93091-fpga-irqs.h> 43 44 #define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0 45 #define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1 46 47 #define __region_CS2 0xe0000000 /* SLBUS/PCI I/O space */ 48 #define __region_CS2_M 0x0fffffff /* mask */ 49 #define __region_CS2_C 0x00000000 /* control */ 50 #define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */ 51 #define __region_CS5_M 0x00ffffff 52 #define __region_CS5_C 0x00010000 53 #define __region_CS7 0xf1000000 /* CB70 CPU-card PCMCIA port I/O space */ 54 #define __region_CS7_M 0x00ffffff 55 #define __region_CS7_C 0x00410701 56 #define __region_CS1 0xfc000000 /* SLBUS/PCI bridge control registers */ 57 #define __region_CS1_M 0x000fffff 58 #define __region_CS1_C 0x00000000 59 #define __region_CS6 0xfc100000 /* CB70 CPU-card DM9000 LAN I/O space */ 60 #define __region_CS6_M 0x000fffff 61 #define __region_CS6_C 0x00400707 62 #define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */ 63 #define __region_CS3_M 0x000fffff 64 #define __region_CS3_C 0xc8100000 65 #define __region_CS4 0xfd000000 /* CB70 CPU-card extra flash space */ 66 #define __region_CS4_M 0x00ffffff 67 #define __region_CS4_C 0x00000f07 68 69 #define __region_PCI_IO (__region_CS2 + 0x04000000UL) 70 #define __region_PCI_MEM (__region_CS2 + 0x08000000UL) 71 #define __flush_PCI_writes() \ 72 do { \ 73 __builtin_write8((volatile void __iomem *) __region_PCI_MEM, 0); \ 74 } while(0) 75 76 #define __is_PCI_IO(addr) \ 77 (((unsigned long)(addr) >> 24) - (__region_PCI_IO >> 24) < (0x04000000UL >> 24)) 78 79 #define __is_PCI_MEM(addr) \ 80 ((unsigned long)(addr) - __region_PCI_MEM < 0x08000000UL) 81 82 #define __is_PCI_addr(addr) \ 83 ((unsigned long)(addr) - __region_PCI_IO < 0x0c000000UL) 84 85 #define __get_CLKSW() ({ *(volatile unsigned long *)(__region_CS2 + 0x0130000cUL) & 0xffUL; }) 86 #define __get_CLKIN() (__get_CLKSW() * 125U * 100000U / 24U) 87 88 #ifndef __ASSEMBLY__ 89 extern int __nongprelbss mb93090_mb00_detected; 90 #endif 91 92 #define __addr_LEDS() (__region_CS2 + 0x01200004UL) 93 #ifdef CONFIG_MB93090_MB00 94 #define __set_LEDS(X) \ 95 do { \ 96 if (mb93090_mb00_detected) \ 97 __builtin_write32((void __iomem *) __addr_LEDS(), ~(X)); \ 98 } while (0) 99 #else 100 #define __set_LEDS(X) 101 #endif 102 103 #define __addr_LCD() (__region_CS2 + 0x01200008UL) 104 #define __get_LCD(B) __builtin_read32((volatile void __iomem *) (B)) 105 #define __set_LCD(B,X) __builtin_write32((volatile void __iomem *) (B), (X)) 106 107 #define LCD_D 0x000000ff /* LCD data bus */ 108 #define LCD_RW 0x00000100 /* LCD R/W signal */ 109 #define LCD_RS 0x00000200 /* LCD Register Select */ 110 #define LCD_E 0x00000400 /* LCD Start Enable Signal */ 111 112 #define LCD_CMD_CLEAR (LCD_E|0x001) 113 #define LCD_CMD_HOME (LCD_E|0x002) 114 #define LCD_CMD_CURSOR_INC (LCD_E|0x004) 115 #define LCD_CMD_SCROLL_INC (LCD_E|0x005) 116 #define LCD_CMD_CURSOR_DEC (LCD_E|0x006) 117 #define LCD_CMD_SCROLL_DEC (LCD_E|0x007) 118 #define LCD_CMD_OFF (LCD_E|0x008) 119 #define LCD_CMD_ON(CRSR,BLINK) (LCD_E|0x00c|(CRSR<<1)|BLINK) 120 #define LCD_CMD_CURSOR_MOVE_L (LCD_E|0x010) 121 #define LCD_CMD_CURSOR_MOVE_R (LCD_E|0x014) 122 #define LCD_CMD_DISPLAY_SHIFT_L (LCD_E|0x018) 123 #define LCD_CMD_DISPLAY_SHIFT_R (LCD_E|0x01c) 124 #define LCD_CMD_FUNCSET(DL,N,F) (LCD_E|0x020|(DL<<4)|(N<<3)|(F<<2)) 125 #define LCD_CMD_SET_CG_ADDR(X) (LCD_E|0x040|X) 126 #define LCD_CMD_SET_DD_ADDR(X) (LCD_E|0x080|X) 127 #define LCD_CMD_READ_BUSY (LCD_E|LCD_RW) 128 #define LCD_DATA_WRITE(X) (LCD_E|LCD_RS|(X)) 129 #define LCD_DATA_READ (LCD_E|LCD_RS|LCD_RW) 130 131 #else 132 /* 133 * PDK unit specific stuff 134 */ 135 136 #include <asm/mb93093-fpga-irqs.h> 137 138 #define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0 139 #define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1 140 141 #define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */ 142 #define __region_CS5_M 0x00ffffff /* mask */ 143 #define __region_CS5_C 0x00010000 /* control */ 144 #define __region_CS2 0x20000000 /* FPGA registers */ 145 #define __region_CS2_M 0x000fffff 146 #define __region_CS2_C 0x00000000 147 #define __region_CS1 0xfc100000 /* LAN registers */ 148 #define __region_CS1_M 0x000fffff 149 #define __region_CS1_C 0x00010404 150 #define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */ 151 #define __region_CS3_M 0x000fffff 152 #define __region_CS3_C 0xc8000000 153 #define __region_CS4 0xfd000000 /* extra ROMs area */ 154 #define __region_CS4_M 0x00ffffff 155 #define __region_CS4_C 0x00000f07 156 157 #define __region_CS6 0xfe000000 /* not used - hide behind CPU resource I/O regs */ 158 #define __region_CS6_M 0x000fffff 159 #define __region_CS6_C 0x00000f07 160 #define __region_CS7 0xfe000000 /* not used - hide behind CPU resource I/O regs */ 161 #define __region_CS7_M 0x000fffff 162 #define __region_CS7_C 0x00000f07 163 164 #define __is_PCI_IO(addr) 0 /* no PCI */ 165 #define __is_PCI_MEM(addr) 0 166 #define __is_PCI_addr(addr) 0 167 #define __region_PCI_IO 0 168 #define __region_PCI_MEM 0 169 #define __flush_PCI_writes() do { } while(0) 170 171 #define __get_CLKSW() 0UL 172 #define __get_CLKIN() 66000000UL 173 174 #define __addr_LEDS() (__region_CS2 + 0x00000023UL) 175 #define __set_LEDS(X) __builtin_write8((volatile void __iomem *) __addr_LEDS(), (X)) 176 177 #define __addr_FPGATR() (__region_CS2 + 0x00000030UL) 178 #define __set_FPGATR(X) __builtin_write32((volatile void __iomem *) __addr_FPGATR(), (X)) 179 #define __get_FPGATR() __builtin_read32((volatile void __iomem *) __addr_FPGATR()) 180 181 #define MB93093_FPGA_FPGATR_AUDIO_CLK 0x00000003 182 183 #define __set_FPGATR_AUDIO_CLK(V) \ 184 __set_FPGATR((__get_FPGATR() & ~MB93093_FPGA_FPGATR_AUDIO_CLK) | (V)) 185 186 #define MB93093_FPGA_FPGATR_AUDIO_CLK_OFF 0x0 187 #define MB93093_FPGA_FPGATR_AUDIO_CLK_11MHz 0x1 188 #define MB93093_FPGA_FPGATR_AUDIO_CLK_12MHz 0x2 189 #define MB93093_FPGA_FPGATR_AUDIO_CLK_02MHz 0x3 190 191 #define MB93093_FPGA_SWR_PUSHSWMASK (0x1F<<26) 192 #define MB93093_FPGA_SWR_PUSHSW4 (1<<29) 193 194 #define __addr_FPGA_SWR ((volatile void __iomem *)(__region_CS2 + 0x28UL)) 195 #define __get_FPGA_PUSHSW1_5() (__builtin_read32(__addr_FPGA_SWR) & MB93093_FPGA_SWR_PUSHSWMASK) 196 197 198 #endif 199 200 #endif /* _ASM_MB_REGS_H */ 201